Posts Tagged ‘VIP’

3 May, 2017

VIP: Accelerating SoC Design Verification

Your SoC designs have grown more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world.  With each of these interconnect methods, design IP blocks support a faster SoC design process.  However, being an expert on each of the interconnect methods or protocols is not likely leading to protracted SoC verification schedules, reduced design productivity and exposing your designs to bugs that might only be found when in use by the end consumer.

These complex industry standard interfaces can be more rapidly verified in your SoC design with the use of Verification IP (VIP).  You will still need to understand the specific protocols, but when VIP is used you improve design quality and reduce verification time which allows you to hit aggressive time-to-market goals.

To foster industry discussion and share best practices we invite you to the Silicon Valley Design & Verification IP Forum 2017.  The forum brings DIP and VIP designers, integrators and partners together to learn the latest in IP-driven verification trends and solutions.  The forum will have presentations on numerous protocols include MIPI CSI-2, USB 3.1, PCIe Gen 4, DDR & Flash memory and IEEE 802.3 Ethernet PHY.

The day will be full of presentation from those protocol experts and will start with an opening keynote from Mentor’s verification chief scientist, Harry Foster. Harry will explore “Conquering the New IP Economy” in his keynote.  Several of our Questa Vanguard Partners who supply design IP will also be present to show how all this works together to accelerate SoC design verification closure.

Silicon Valley Design & Verification IP Forum 2017 Details

Date: May 9, 2017
Time: 8:30 a.m. – 4:15 p.m. PT
Location: San Jose, CA USA
Register: Click here.

The event is free of charge to qualified registrants and includes lunch.  The lunch keynote will be presented by Niraj Mathur, VP High Speed Interface Products, Rambus.  Niraj will share is 20 years of experience in advanced SoC & IP design, verification, software and cross-functional, global engineering team challenges.

I look forward to seeing your there!

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16 November, 2015

Thus far we have talked about the importance of having a VIP which is easy to connect to the DUT in part 1 and having the flexibility to configure the VIP as per your requirements and use the built-in or pre-packaged sequences in part 2. In this final part of the series, we will talk about the various built-in features of a VIP which helps with your debug.

If you have a UVM based testbench with one or multiple VIPs, your testbench could be more complex than your DUT and debugging this environment could be a major challenge. Debugging UVM VIP based environments could be thought of having 3 layers:

  1. UVM’s built-in debug mechanism
  2. Simulator with Class Based Debug
  3. VIP with built-in debug features

These are some of the features that Mentor’s VIP provide as built-in debug mechanisms:

VIP Query Commands:

These query commands provide the ability to query the state of the VIP in the testbench at any given time in a batch or CLI mode to get the summary of the VIP or the current configuration of the VIP and prints it to the simulation log.


For example, in PCI Express, the VIP can output B.A.R. information, to show the addressing set up in the system (above) as well as the PCIe configuration space showing the device capabilities (below).


Error Messaging & Reporting:

Error Messaging is very important as this is the first thing the user checks while debugging. The error messages have proper encoding to differentiate between methodology errors, protocol errors and infrastructure errors. It also provides the flexibility of customizing the report message and logging mechanism.



While the VIP is running, a built-in set of assertions check for any protocol violations to verify compliance with the specification.  When these fire, they result in a message that can be printed to the transcript, or piped through the UVM reporting mechanism.  The text of the message include the interface instance name, a description of what went wrong and a reference back to the specification to help when looking up further details.  Each assertion error is configurable and can be enabled or disabled and have its severity level changed.

 Protocol Debug:

Another important aspect of the VIP is to help with protocol debug.  Mentor VIP is transaction based, and those transactions are available for creating stimulus as well as for analysis, where they can be used in the testbench for scoreboarding and coverage collection.

Transaction Logging:

Transactions can also be logged to a text file, printed out via the standard UVM print mechanism, or output to a tracker file by a provided analysis component. Following is the sample print of transaction log file that shows attribute information that is printed along with the format:
   AXI Clk Cycle = 10.00 ns; AXI Clk Frequency = 100.00 MHz; Data bus width = 32 bits


Here, transaction wise data is printed in the log file which includes whether transaction is read or write, ID of transaction, starting address, accept time of address phase, data of each beat, write strobes, data burst accept time, response of transaction, response phase accept time, length of transaction, burst type, and size of burst.

The VIP can also output text based log, or tracker files.  This can typically be done at both the protocol level, and also at the symbol level for protocols such as PCI Express to help debug link training, or other state machines.  Here we can see the symbols for an OS PLP transmission, a TLP transmission and a DLLP transmission on the bus.


Transaction Linking:


Just logging transactions isn’t sufficient while debugging a cache coherent interconnect (CCI). An originating master request transaction results in snoops to other cached masters and a slave access as needed. While debugging system level stimulus, it becomes difficult to identify which all snoop transactions are related to a specific originating request. A Cache Coherency Interconnect Monitor (CCIM), helps overcome this debugging issue by providing a transaction linking component that connects to all the interfaces around a CCI. CCIM provides a top-level parent sequence item that links to all related child sequence items, such as originating request, snoop to cached masters, and slave access.

Protocol Stack Debug:


Along with the transactions, the VIP also records relationship information, relations to other transactions through the protocol stack and also to the signals themselves.  This allows you to quickly move from transaction, to signal level debug, and highlight not just which signals, but also the time at which those signals participated in any given transaction.

I hope this series has provided you with few insights into what makes a VIP easy to instantiate, connect, configure and start driving stimulus. I would really like to hear about your VIP usage experiences.

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25 October, 2015

Verification Academy Brings “UVM Live” to the Santa Clara Convention Center

Uvm logoFor everyone involved in the functional verification of electronic systems, you know about the Universal Verification Methodology (UVM) and are probably using it in one fashion or another.  And if you have been reading this blog, you have undoubtedly seen blogs by Harry Foster on the adoption and use of UVM by the FPGA and ASIC/SoC community.  It has clearly become the world’s most popular and accepted verification methodology.  It is odd to point out that with this popularity, there has not been a UVM-only event to bring UVM users together this year.  We believe it is time for UVM users to come together to explore its use and share productivity tips and tricks with each other.  You are invited to register and attend.  The details of the event are:

          Event: UVM Forum – Verification Academy Live Seminar
          Location: Santa Clara Convention Center, Santa Clara, CA USA
          Date: 17 November 2015
          Time: 8:30 a.m. – 4:00 p.m. PT
          More Information & Agenda: Click Here
          Register: Click Here

Experts Learn Something New

If you are an UVM Expert, and already know just about everything about UVM, you might be interested in some new topics that will be introduced and expanded upon.  Here are four:

The first is UVM Framework.  UVM Framework supports reuse across projects, sites and companies from block to chip to system for both simulation and emulation.  Those using it have seen at least a four week reduction in verification product schedules.

The second is Verification IP.  VIP can help you overcome your IP verification challenges.  One session will explore integrating VIP into a UVM environment with examples based on protocols such as AMBA®, MIPI® and PCI Express®.  If you are not an expert on a specific protocol, you can use VIP to drive stimulus and verify protocol compliance for you.

The third is Automating Scenario-Level UVM Test with Portable Stimulus.  In this session you will learn to rise above the transaction level to make scenario creation more productive.  You will learn how to leverage lower-level descriptions, such as sequence items, into larger scenarios.  You will learn how to leverage graph-based methods to efficiently and predicable exercise the scenario space to deliver high quality verification results.  It should also be noted, that an ongoing Accellera Working Group is exploring standardization of Portable Stimulus.  While Accellera working group details are not part of the session, UVM Forum attendees might consider augmenting their knowledge by visiting the Accellera Portable Stimulus group.

The fourth is Improved UVM Testbench Debug Productivity and Visibility.  For those who debug UVM on a daily basis, you might hear a common question “Are we having fun yet?” asked.  The debug of UVM can be particularly difficult.  We will have a session to show you how to navigate complex UVM environments to quickly find your way around the code – whether its your own or inherited.  You will see how SystemVerilog/UVM dynamic class activity is as easy to debug as it is with RTL signals.  Want to learn how to solve the top 10 common UVM bring-up issues with config_db, the factory, and sequence execution?  Attend and you will learn.

Novices Welcome (and will learn something too!)

While I can’t promise that if you come as a novice you will leave as an expert, you can learn about UVM in the morning as one of the sessions is a technology overview to ensure you won’t be lost when the experts speak.  If you know very little about UVM, the UVM Forum will help you.  There will be a couple presentations from UVM users.  One session is on how UVM enabled advanced storage IP silicon success (presented by Micron) and another session on UVM and emulation to ease the path to advanced verification and analysis (presented by Qualcomm).

Still want to know more before you attend?  You can also boost your UVM knowledge by attending an online UVM Basics course at Verification Academy.  Visit here to learn more about the UVM Basics course.  The Basic UVM course consists of 8 sessions with over an hour of instructional content. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The goal of the course is to raise the level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption – and makes the UVM Forum 2015 more meaningful for you.

I look forward to seeing you there.

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29 July, 2015

VA DAC2015 smlIf you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed an opportunity to get a printed copy of the DAC 2015 issue of Verification Horizons, don’t worry.  You can also download it as well.

Questa Vanguard Partners Highlighted

Eight of the eleven articles were authored or co-authored by our partners and represent a wide range of topics.  There are two articles on DO-254 (Partners: eInfochips and Verisense).  There is an article on Formal and ABV of MBIST MCPs (Parnter: FishTail Design Automation).  There is an article on how to start formal analysis “right” (Partner: OSKI).  For UVM users, reuse of MATLAB® functions and Simulink® functions is covered (Partner: Mathworks).  Continuing with another article for the UVM users, intelligent testbench automation with UVM and Questa® is explored (Partner: Codasip Ltd.).  For the Agile community, unit testing your way to a reliable testbench is explored (Partner: XtremeEDA & User company: NVIDIA).  Lastly, a noted emulation consultant (Lauro Rizzatti) shares part 2 of his three decades of emulation evolution and a customer paper (Marvell) covers techniques to accelerate RTL simulation.

VH DAC 2015 CoverAll of this is inside the 60-page mega-issue of Verification Horizons in 11 articles.  Direct links to each of the articles is shared below along with the article titles and authors.  The editor introduction by Tom Fitzpatrick gives even more detail and background on this issue.  If you don’t already have some summer or vacation reading, get your electronic copy today!

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1 July, 2015

Continuing on our journey on what is needed to get to productive verification with VIP, the first step is to make the connections between the DUT and the testbench.  This includes connecting the signals, the clock and reset and setting any parameters. This is what we covered in part 1 of the series.

Let us look at other steps need to get productive, taking PCIe VIP as an example.


Protocol Specific agents enables easy instantiation of agents in your testbench with fewer lines of configuration in the testbench. This is the customization of the generic agent. The PCIe agent will perform link training automatically, without us needing to start a sequence.


Next we move onto configuring the VIP.  Here we are able to take advantage of a configuration policy that has already been defined for the specific design IP we are using and available alongside the VIP.

It is again important for the VIP to be intuitive, and here you can see that we have used a collection of structs to define the configuration.  These are then declared as variables in a configuration class for the agent, which is used in the testbench to set the configuration.


The user code which sets the configuration for a test is then intuitive and easy to read as shown below.  In this particular example, we have set our agent to be a GEN2 root complex, connected at the serial interface and using an internally generated clock and reset.  We have disabled the build in scoreboard and coverage, but enabled transaction logging.


Once done with configuration, move on to PCIe link training and enumeration, which the VIP can take care of. As I mentioned earlier the agent will perform link training automatically, without needing to start a sequence.  The VIP also provides a sequence to complete enumeration, which will block until link training is complete.

This means that in the test, you just need to create and start this sequence, the “bring up sequence” in the code below.


Once that sequence ends, link up and enumeration are complete and you can start a user defined sequence that would typically perform reads and writes to do some application specific verification.

VIP’s include various sequence API for rapid test creation like memory, configure and I/O reads and writes, as well as various scenario and error injection sequences. Finally we are able to use the transaction layer sequences to begin some application specific verification by performing reads and writes across the bus.

Using the automation provided by the VIP it is possible to complete the entire testbench and link up process in hours rather than days, allowing users to become productive much earlier.

I would really like to hear how you use various VIPs so please comment below. In part 3 of the series, we will talk about various debug features of a VIP.

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16 May, 2015

In a recent post on John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this same topic on the verification horizon’s blog. So are VIPs becoming more and more popular? Yes!

Here are the big reasons why I believe we are seeing this trend:

  • Ease of Integration
  • Ready made Configurations and Sequences
  • Debug Capabilities

I will be digging deeper on each of these reasons and topics in a three part series on the Verification Horizons BLOG. Today, in part 1 our focus is Easy Integration or EZ VIP.

While developing VIP’s there are various trade off that one has to consider – ease of use vs amount of configuration, protocol specific vs commonality across various protocols. A couple of years ago; when I first got my hands on Mentor’s VIP, there were some features that I really liked and some that I wasn’t familiar with and some that I needed to learn. Over the last couple of years, there have been strides of improvements with ease of use (EZ-VIP) a big one in that list.

EZ-VIP’s is aimed to make it easier to:

  • Make connections between QVIP interfaces and DUT signals
  • Integrate and configure a QVIP in a UVM testbench


This makes it easier for customers to become productive in hours rather than days.

Connectivity Modules:

Earlier we gave the users the flexibility on the direction of the ports of VIP based on the use modes. The user needed to write certain glue logic apart from setting the directions of the ports.


Now we have created new connectivity modules. These connectivity modules enable easy connectivity during integration. These connectivity modules are wrapper around the VIP interface with the needed glue logic, ports having protocol standard names and with the right direction based on the mode e.g. Master, Slave, EP, RC etc. These now enables the user to quickly integrate the QVIP with the DUT.


Quick Starter Kits:

These kits are specific to PCIe and are customized pre-packaged for all major IP vendors, easy-to-use verification environments for the serial and parallel interfaces of PCIe 1.0, 2.0, 3.0, 4.0 and mPCIe, which can be used to verify PHY, Root Complex and Endpoint designs. Users also get example which could be used as reference. These have dramatically reduced bring up time for PCIe QVIP with these IPs to less than a day.

In the part 2 of this series, I will talk about QVIP Configuration and Sequences. Stay tuned and I look forward to hearing your feedback on the series of posts on VIP.

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14 January, 2015

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18.  More specifically the article states, “Who knew VIP was big and that Wally had a good piece of it?”  We knew.

We knew that ASIC and FPGA design engineers can choose to buy design IP from several alternative sources or build their own, but that does not help with the problem of verification.  We knew that you don’t really want to rely on the same source that designed your IP, to test it.  We knew that you don’t want to write and maintain bus functional models (BFMs) or more complete VIP for standard protocols.  Not that you couldn’t, but why would you if you don’t have to?

We also knew that verification teams want easy-to-use VIP that is built on a standard foundation of SystemVerilog, compliant with a protocol’s specification, and is easily configurable to your implementation.  That way it integrates into your verification environment just as easily as if you had built it yourself.

Leading design IP providers such as ARM®, PLDA, and Northwest Logic knew that Mentor Graphics’ VIP is built on standards, is protocol compliant, and is easy to use.  In fact you can read more about what Jim Wallace, systems and software group director at ARM; Stephane Hauradou, CTO of PLDA; and Brian Daellenbach, president of Northwest Logic; have to say about Mentor Graphics’ recently introduced EZ-VIP technology for PCIe 4.0 (at this website ), and why they know that their customers can rely on it as well.

Verification engineers knew, too.  You can read comments from many of them (at Cooley’s website ), about their opinions on VIP.  In addition, Mercury Systems also knew.  “Mentor Graphics PCIe VIP is fully compliant with the PCIe protocol specification and with UVM coding guidelines. We found that we could drop it into our existing environment and get it up and running very quickly”, said Nick Solimini, Consulting DV Engineer at Mercury Systems. “Mentor’s support for their VIP is excellent. All our technical questions were answered promptly so we were able to be productive throughout the project”.

So, now you know,  Mentor Graphics’ Questa VIP is built on standard SV UVM, is specification compliant, is easy to get up and running and is an integral part of many successful verification environments today.  If you’d like to learn more about Questa VIP and Mentor Graphics’ EZ-VIP technology, send me an email, and I’ll let you in on what (thanks to Cooley and our customers) is no longer the best kept secret in verification.  Who knew?

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21 April, 2011

User Adoption of OVM Featured; Views on UVM Discussed

The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set.  U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens.

Registration for the event is open and is fee-free.  U2U includes a complimentary lunch, evening reception and raffle along with the technical program.

The functional verification track opens with a presentation by Mentor’s Steve Chappell on how Mentor is “transforming verification” followed by three user presentations.  The three user presentations share a common theme that highlight how they have leveraged the Open Verification Methodology (OVM) to improve their verification productivity.  A couple presentations will also offer their views of the Accellera Universal Verification Methodology (UVM).

For users interested in the most current information on adoption and use of OVM and UVM, connecting with other users is probably the best source of unbiased information available.  Here are three presentations that can help you understand how three users get the most out OVM and UVM when coupled with Mentor technology.

User Presentations

Using OVM with Transaction and Emulation Based Simulation Acceleration
Galen Blake | Verification Lead | Altera
Using OVM (or UVM) with transaction and emulation based simulation acceleration platforms.  The OVM library is not quite as well suited to transaction and emulator based simulation acceleration.  This presentation examines the problems and approaches to address them.

Case Study “Proving OVM on a Real Design” – Testimonial by AppliedMicro
Shing Sheung Tse | Senior Verification Manager | AppliedMicro
This case study will present how APM overcame their verification challenges with Mentor’s advanced verification methodology and the decision to choose OVM.  APM will also present their view on UVM.

Verifying Bus Bridges with Questa Verification IP
Sudararajan Haran | Verification Lead | Microsemi
Microsemi moved to OVM-based verification environments and decided to use industry standard VIPs as much as possible.   This presentation will highlight Microsemi’s experiences using Mentor’s AHB and AXI VIP’s to drive the verification of our AHB_AXI and AXI_AHB bridges to a quicker completion.

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9 June, 2010

EDACafe Guest Blog DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys

The full statement can be read at EDA Cafe, click here.

The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology (OVM) can work together.  This preserves the investments made to date by users of those two methodologies.

The joint statement also says the Accellera Universal Verification Methodology (UVM) is based on OVM 2.1.1 and firmly rooted in SystemVerilog.  While we know today UVM is OVM 2.1.1 with a few small changes or additions, it is made clear that Accellera has just begun.  What happens next is the topic of the Accellera breakfast meeting.  (Have you registered yet for it?)

The joint statement asked these questions:

  • If we fast forward by a year, what would UVM base class release X look like?
  • What features should it have to solve the problems faced a year from now? 3 years from now?
  • Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs?
  • What specifically are we doing to improve our ability to find bugs in the design and then fix them?

What questions do you have?  If you want to share them here, please do.  If you cannot attend the breakfast in person, I’ll bring your questions along to ask and report back after DAC on what happened at the Accellera breakfast.

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4 May, 2010
Download OVM Configuration and Virtual Interface Extensions from

OVM_Logo Creating configurable testbench elements is critical for reuse. If you write some OVM code in one particular testbench and never intend to use it in any other testbench, then there is no need to make it configurable. As soon as you wish to take code and turn it into reusable IP which can be used in a variety of applications, not all of which are immediately known, then you need to think about how to make the code configurable. Making code configurable means that you need to think about the breadth of applications where it will be used and the degrees of freedom you want to make available to the user of this IP.

The author of any verification IP needs to think about how to make that VIP sufficiently flexible to be used in a variety of different scenarios. In order to achieve this, OVM components need to have a number of settings associated with which can be varied by the testbench integrator. These settings may include things such as error injection rates, protocol modes supported or not supported, whether an agent is active or passive, to name but a few.

Future OVM Directions

If you download the OVM Configuration and Virtual Interface Extensions, you will find information on future directions for OVM in the documentation directory.  In particular, detaching the configuration scoping mechanism from the OVM component hierarchy is an active area of investigation which might enhance the existing configuration mechanisms in important ways. This would allow one to naturally use the scoping mechanism with “behavioral VIP,” such as sequences, in addition to the current “structural scoping” mechanism that works with OVM components.

Additionally, the current configuration database is limited to storing strings, integers, and objects derived from ovm _ object. Another area of active investigation is enabling the database to store values of any type to solve the efficiency problems when storing and retrieving integral types.

It is also possible to improve and expand the existing wildcarding mechanisms to deal with the full regular expression syntax.

We invite you to join us in the this endeavor and share your thoughts here or on OVM World.  To get started, you can download the OVM Configuration and Virtual Interface extensions to learn more.

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