Posts Tagged ‘vip-tsc’

13 October, 2011

Legacy’s Luster Lost

As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.

Buy why this title?  For some, there may be no recollection of what VHS or Betamax are.  And if I were to say it is a format used to tape record video, that still might not help given DVD, MP4, etc.  If I were to even say there was once a format war over these two, one could easily shrug one’s shoulder and proclaim they both lost.  And that is true.

What do we record on today?  Precisely, the answer is neither of these for all but an obscure few.  But it was towards the end of this format war I left one area to move to another.  VHS had all but become the format of that area for video rentals, while the area I moved to was evenly split between the two formats.  I had selected Betamax.  I can go into great detail to explain the technical advantages of the format.  But those words are all lost on the market forces that ushered in VHS.  And thanks to continued innovation, these legacy formats have lost their luster.  We have all moved on.

Be Kind – Rewind

As SystemVerilog has become the dominant language standard for verification, the methodology work aggregated in Accellera’s Verification IP Technical Subcommittee (VIP-TSC) where it built the Universal Verification Methodology (UVM).  While UVM leverages SystemVerilog, the market’s move from legacy formats has left some who still use those formats to ask if the industry can be “kind, and rewind” – to still support them.

While Accellera’s UVM has been open to bring the dogma of all market participants together to create a single coherent standard, that has not met with total satisfaction of legacy users.  What now appears to be more liked by them is a wholesale translation of UVM in SystemVerilog to legacy languages.  What’s the value in that?  Does one gain greater productivity from this?

Accellera hopes to bridge this divide with a return to its first phase of verification IP interoperability work to suggest additional ways to interoperate.  For up-to-the-minute information on this, I suggest you get involved with the group.  Full information about the group is only available in the membership area – and everyone is invited to be an observing member.  But we should expect Accellera to talk about better bridges to those formats important to those sitting around the standardization table.

Fast Forward

But I still come back to the question about what’s the value in this. It is time to move forward or be stuck in the past? The format is not the value; the algorithms to do better and faster verification are.  To that end, for the users of the e language, Mentor Graphics has extended its Intelligent Testbench Automation (iTBA) technology to work in an e environment.

Many UVM (and OVM) users have found they have been able to achieve their coverage goals 10x to 100x faster than before with this innovative technology.  And it  is now readily available to the 10-15% who still use e.  For more information about leveraging iTBA, you can visit the Verification Academy where one of the new modules that was added in the iTBA section, titled Integrating iTBA into an ‘e’ Environment, is ready for viewing and explains how this is done.  [Note: Registration is required to view the module and certain restrictions apply.]  This module describes integrating Intelligent Testbench Automation into an e environment, re-using existing eVCs, and achieving functional coverage >10X faster.

While legacy language users may fret about their preferred language, the market has already spoken.  Maybe it is time to explore how advanced verification algorithms can be back ported to support legacy to ease the transition.  After all, its not the language, it’s the algorithms.  Go online and see what the advance algorithms can offer you.  Or, join us next week in San Jose, CA at the Verification Seminar.

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5 October, 2011

Is Legacy Holding You Back?

Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).

Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.

To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:

Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Cost: Free; registration restrictions apply

Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Cost: Free

Legacy set for replacement?

Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.

This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.

When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.

With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.

While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.

Why bring all this up?

We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.

In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.

In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?

I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.

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14 October, 2010

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package

UVM_Logo As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway.  While the Accellera VIP-TSC is making good progress, limited information is available to non-participants.  This limited knowledge is true for both eventual users of the standard as well as for many EDA, IP and VIP companies that don’t participate directly in the development activities but whom could benefit from planning for tool and IP interoperability.  As the standard nears completion, it is important for other EDA and IP companies to know how they might collaborate with others in support of the pending standard.

The 23rd Synopsys EDA Interoperability Forum offers EDA and IP companies and others who will integrate the use of tools and Verification IP from several vendors a first look at the new UVM 1.0 Register Package.    The Forum’s 3:15 p.m. – 4:15 p.m. session will focus on Verification and UVM Register Package interoperability.

Mark Glasser, Methodology Architect at Mentor Graphics, will share the presentation time with a couple other presenters.  His presentation is “Building Register Verification Environment in UVM.” We encourage those who can make it to the event and have the time on October 21st to attend to do so.  Mark and other experts will be able to share their UVM development experiences and offer key insight into the newer UVM 1.0 Register Package features.

The event is free of charge, but registration is required to attend this session and any others at the Forum.  Forum details are:

Date: 21 October 2010
Time: 9:30 a.m. – 4:30 p.m.
Location: Oracle Conference Center at Agnews Historic Park, Santa Clara, CA 95054 USA
Forum Website:

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23 September, 2010

UVM_Logo Mentor/Synopsys Collaboration Bears Fruit

Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC).  Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate.

As it happened, of the three major features planned for UVM 1.0, only the register package addition had multiple candidates.  For the phasing and TLM2 integration, there is only one code candidate.  There was no need to select from multiple candidates for them.

After we announced our collaboration with Synopsys, the next steps were to review the candidates via public review meetings and then hold an in-depth review at an Accellera VIP-TSC face-to-face meeting.  The multi-day face-to-face meeting concluded on September 16th and a vote to select one of the two candidate register packages opened.  That vote concluded on September 22nd with the selection of RAL, the Mentor/Synopsys collaborated candidate.

While neither candidate addressed 100% of the Accellera VIP-TSC requirements, the work now is to move in a direction where it can get closer to 100% and final approval of the UVM 1.0 standard can move this work from standards development to standards deployment.

I will update you on further UVM 1.0 developments as the code progresses to a final stage for approval.  As we near that point, we will want to have early users of UVM 1.0 test it with the Questa verification platform for completeness and readiness.

As I have done in my prior blogs, I invite those who wish to participate in this work or monitor it more closely to join the committee email reflector.  You can find official status on Accellera UVM development and how to join and monitor it at the committee website located at

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7 September, 2010


Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate

Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements.  Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently.

Further, as part of the Accellera VIP-TSC UVM development process, a request was made for companies that would have candidate solutions to hold public review meetings to share high-level information about their proposals.  There is such a review meeting for this candidate on Wednesday, 8 September 2010 at 8am PDT.

You are invited to join the presentation on WebEx and listen live on the teleconference by Mentor’s Tom Fitzpatrick and Synopsys’ Janick Bergeron as they cover the details of Synopsys RAL for UVM.  For more information on the event, visit the Main UVM Forum on by clicking here.

There are more elements to UVM 1.0 that are not part of a public review process and I invite you to visit the committee website where you can find official status on Accellera UVM development or to participate in the committee.  The committee website is located at

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28 June, 2010

Now that the Accellera VIP-TSC has released UVM-EA, effectively narrowing the choice of verification methodologies to UVM or OVM, many people are asking which way to go — OVM or UVM?  The answer depends a lot on where you are in code development and what your risk tolerance is.  The good news is that neither is a bad choice. One thing is certain: OVM is not dead yet.  It will be around for a long time.  Across the industry a lot of IP has been built and testbenches have been put into production all with OVM.  These must remain operational and supported for a similarly long time. Right now, OVM is the lowest risk choice overall.  There is tons of tool support and lots of IP available along with training and other material from a variety of vendors.  We know OVM is stable and production-worthy just by how widespread its use is.

In its current state UVM is for the more adventurous.  By and large it is OVM with the Os changed to Us.  That’s why we can say it is stable and not necessarily a bad choice.  The risk comes not from whether or not UVM itself works, but in how much support of various kinds is currently available.  Vendors are now updating their tool sets to support UVM, but that work is far from complete.  I imagine as the Accellera committee gets close to releasing UVM-1.0 we’ll see announcements from vendors around their tool support for UVM. Training, examples, and other material is under development as well and will probably be available from their respective  sources shortly after UVM-1.0 is out.

Another aspect to the risk involves 3rd party IP.  IP vendors are also working on converting their IP to be UVM compatible.  If you use 3rd party IP you will need to know when your vendor will make available the components you need converted to run under UVM. The biggest risk comes from the potential of UVM not being entirely backward compatible with OVM (factoring out the simple syntactic name changes).  The VIP-TSC has stated that backward compatibility is a goal, but not a hard requirement.  For example, the VIP-TSC is now looking deeply at phasing.  Proposals are being considered that enable phases to run in parallel and to add additional default phases.  If done properly these changes would add significant capability to UVM and be entirely backward compatible.  If not, UVM could require architectural changes in drivers and monitors to accommodate new phases.  Exactly which way this will go is not clear right now. Mentor, of course, is making a case to retain backward compatibility.

The availability of UVM-EA in advance of the standard affords a prime opportunity to kick the tires and to start some early planning.  Go ahead and download it and start evaluating it.  Try it out on small- to medium-sized pieces of code.  The UVM-EA includes a script to change the Os to Us.  It’s the same script that was used to import OVM as the seed for UVM development.  You can use UVM-EA to figure out what you need to do to convert your environment from OVM to UVM.

Eventually there will be a tipping point and UVM will become the obvious choice for a testbench methodology.  That day is still in the distance.  In the mean time OVM is around and provides all the features necessary to build sophisticated testbenches.

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17 May, 2010


The Accellera VIP-TSC makes the Early Adopter release of the Universal Verification Methodology (UVM) available.

While Accellera does not use the Latin word Omnimodus in place of the English word Universal, what Accellera does make available is for all practical intents and purposes just OVM.  In April 2010, we made available at an early version of UVM EA.  It has now been updated with Accellera’s version here.

Accellera VIP-TSC has toiled for about a year following the completion of the VIP Interoperability Recommended Practices, which allowed verification specialist to use their legacy VMM code in an OVM environment, to produce UVM 1.0 EA.  EA stands for Early Adopter to signify a release intended for wider community testing before further additions and changes are made, which will then to be followed by formal Accellera standards approval and release of the official UVM 1.0 standard.

UVM EA Content

For OVM users, UVM 1.0 EA offers no substantive technical advances from OVM.  In changing “O’s” to “U’s” and “tlm’s” to “uvm_tlm’s” it has the promise, however, of wider public EDA vendor support.  It offers no compelling reason for current OVM users to move now.  For those who wish to test their code’s readiness to adopt UVM, we have tested the EA release with the most current version of Questa.  We also maintain our commitment to offer versions of the OVM Register Package and the OVM Sequence Layering solution for those who wish to experiment with native UVM.  Stay tuned for more information on that in the future.

UVM 1.0 Standard Proposed Content

The Accellera VIP-TSC now embarks on the hard task to address development of the official UVM 1.0 standard.  At its last technical committee meeting, it began to discuss how to start the process to identify requirements for the UVM 1.0 register package.  That feature, along with others currently on the committee’s list of features include the following:

Register Memory package
Non-interpreted field macros
TLM 2.0 Support
Hierarchical phasing
Strongly-typed factory
Pre-defined run-time phases
Auto-documentation of configuration options
Virtual interface connection
Configuration randomization
Test concatenation
RTL configuration

I will share ongoing progress towards the official UVM 1.0 release as developments merit.

Getting Started with UVM EA

You can download UVM from OVM World contributions area where other OVM contributions are being readied for UVM.  Your feedback is always welcome.

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3 February, 2010

Accellera-VIP-Interop-Code-Download3 – 2 – 1 – DOWNLOAD!

As I mentioned in a previous blog, the Accellera OVM/VMM Interoperability kit code that is a companion to the Verification Intellectual Property Recommended Practices (1MB PDF) was nearing readiness.  As of today, it is now ready for download and use.  With qualification tests run on verification platforms from the Big-3 EDA companies, no objection was voiced at a recent Accellera VIP-TSC meeting against it being released for general industry use and adoption.

Congratulations to the Accellera VIP-TSC for hitting this huge milestone!

This kit contains an OVM/VMM interoperability library that meets and exceeds the requirements recently approved by the Accellera VIP-TSC.  It includes a growing collection of adapters and utilities that enable easy and flexible reuse of existing IP in both OVM and VMM environments. Both library’s use-models are fully preserved, and no modifications to existing IP are needed.

Team OVM has created a version of the VMM 1.1b kit that needs to be downloaded from OVM World to work with the Accellera interoperability kit.  In addition to modifications needed to get VMM 1.1 in compliance with standard SystemVerilog and to workaround differences in simulator implementations, the VMM 1.1b kit also incorporates changes to enable interoperability with OVM.

To setup your environment requires making sure you have installed and are pointing to qualified versions of simulators, libraries, and utilities.  The release notes and overview documentation contained in the kit offer full details on how to use the kit.  Basic information is shown below.

VIP-TSC Interoperability Release Notes

The Accellera VIP-TSC welcomes suggestions for improvements to the Verification Intellectual Property Recommended Practices and Interoperability Kit.  They should be sent to the VIP email reflector:

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