Posts Tagged ‘TLM’

25 July, 2016

As I mentioned in my last UVM post, UVM allows engineers to create modular, reusable, randomized self-checking testbenches. In that post, we covered the “modularity” aspect of UVM by discussing TLM interfaces, and their value in isolating a component from others connected to it. This modularity allows a sequence to be connected to any compatible driver as long as they both are communicating via the same transaction type, or allows multiple coverage collectors to be connected to a monitor via the analysis port. This is incredibly useful in creating an environment in that it gives the environment writer the ability to mix and match components from a library into a configuration that will verify the desired DUT.

Of course, it is often the case that you may want to have multiple environments that are very similar, but may only differ in small ways from each other. Every environment has a specific purpose, and also shares most of its infrastructure with the others. How can we share the common parts and only customize the unique portions? This is, of course, one of the principles of object-oriented programming (OOP), but UVM actually takes it a step further.

A naïve OOP coder might be tempted to instantiate components in an environment directly, such as:
class my_env extends uvm_env;
  function void build_phase(…);
    my_driver drv = new("drv", this); //extended from uvm_driver
    …
  endfunction
  …
endclass

The environment would be similarly instantiated in a test:
class my_test extends uvm_test;
  function void build_phase(…);
    my_env env = new("env", this); //extended from uvm_env
  endfunction
  …
endclass

Once you get your environment running with good transactions, it’s often useful to modify things to find out what happens when you inject errors into the transaction stream. To do this, we’ll create a new driver, called my_err_driver (extended from my_driver) and instantiate it in an environment. OOP would let us do this by extending the my_env class and overloading the build_phase() method like this:
class my_env2 extends my_env;
  function void build_phase(…);
    my_err_driver drv = new(“drv”, this);
    …
  endfunction
  …
endclass

Thus, the only thing different is the type of the driver. Because my_err_driver is extended from my_driver, it would have the same interfaces and all the connections between the driver and the sequencer would be the same, so we don’t have to duplicate that other code. Similarly, we could extend my_test to use the new environment:
class my_test2 extends my_test;
  function void build_phase(…);
    my_env2 env = new(“env”, this); //extended from my_env
    …
  endfunction
  …
endclass

So, we’ve gone from one test, one env and one driver, to two tests, two envs and two drivers (and a whole slew of new build_phase() methods), when all we really needed was the extra driver. Wouldn’t it be nice if there were a way that we could tell the environment to instantiate the my_err_driver without having to create a new extension to the environment? We use something called the factory pattern to do this in UVM.

The factory is a special class in UVM that creates an instance for you of whatever uvm_object or uvm_component type you specify. There are two important parts to using the factory. The first is registering a component with the factory, so the factory knows how to create an instance of it. This is done using the appropriate utils macro (which is just about the only macro I like using in UVM):
class my_driver extends uvm_driver;
  `uvm_component_utils(my_driver) // notice no ‘;’
  …
endclass

The uvm_component_utils macro sets up the factory so that it can create an instance of the type specified in its argument. It is critical that you include this macro in all UVM classes you create that are extended (even indirectly) from the uvm_component base class. Similarly, you should use the uvm_object_utils macro to register all uvm_object extensions (such as uvm_sequence, uvm_sequence_item, etc.).

Now, instead of instantiating the my_driver directly, we instead use the factory’s create() method to create the instance:
class my_env extends uvm_env;
  `uvm_component_utils(my_env)
  function void build_phase(uvm_phase phase);
    drv = my_driver::type_id::create(“drv”, this);
    …
  endfunction
  …
endclass

The “::type_id::create()” incantation is the standard UVM idiom for invoking the factory’s static create() method. You don’t really need to know what it does, only that it returns an instance of the my_driver type, which is then assigned to the drv handle in the environment. Given this flexibility, we can now use the test to tell the environment which driver to use without having to modify the my_env code.

Instead of extending my_test to instantiate a different environment, we can instead use an extension of my_test to tell the factory to override the type of object that gets instantiated for my_driver in the environment:
class my_factory_test extends uvm_test;
  `uvm_component_utils(my_factory_test);
  function void build_phase(…);
my_driver::type_id::set_type_override(my_err_driver::get_type());
    super.build_phase(…);
  endfunction
endclass

This paradigm allows us to set up a base test that instantiates the basic environment with default components, and then extend the base test to create a new test that simply consists of factory overrides and perhaps a few other things (for future blog posts) to make interesting things happen. For example, in addition to overriding the driver type, the test may also choose a new stimulus sequence to execute, or swap in a new coverage collector. The point is that the factory gives us the hook to make these changes without changing the env code because the connections between components remain the same due to the use of the TLM interfaces. You get to add new behavior to an existing testbench without changing code that works just fine. It all fits together…

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25 April, 2016

Having been deeply involved with Universal Verification Methodology (UVM) from its inception, and before that, with OVM from its secret-meetings-in-a-hidden-hotel-room beginnings, I must admit that sometimes I forget some of the truly innovative and valuable aspects of what has become the leading verification methodology for both ASIC (see here) and FPGA (see here) verification teams. So I thought it might be helpful to all of us if I took a moment to review some of the key concepts in UVM. Perhaps it will help even those of us who may have become a bit jaded over the years just how cool UVM really is.

I have long preached that UVM allows engineers to create modular, reusable, randomized self-checking testbenches. Of course, these qualities are all inter-related. For example, modularity is the key to reuse. UVM promotes this through the use of transation-level modeling (TLM) interfaces. By abstracting the connections using ports on the “calling” side and exports on the “implementation” side, every component in a UVM testbench is blissfully unaware of the internal details of the component(s) to which it is connected. One of the most important places where this abstraction comes in handy is between sequences and drivers.

seq2driverconnection Figure 1: Sequence-to-Driver Connection(s)

Much of the “mechanical” details are, of course, hidden by the implementation of the sequencer, and the user view of the interaction is therefore rather straightforward:

seqdriverapi Figure 2: The Sequence-Driver API

Here’s the key: That “drive_item2bus(req)” call inside the driver can be anything. In many cases, it will be a task call inside the driver that manipulates signals inside the virtual interface, or the calls could be inline:

task run_phase(uvm_phase phase);
  forever begin
    my_transaction tx;
    @(posedge dut_vi.clock);
    seq_item_port.get_next_item(tx);
    dut_vi.cmd  = tx.cmd;
    dut_vi.addr = tx.addr;
    dut_vi.data = tx.data;
    @(posedge dut_vi.clock)
      seq_item_port.item_done();
  end
endtask: run_phase

As long as the get_next_item() and item_done() calls are present in the driver, everything else is hidden from the rest of the environment, including the sequence. This opens up a world of possibilities.

One example of the value of this setup is when emulation is a consideration. In this case, the task can exist inside the interface, which can itself exist anywhere. For emulation, the interface often will be instantiated inside a protocol module, which includes other protocol-specific information:

dualtop Figure 3: Dual Top Architecture

You can find out more about how to set up your environment like this in the UVM Cookbook. And if you’re interested in learning more about setting up your testbench to facilitate emulation, you can download a very interesting paper here.

The flexibility of the TLM interface between the sequence and the driver gives UVM users the flexibility to reuse the same tests and sequences as the project progresses from block-level simulation through emulation. All that’s needed is a mechanism to allow a single environment to instantiate different components with the same interfaces without having to change the code. That’s what the factory is for, and we’ll cover that in our next session.

I’m looking forward to hearing from the new and advanced UVM users out there!

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30 May, 2012

Where might our paths cross?

It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC).  If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.

Saturday and Sunday are busy with an Accellera Systems Initiative board meeting.  Split across two days, Accellera board members will meet to conduct traditional business and  do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year.  Intel has graciously granted space in their San Francisco offices, so I won’t be around the Moscone Center during the pre-conference setup phase.  (By the way, Thank you Intel!)
After we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception (registration required) at 6:00pm  (San Francisco Marriott, Salon 7) and Gary Smith’s “Sunday Night at DAC” at 7:00pm (San Francisco Marriott, Salon 6).

During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth  #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings.  And just in case you may note that most of my evenings are not scheduled, they are with customer activities.

MentorGraphics-LogoWhen the show floor is open, you will find me most of the time at the Verification Academy Booth #1514.  I will join Mentor’s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry’s research results, updates on important verification standards from Mentor’s perspective and more.  You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth.  (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)

Verification Academy DAC Schedule

Monday, June 4th Tuesday, June 5th Wednesday, June 6th
10:00 – Simulation and Formal Assertion-Based Verification
Harry Foster, Mentor Graphics
9:30 – Using the UVM Register Layer
John Aynsley, Doulos
10:00 – Bringing UVM to Life
Ellie Burns, Mentor Graphics
11:00 – Bringing UVM to Life
Ellie Burns, Mentor Graphics
10:00 – Generating Coverage Models and Achieving Coverage Closure
Mark Olen, Mentor Graphics
11:00 – Resistance is Futile: Learning to love UVM!
Mike Bartley, Test & Verification Solutions
2:00 – Verification of Low Power SoCs with IEEE UPF
Stephen Bailey, Mentor Graphics
2:00 – Bringing UVM to Life
Ellie Burns, Mentor Graphics
2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics
Yunshan Zhu, NextOp
3:00 – Evolving Trends in Functional Verification
Harry Foster, Mentor Graphics
3:00 – Evolving Trends in Functional Verification
Harry Foster, Mentor Graphics
3:00 – UVM Express
Mike Baird, Willamette HDL, Inc.
4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
Paul Martin, ARM
4:00 – Evolving Trends in Functional Verification
Harry Foster, Mentor Graphics
5:00 – Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
David Murray, Duolog
5:00 – Meet the Verification Experts Cocktail Reception

Accellera logo_color_200x111 - CopyAccellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS).  The lunch is free and seating is limited and registration is required.

Hosted Luncheon and Technical Presentation

Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard


Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee

Wednesday, June 6, 12:00-1:30pm
Moscone Center, Room 250
Register Now >
This luncheon is open to all DAC attendees. Seating is limited! You must pre-register for this event.

Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.

This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.

SystemC User Group Meeting

NASCUG XVIII

North American SystemC User’s Group Meeting
Wednesday, June 6, 2:00-6:00pm
Moscone Center, Room 262
Register Now >
This event is open to all DAC attendees. Seating is limited!

The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agendafor the event has a lot offer user group attendees.

Mentor’s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog.  Adam’s presentation is scheduled to start at 3:00pm.

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16 January, 2012

IEEE Std. 1666™-2011 Available as Free Download

In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011.  One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM).  I pointed to several online resources to learn more about the revised SystemC standard in that blog.  But missing from the list of resources was information on how to get the revised standard from the IEEE.  As I concluded my blog, I indicated that the final editorial review and formatting for publication was underway and that I would report back when this work was completed.

IEEE Std 1666-2011I can report that the IEEE SA concluded their editing of the specification and it is now ready for download.  Many of you know the prior version of the SystemC standard was available for free download and have wondered if this would be the same for this revision update.  The good news is the revision update is available as a free download as well.  If you wish to have a printed and bound copy, that too is available, but that will have to be purchased.

IEEE Std. 1666-2011 is part of the “IEEE Get Program” that offers individuals the ability to retrieve, download and print one copy of the standard for free.  Click on the link above to get your personal copy of the standard.  You will need to share some basic information with the IEEE on your user type (Academic, System/Semiconductor Company,  EDA Company, IP Company or Other).  This is certainly worth if for a free copy.

The original standard, IEEE Std. 1666™-2005, had more than 50,000 free downloads since it was made available and I expect this version to do even better.  With the addition of TLM to the standard and the move up in abstraction to handle system design requirements, the need for this standard is even more pressing today.

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10 November, 2011

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support

A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.

For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI).  OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard.  TLM is important to SystemC, but it has also been leveraged outside of it.

We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog.  This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).

If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity.  The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first.  This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.

As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together.  And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together.  I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.

For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting.  I will share with you when it is ready to use as well as how to get it and where to find it.

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21 June, 2011

System Standards Worlds Initiate Unification

accellera SystemC Logo

Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here.

While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs.  At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit?  Where are they going?,” technical members of the two communities gathered to ponder answers to those questions.  At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.

DAC Slide 5

Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community.  A lot has transpired since then.  Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively.  And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.

In this evolution, it became clear to me that each organization was “completing” the other.  OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™).  As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.

In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.

What do you think about the unification?

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22 February, 2011

systemcday2011curveOpen SystemC Initiative Tackles the Future

If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM).  And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days.  But you may also want to bring a colleague to attend the SystemC Day activities.

For SystemC Day at DVCon, the morning session is the North American SystemC Users Group (NASCUG) meeting that features a Keynote presentation by industry luminary Jim Hogan.

Jim HoganJim’s keynote will be on “Navigating the SoC Era.”  NASCUG attendance is free, but you need to register to attend.

Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.

After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.

In the afternoon, a tutorial on software-driven verification titled Software-Driven Verification Using TLM-2.0 Virtual Platforms will be presented by experts from the OSCI, Accellera and the user community that are using standards-based methodologies in production today.  The afternoon tutorial requires registration at the DVCon website.  The tutorial is free for conference attendees.  A small fee is charged for those who wish to attend this tutorial only.  Is software-driven verification in your future?  Chances are highly likely it is and I suggest you look at attending this event.

I’ll see you there!

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24 May, 2010

You Are Invited – Register Now!

(seating is limited)

Sunday, June 13
2:30pm – 6:00pm
Anaheim Hilton, California Ballroom A
Anaheim, California
www.nascug.org

On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.

As a global sponsor of OSCI events, Mentor encourages the SystemC community to meet at this event to learn more about SystemC advances and applications.

Technical presentations on architectural modeling, transaction-level modeling and analog/mixed-signal design using SystemC™ will be featured. You will be able to interact with colleagues and industry experts, and find out first-hand how system-level design with SystemC has become a nuts-and-bolts part of the designer’s toolbox.

AGENDA

2:30pm – 3:00pm Registration
3:00pm – 3:10pm Welcome & Agenda
3:10pm – 3:30pm OSCI and Technical Working Group Update
Eric Lish, OSCI Chairman
3:30pm – 5:50pm Technical Presentations:
  • How to Create Adaptors Between Modeling Abstraction Levels
    Ashwani Singh, CircuitSutra Technologies Pvt Ltd
  • Virtual Development Platforms — What and How Much to Model?
    Bill Bunton, LSI Networking Components Division
  • Modeling Communication Systems Using the SystemC AMS    Building Block Library
    Jiong Ou, Institute of Computer Technology, Vienna University of Technology
  • New Features for Process Control in SystemC
    John Ansley, Doulos Ltd.
  • Generating Workload Models from TLM-2.0-Based Virtual Platforms for Efficient Architecture Performance Analysis
    Tim Kogel, Synopsys, Inc.
5:50pm – 6:00pm Meeting Close and Prize Drawing

Design Automation Conference

EDA ConsortiumSpecial Invitation to DAC 47 Kick-Off Reception

6:00pm – 7:30pm
Anaheim Hilton, Pacific Ballroom

The DAC Executive Committee and the EDA Consortium invite the NASCUG XIII participants to attend their annual DAC Kick-Off Reception at this year’s conference in Anaheim, California. The reception begins just as the user group meeting concludes.  Both events are in the Anaheim Hilton and located close to each other.  Register Now to attend the Sunday reception.

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22 April, 2010

Noted EDA analyst and guru Gary Smith delivered keynote address: “ESL: Where We Are and Where We’re Going”

OSCI sponsored the first annual SystemC Day at DVCon 2010.  The presentations were video recorded and are available for free for those who missed DVCon or who may wish to see them again.  Gary Smith’s presentation (registration required) and OSCI chair, Eric Lish’s OSCI Update lead the video set from SystemC Day.

The 12th North American SystemC Users Group (NASCUG) meeting was part of SystemC Day at DVCon and featured technical presentations on architectural modeling, verification, and analog/mixed-signal design using SystemC.

OSCI ON YOUTUBE: More videos of users and their perspectives on SystemC events and activities can be found via the OSCI channel on YouTube: http://www.youtube.com/officialsystemc

Click here for completing listing of the following technical presentations.

The Metaport: A Technique for Managing Code Complexity
Jack Donovan, HighIP Design, Texas, USA

The metaport is a coding style that can effectively manage code complexity for complex ESL models, especially models that are intended for high-level synthesis. This presentation will give an overview of the metaport concept and dive into the details of a possible implementation.

OCP Socket Modeling with TLM-2.0
Hervé Alexanian, Sonics Inc., California, USA

This presentation discusses work performed by the OCP-IP Committee, specifically modeling that OCP built upon the TLM-2.0 standard.

ADL Synthesis using ArchC
Samuel Goto, Master student at UNICAMP

The design and implementation of processors is a complex task. Architecture Description Languages (ADLs) were created to extend existing HDLs, to ease the process of developing and prototyping an architecture by providing a set of tools and algorithms to optimize and automate some of the tedious parts. While much has been done on the specification and business levels of ADLs, there is a huge gap between ADL specifications/simulators and real life processors written in RTL. This project addresses the issues of bringing an ADL description to the RTL level, and reports the development of an extension of ArchC to support this level.

Look Ma, No Clocks! Improving Model Performance
David Black, XtremeEDA, Texas, USA

This tutorial-style presentation illustrates some techniques to avoid the inclusion of clocks in SystemC simulations and provide results of simple experiments showing the simulation performance benefits. Concepts discussed include synchronization, clock-free timers, and the effects of clocks on performance. A proposal is made for a simple SystemC class that can simplify coding when clocks are thought to be needed.

TLM-driven Design and Verification Methodology
Brian Bailey, independent consultant

SystemC is well on the road to adoption in a number of areas within the Electronic System Level (ESL) space, but many of those are separated islands today. Virtual Prototyping has seen a huge leap forward with the standardization of TLM 2.0. SystemC is also being used successfully for high-level synthesis at the module level, but to make SystemC pervasive, there must be a link between the applications. In addition, to reap the maximum productivity gains from a migration to a higher-level of abstraction, the verification methodology must also change in significant ways. In this presentation we will explore a new TLM-driven design and verification methodology that is being developed within Cadence, critiqued by their customers and documented in a book, which will be released over a number of months as pieces of it mature.

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