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Posts Tagged ‘systemc’

15 December, 2016

Technical Program is Live

For the past several months, the DVCon U.S. Steering Committee has been meeting to craft a compelling event of technical papers, panels, keynotes, poster sessions and more for you.  With the hard work of authors who supply this content and the Technical Program Committee that reviews and selects from this content, a 4-day event schedule is now published.  You can find the event schedule here.

I am pleased to chair DVCon U.S. 2017 and work with such an august body of people – from the electronic design automation industry, design and verification practitioners and professionals from large systems houses to small consultancies – all who work hard for you to make this happen.  As has been the tradition of DVCon U.S. the past several years, the event starts with Accellera Day on Monday (Feb 27th) followed by two days of paper presentations, keynotes, panels and an exhibition.  The exhibition starts Monday, Accellera Day.  The last day of DVCon U.S. features a full day of tutorials split in to half-day parts.

Accellera Day

DVCon U.S. will feature something for advanced users and those who may be more novice.  The conference will showcase emerging standards and updates to those standards well used.  On Monday, Accellera Day, DVCon U.S. begins with a tutorial devoted to work underway within Accellera on a new standard, “Portable Stimulus,” that is set to give design and verification engineers a boost in overall design and verification productivity.  Given the work by the Accellera Portable Stimulus Working Group to put as much of the standard in place that it can, this tutorial, Creating Portable Stimulus Models with the Upcoming Accellera Standard, is sure to be an important educational opportunity.  If you are a user of UVM (Universal Verification Methodology) you will find the Portable Stimulus standard is set to remove many of the limitations of reuse at the subsystem and full-chip level and address the lack of portability across execution platforms.  Are you ready for Portable Stimulus?  You will be ready after attending this tutorial.

As the Monday luncheon evolves, I anticipate a moderated panel discussion hosted by Accellera on the emerging Portable Stimulus standard based on what you learned in the morning session.  As lunch ends, two parallel tutorials will start, one on IEEE P1800.2™ (aka UVM) and the other on System C design and verification advances.  Accellera Day is a great event to learn about the latest in the evolution of standards coming from Accellera and the IEEE.

Special Session

DVCon U.S. will make one departure from prior years’ programs and offer a special session on Tuesday on Trends in Functional Verification: A 2016 Industry Study presented by Harry Foster.  Harry has been reporting on the 2016 Wilson Research Group Study here at the Verification Horizon’s BLOG, and he has shared regional information at DVCon Europe and DVCon India on adoption and use of design and verification tools, technology and standards.  At DVCon U.S. he will pull all this together to show trends and offer predictions for the future.

There is much more to DVCon U.S. 2017 that I think you will find useful.  I leave it to you to explore the program more to discover this for yourself.  And if you can make it to DVCon U.S., registration is also open with advanced rates available until January 26th.  I hope to see you there!

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21 September, 2016

FPGA Language and Library Trends

This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I focused on FPGA verification techniques and technologies adoption trends, as identified by the 2016 Wilson Research Group study. In this blog, I’ll present FPGA design and verification language trends.

You might note that the percentage for some of the language that I present sums to more than one hundred percent. The reason for this is that many FPGA projects today use multiple languages.

FPGA RTL Design Language Adoption Trends

Let’s begin by examining the languages used for FPGA RTL design. Figure 1 shows the trends in terms of languages used for design, by comparing the 2012, 2014, and 2016 Wilson Research Group study, as well as the projected design language adoption trends within the next twelve months. Note that the language adoption is declining for most of the languages used for FPGA design with the exception of Verilog and SystemVerilog.

Also, it’s important to note that this study focused on languages used for RTL design. We have conducted a few informal studies related to languages used for architectural modeling—and it’s not too big of a surprise that we see increased adoption of C/C++ and SystemC in that space. However, since those studies have (thus far) been informal and not as rigorously executed as the Wilson Research Group study, I have decided to withhold that data until a more formal study can be executed related to architectural modeling and virtual prototyping.


Figure 1. Trends in languages used for FPGA design

It’s not too big of a surprise that VHDL is the predominant language used for FPGA RTL design, although it is slowly declining when viewed as a worldwide trend. An important note here is that if you were to filter the results down by a particular market segment or region of the world, you would find different results. For example, if you only look at Europe, you would find that VHDL adoption as an FPGA design language is about 79 percent, while the world average is 62 percent. However, I believe that it is important to examine worldwide trends to get a sense of where the industry is moving in the future.

FPGA Verification Language Adoption Trends

Next, let’s look at the languages used to verify FPGA designs (that is, languages used to create simulation testbenches). Figure 2 shows the trends in terms of languages used to create simulation testbenches by comparing the 2012, 2014, and 2016 Wilson Research Group study, as well as the projected verification language adoption trends within the next twelve months.


Figure 2. Trends in languages used in verification to create FPGA simulation testbenches

What is interesting in 2016 is that SystemVerilog overtook VHDL as the language of choice for building FPGA testbenches. But please note that the same comment related to design language adoption applies to verification language adoption. That is, if you were to filter the results down by a particular market segment or region of the world, you would find different results. For example, if you only look at Europe, you would find that VHDL adoption as an FPGA verification language is about 66 percent (greater than the worldwide average), while SystemVerilog adoption is 41 percent (less than the worldwide average).

FPGA Testbench Methodology Class Library Adoption Trends

Now let’s look at testbench methodology and class library adoption for FPGA designs. Figure 3 shows the trends in terms of methodology and class library adoption by comparing the 2012, 2014, and 2016 Wilson Research Group study, as well as the projected verification language adoption trends within the next twelve months.


Figure 3. FPGA methodology and class library adoption trends

Today, we see a basically a flat or downward trend in terms of adoption of all testbench methodologies and class libraries with the exception of UVM, which has been growing at a healthy 10.7 percent compounded annual growth rate. The study participants were also asked what they plan to use within the next 12 months, and based on the responses, UVM is projected to increase an additional 12.5 percent.

By the way, to be fair, we did get a few write-in methodologies, such as OSVVM and UVVM that are based on VHDL. I did not list them in the previous figure since it would be difficult to predict an accurate adoption percentage. The reason for this is that they were not listed as a selection option on the original question, which resulted in a few write-in answers. Nonetheless, the data suggest that the industry momentum and focused has moved to SystemVerilog and UVM.

FPGA Assertion Language and Library Adoption Trends

Finally, let’s examine assertion language and library adoption for FPGA designs. The 2016 Wilson Research Group study found that 47 percent of all the FPGA projects have adopted assertion-based verification (ABV) as part of their verification strategy. The data presented in this section shows the assertion language and library adoption trends related to those participants who have adopted ABV.

Figure 4 shows the trends in terms of assertion language and library adoption by comparing the 2012, 2014, and 2016 Wilson Research Group study, and the projected adoption trends within the next 12 months. The adoption of SVA continues to increase, while other assertion languages and libraries are not trending at significant changes.


Figure 4. Trends in assertion language and library adoption for FPGA designs

In my next blog (click here), I will shift the focus of this series of blogs and start to present the ASIC/IC findings from the 2016 Wilson Research Group Functional Verification Study.

Quick links to the 2016 Wilson Research Group Study results

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18 August, 2016

A great technical program awaits you for DVCon India 2016!  The DVCon India Steering Committee and Technical Program Committee have put together another outstanding program.  The two-day event splits itself into two main technical tracks: one for the Design Verification professional [DV Track] and the other from the Electronic System Design professional [ESL Track].  The conference will be held on Thursday & Friday, 15-16 September 2016 at the Leela Palace in Bangalore.  The conference opens with industry keynotes and a round of technical tutorials the first day.  Wally Rhines, Mentor Graphics CEO, will be the first keynote of the morning on “Design Verification – Challenging Yesterday, Today and Tomorrow.”

Mentor Graphics at DVCon India

In addition to Wally’s keynote, Mentor Graphics has sponsored several tutorials which when combined with other conference tutorials shares information, techniques and tips-and-tricks that can be applied to your current design and verification challenges.

The conference’s other technical elements (Posters, Panels & Papers) will likewise feature Mentor Graphics participants.  You should visit the DVCon India website for the full details on the comprehensive and deep program that has been put together.  The breadth of topics makes it an outstanding program.

Accellera Portable Stimulus Standard (PSS)

The hit of the first DVCon India was the early discussion about the emerging standardization activity in Accellera on “Portable Stimulus.”  In fact, at the second DVCon India a follow-up presentation on PSS standardization was requested and given as well (Leveraging Portable Stimulus Across Domains and Disciplines).  This year will be no exception to cover the PSS topic.

The Accellera Tutorial for DVCon India 2016 is on the emerging Portable Stimulus Standard.  The last thing any design and verification team wants to do is to rewrite a test as a design progresses along a path from concept to silicon.  The Accellera PSS tutorial will share with you concepts being ratified in the standard to bring the next generation of verification productivity and efficiency to you to avoid this.  Don’t be surprised if the PSS tutorial is standing room only.  I suggest if you want a seat, you come early to the room.


To attend DVCon India, you must register.  A discounted registration rates available through 30 August 2016.  Click here to register!  I look forward to see you at DVCon India 2016! If you can’t join us in person, track the Mentor team on social media or on Twitter with hashtag #DVCon.

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8 August, 2016

This is the first in a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group functional verification study blogs, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons:

  1. Some of the more interesting trends in our 2016 study are related to FPGA designs. The 2016 ASIC/IC functional verification trends are overall fairly flat, which is another indication of a mature market.
  2. Unlike the traditional ASIC/IC market, there has historically been very few studies published on FPGA functional verification trends. We started studying the FPGA market segment back in the 2010 study, and we now have collected sufficient data to confidently present industry trends related to this market segment.
  3. Today’s FPGA designs have grown in complexity—and many now resemble complete systems. The task of verifying SoC-class designs is daunting, which has forced many FPGA projects to mature their verification process due to rising complexity. The FPGA-focused data I present in this set of blogs will support this claim.

My plan is to release the ASIC/IC functional verification trends through a set of blogs after I finish presenting the FPGA trends.


In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification at that point in time. However, after the 2004 study, no additional Collett studies were conducted, which left a void in identifying industry trends. To address this dearth of knowledge, five functional verification focused studies were commissioned by Mentor Graphics in 2007, 2010, 2012, 2014, and 2016. These were world-wide, double-blind, functional verification studies, covering all electronic industry market segments. To our knowledge, the 2014 and 2016 studies are two of the largest functional verification study ever conducted. This set of blogs presents the findings from our 2016 study and provides invaluable insight into the state of the electronic industry today in terms of both design and verification trends.

Study Background

Our study was modeled after the original 2002 and 2004 Collett International Research, Inc. studies. In other words, we endeavored to preserve the original wording of the Collett questions whenever possible to facilitate trend analysis. To ensure anonymity, we commissioned Wilson Research Group to execute our study. The purpose of preserving anonymity was to prevent biasing the participants’ responses. Furthermore, to ensure that our study would be executed as a double-blind study, the compilation and analysis of the results did not take into account the identity of the participants.

For the purpose of our study we used a multiple sampling frame approach that was constructed from eight independent lists that we acquired. This enabled us to cover all regions of the world—as well as cover all relevant electronic industry market segments. It is important to note that we decided not to include our own account team’s customer list in the sampling frame. This was done in a deliberate attempt to prevent biasing the final results. My next blog in this series will discuss other potential bias concerns when conducting a large industry study and describe what we did to address these concerns.

After data cleaning the results to remove inconsistent or random responses (e.g., someone who only answered “a” on all questions), the final sample size consisted of 1703 eligible participants (i.e., n=1703). This was approximately 90% this size of our 2014 study (i.e., 2014 n=1886). However, to put this figure in perspective, the famous 2004 Ron Collett International study sample size consisted of 201 eligible participants.

Unlike the 2002 and 2004 Collett IC/ASIC functional verification studies, which focused only on the ASIC/IC market segment, our studies were expanded in 2010 to include the FPGA market segment. We have partitioned the analysis of these two different market segments separately, to provide a clear focus on each. One other difference between our studies and the Collett studies is that our study covered all regions of the world, while the original Collett studies were conducted only in North America (US and Canada). We have the ability to compile the results both globally and regionally, but for the purpose of this set of blogs I am presenting only the globally compiled results.

Confidence Interval

All surveys are subject to sampling errors. To quantify this error in probabilistic terms, we calculate a confidence interval. For example, we determined the “overall” margin of error for our study to be ±2.36% at a 95% confidence interval. In other words, this confidence interval tells us that if we were to take repeated samples of size n=1703 from a population, 95% of the samples would fall inside our margin of error ±2.36%, and only 5% of the samples would fall outside. Obviously, response rate per individual question will impact the margin of error. However, all data presented in this blog has a margin of error of less than ±5%, unless otherwise noted.

Study Participants

This section provides background on the makeup of the study.

Figure 1 shows the percentage of overall study FPGA and ASIC/IC participants by market segment. It is important to note that this figures does not represent silicon volume by market segment.


Figure 1: FPGA and ASIC/IC study participants by market segment

Figure 2 shows the percentage of overall study eligible FPGA and ASIC/IC participants by their job description. An example of eligible participant would be a self-identified design or verification engineer, or engineering manager, who is actively working within the electronics industry. Overall, design and verification engineers accounted for 60 percent of the study participants.


Figure 2: FPGA and ASIC/IC study participants job title description

Before I start presenting the findings from our 2016 functional verification study, I plan to discuss in my next blog (click here) general bias concerns associated with all survey-based studies—and what we did to minimize these concerns.

Quick links to the 2016 Wilson Research Group Study results

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30 July, 2015

Accellera Handoffs UVM to IEEE

It has been a long path from Mentor’s AVM to IEEE P1800.2.  But the moment has arrived: Accellera has formally announced UVM 1.2 will be submitted as a contribution to the IEEE P1800.2™ working group.

Verification Methodology Beginnings

As the IEEE finalized approval of the initial release of SystemVerilog (IEEE Std. 1800™) in 2005, I floated the idea of the need for a methodology that would be a companion to it.  At the time there was little to no industry desire to explore this opportunity in earnest – apart from interest by Mentor Graphics – so we launched our Advanced Verification Methodology (AVM) and set a new direction for an open functional verification methodology.  We built implementations of AVM based on SystemVerilog and SystemC (IEEE Std. 1666™).  We also pioneered an open-source mechanism based on the Apache 2.0 license which is now the accepted license to foster global and rapid open-source adoption in the EDA industry.  And as others joined with us in this journey, AVM grew to become OVM, then UVM.  Now UVM is set to become an IEEE standard.  The IEEE has assigned it project number 1800.2.

imagePath to IEEE

To say we are pleased to see UVM move to the IEEE is an understatement.  We congratulate the Accellera UVM team on its accomplishment and look forward to participate in this phase of UVM’s standardization. Since our first public announcement on May 8, 2006 when we introduced the world to AVM and announced support for it from 19 of our Questa Vanguard Partners, to our announced collaboration with Cadence Design Systems on the development of the Open Verification Methodology (OVM) on August 16, 2007 and the eventual announcement January 8, 2010 that Accellera adopts OVM as the basis of its Universal Verification Methodology, we have guided its development and supported a path for the Big-3 EDA to voice positive public support.  We are thrilled Accellera has announced its delivery of UVM to the IEEE for ongoing standardization and maintenance.

IEEE Standardization

What comes next?  The IEEE P1800.2 (UVM) project has announced a Call for Participation and kickoff meeting to be held August 6, 2015 from 9am – 11am PDT.  The first meeting will be held via teleconference.  In order to attend, you will need to register for the meeting.  Membership in the IEEE project will be “entity-based” with one company, one vote.  The call for participation has details on membership requirements in order to observe or actively participate.  The 1800.2 project will only focus on the written specification and not the open-source base class library (BCL).  The Accellera UVM TSC will continue to update the BCL.  Accellera has committed to keep the BCL implementation current with changes proposed and approved by the IEEE 1800.2 working group.  This is just like the arrangement Accellera has with the IEEE for SystemC.

Join us at the upcoming meeting and remember to register in order to attend!


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27 July, 2015

ASIC/IC Language and Library Adoption Trends

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I presented our study findings on various verification technology adoption trends. In this blog, I focus on language and library adoption trends.

As previously noted, the reason some of the results sum to more than 100 percent is that some projects are using multiple languages; thus, individual projects can have multiple answers.

Figure 1 shows the adoption trends for languages used to create RTL designs. Essentially, the adoption rates for all languages used to create RTL designs is projected to be either declining or flat over the next year, with the exception of SystemVerilog.


Figure 1. ASIC/IC Languages Used for RTL Design

Figure 2 shows the adoption trends for languages used to create ASIC/IC testbenches. Essentially, the adoption rates for all languages used to create testbenches are either declining or flat, with the exception of SystemVerilog. Nonetheless, the data suggest that SystemVerilog adoption is starting to saturate or level off at about 75 percent.


Figure 2. ASIC/IC Languages Used for  Verification (Testbenches)

Figure 3 shows the adoption trends for various ASIC/IC testbench methodologies built using class libraries.


Figure 3. ASIC/IC Methodologies and Testbench Base-Class Libraries

Here we see a decline in adoption of all methodologies and class libraries with the exception of Accellera’s UVM3, whose adoption increased by 56 percent between 2012 and 2014. Furthermore, our study revealed that UVM is projected to grow an additional 13 percent within the next year.

Figure 4 shows the ASIC/IC industry adoption trends for various assertion languages, and again, SystemVerilog Assertions seems to have saturated or leveled off.


Figure 4. ASIC/IC Assertion Language Adoption

In my next blog (click here) I plan to present the ASIC/IC design and verification power trends.

Quick links to the 2014 Wilson Research Group Study results

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9 October, 2014

DVCon India, held in September 2014 in Bangalore, built on the Indian SystemC User Group meeting events and added a Design & Verification track to its popular system-level design (ESL) track that has been popular for many years.  The main stage played host to the keynote presentations, opening ceremonies and best paper and poster awards.

Several DVCon India keynote presentations, which I will go into more depth later touched on emerging use of virtual platforms in system design and the growing impact India has on design verification.  In particular, Mentor’s CEO, Wally Rhines contrasted Wilson Research survey data on design verification from India and the rest of the world.  A strong adoption of SystemVerilog and its popular methodology, the Universal Verification Methodology (UVM) was clear from the survey results Wally shared.

But even beyond SystemVerilog and UVM, the discuss of what could come next anchored the first day of DVCon India discussion on Accellera’s exploration of “portable stimulus.”  Accellera has a group exploring if the industry is ready to start a standards project on this concept.  And the first day when DVCon India attendees were offered an opportunity to learn about this, the multi-company (Mentor Graphics, Breker & CVC) tutorial on the topic was standing room only.

DVCon Europe – The Stage is Set!

A tutorial slot at DVCon Europe will be devoted to the same topic that was popular at DVCon India.  For DVCon Europe attendees, you will find Tutorial T9, “Creating Portable Tests with a Graph-Based Test Specification” will cover this topic.  Technical representatives from Mentor Graphics and Breker will cover aspects of portable stimulus and offer examples of how it can work.  And early application of the technology will be covered by a representative from IBM.  To cover the topic appropriately, we have modified the presenters listed in the official printed program and full details are available online.  The presenters will be, in this order:

  • Holger Horbach, IBM, Germany
  • Frederic Krampac, Breker, France
  • Staffan Berg, Mentor Graphics, Sweden

Please join us for this tutorial and ensuing conversation and discussion.  Verification productivity is a pressing issue and our ability to better control and create stimulus is a step in the direction to address the verification challenges we all face.

One last note, the concept of “portable stimulus” is language agnostic so no matter which language you use for design and verification, the intention is this technology will be able to help.   The tutorial will help you understand how using a graph-based approach enables the highest degree of verification re-use, from IP block to sub-system to full-system level verification. You will see how it supports verification in SystemVerilog, Verilog, VHDL, C, C/C++, assembly, and even other non-traditional base languages. And it also can be extended from simulation to emulation to FPGA prototyping, and even silicon validation.

I look forward to seeing you at DVCon Europe in Munich!  And if you have not yet registered, please do so to secure your seat.

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11 September, 2014

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year when those taking their first steps to learn VHDL, Verilog/SystemVerilog join the academic “back to school” crowd and those who are using design & verification languages in practice are honing skills at industry events around the world.

A new academic year has started and the Mentor Higher Education Program (HEP) is well set to help students at more than 1200 colleges and universities secure access to the same commercial tools and technology used by industry.  It is a real win-win when students learn using the same tools they will use after graduating.  Early exposure and use means better skilled and productive engineers for employers.

The functional verification team at Mentor Graphics knows that many students would prefer to have a local copy of ModelSim on their personal computer to do their course work and smaller projects as they learn VHDL or Verilog.  To help facilitate that we make the ModelSim PE Student Edition available for download without charge.  More than 10,000 students use ModelSim PE Student Edition around the world now in addition to our commercial grade tools they can access in their university labs.

For the practicing engineer, the Verification Academy offers an online community of more than 25,000 design and verification engineers that exchange ideas on a wide variety issues across the numerous standards and methodologies.  If you are not a member of the Verification Academy, I recommend you join.  You will also find the Verification Academy at DAC for one-on-one discussions and even more recently Verification Academy Live daylong seminars which came to Austin and which will be in Santa Clara – as of the writing of this blog.  There is still time to register for the Santa Clara event and I invite you to attend.

As design and verification is global, Accellera realized that DVCon should explore the needs of the global design and verification engineer population as well.  For 2014, DVCon Europe and DVCon India were born from an already successful running SystemC User Group events.  These user-led conferences will be held so engineers in these areas can more easily come together to share experiences and knowledge to ultimately become more productive.

Students and practicing engineers alike can benefit from fee-free access to some of the popular IEEE EDA standards.   While I don’t think reading them alone is the ultimate way to educate yourself, they make great companions to daily design and verification activities.  Accellera has worked with the IEEE to place several EDA standards in the IEEE Standards Association’s “Get™” program.  Almost 16,000 copies of the SystemC standard (1666) and just about the same number of SystemVerilog standards (1800) have been downloaded as of the end of August 2014.  Have you download your free copies yet?

The chart below shows the distribution of nearly 45,000 downloads which have occurred since 2010.  Stay tuned for breaking news on some updates to the EDA standards in the Get program.  When updated, they will replace the versions available now.  So if you want to have the current versions and the ones to come out shortly, you better download your copies now.  If the electronic version is not sufficient for you, the IEEE continues to sell printed versions.


From students to practicing engineers, the season of learning has started.  I encourage you to find your right venue or style of learning and connect with others to advance and improve your design and verification productivity.

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25 February, 2014

As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less?

In DVCon’s recent past, it was a tradition for the North American SystemC User Group (NASCUG) to sponsor a day of activity before the official start of the conference.  When OSCI merged with Accellera, the day before the official conference start grew to become Accellera Day with a broader set of meetings and activities covering many of Accellera’s standards.  This has all grown into a more official part of the DVCon program.  On Monday at DVCon – or as many still call it – Accellera Day – the tradeshow now joins in opening.  I covered this in detail in an earlier blog, so I won’t repeat myself now.

The pre-conference education and meet-up to discuss the latest in standards development is joined by an end of conference tutorial series that has expanded to allow four parallel sessions from three.  Instead of the one tutorial we at Mentor Graphics would otherwise sponsor at DVCon, we will offer two in this expanded series. Given the impact verification has on design it would seem right that more time be devoted to topics that address this.  One half-day tutorial is just to short to give the subject its due respect.

The two Mentor Graphics sponsored tutorials at DVCon, to be run in series, will devote a day to explore the application of current verification technology by us and users like you.  If you are already attending DVCon, you are making your tutorial selections now.  And for those who might only be interested to attend the tutorials themselves, DVCon offers a tutorials-only package ($145/Tutorial).  Mentor’s two tutorials are:

The first tutorial references “smooth sailing,” not because this will be a “no-pirate zone,” although I can tell you that since International Talk Like a Pirate Day is in late September, one won’t have to worry about a morning of pirate talk! [Interesting Fun Fact: Mentor Graphics’ headquarters in Wilsonville, OR USA is a short 50 miles (~80 km) north of the creators of this parotic holiday.]  The smooth sailing comes from the ability to easily use multiple engines from simulation, formal, emulation, FPGA prototyping to address your block to system-level verification needs.

The second tutorial is all about formal.  Or, in a more colloquial way to say it, we will answer the question: Whatsup with formal?  No, I doubt we will find more slang terms for formal technology being used and created in the tutorial.  But the tutorial will certainly look at more focused applications of formal technology.  As a pioneer in focused formal applications (like clock domain crossing) the creation of these focused formal applications has greatly simplified use and expanded technology access to verification teams with RTL design checks, X-state verification, and more joining the list.  Maybe we should ask Whatsapp with formal! But wait!  That slang question is already taken – and Facebook affirmed ownership with a $19B purchase of it recently.  Oh well, I lament.  Join me at this tutorial and we can explore something suitable and not yet taken as a replacement.  I can’t think of a better way to close DVCon than to see if we can invent another $19B term (or app).

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11 February, 2014

DVCon 2014 LogoOne of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.  And this year’s DVCon is no exception.  The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.  For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers.

UVM LogoI have written in the past about the productivity challenges before us to address the verification crisis and the emergence of machine-to-machine communication and the Internet of Things driving power aware design and verification.  To advance the demands on improved verification and help to address the verification crisis, the next round in the Universal Verification Methodology (UVM) standard is being readied for industry adoption.  UVM 1.2, the emerging update will be covered in some detail in a Monday morning tutorial to help you learn “What’s Now and What’s Next.”  Mentor Graphics’ Tom Fitzpatrick and Accellera Working Group representative will present in this tutorial.

UVM 1.2 is an active development project of Accellera and has not yet been released so there is no official standard available for download and use yet.  I’ll share standardization details as they happen.

At the same time on Monday, those who are concerned with power aware design and verification can attend the tutorial on the Unified Low Power Format (UPF), or as it is officially called IEEE 1801™-2013.  The tutorial will cover the full spectrum of UPF capabilities and methodology from basic to advanced applications.  So if you are new to UPF and want to learn, this is a great tutorial to attend.  And if you are already an expert, the advanced application of UPF as highlighted by those companies who have adopted UPF make this valuable for you as well.  Mentor Graphics’ Erich Marschner and IEEE 1801 Working Group vice-chair will participate in this tutorial.

UPF is an official IEEE standard.  Have you downloaded your copy yet?  Accellera has worked with the IEEE to make no-charge access to the official standard for you.  You can find the UPF standard here.

In the afternoon, there will be a session on case studies in SystemC.  User and vendor presentations will explore use of this standard.  SystemC offers much in the verification space, not just in technology but learning on how to bridge the RTL world with transaction level modeling world.  Mentor Graphics’ John Stickley will review what we have learned and how you can apply it to your most pressing verification needs.

SystemC is an official IEEE standard.  Have you downloaded your copy yet?  Under the Accellera agreement with the IEEE, you can download SystemC standard here.

There is a lot more to DVCon than just the use of current standards and planning adoption of emerging standards.  I encourage you to check out the whole agenda and join me at DVCon 2014 March 3-6.

Mentor Graphics presentations during the conference include:

  • Tuesday Paper Sessions
    • Amit Srivastava – Stepping Into UPF 2.1 World: Easy Solution to Complex
      Power Estimation
    • Kenneth Bakalar – Interpreting UPF For A Mixed-Signal Design Under Test
    • Gordon Allan – Tried and Tested Speedups for Software-Driven SoC Simulatio
  • Tuesday Poster Sessions
    • Rich Edelman – Debugging Communicating Systems: The Blame Game – Blurring
      the Line Between Performance Analysis and Debug
    • Matthew Balance – Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
    • Gaurav K. Verma – Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology
    • Andreas Meyer – So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
    • Rich Edelman – UVM SchmooVM – I Want My C Tests!
    • Thom Ellis – Are  You Really Confident That You Are Getting the Very Best From Your Verification Resources?
    • Jitesh Bansal – Is Your Power Aware Design Really X-Aware
  • Wednesday Paper Sessions
    • Avidan Efody – Wiretap Your SoC: Why Scattering Verification IPs Throughout Your Design Is A Smart Thing To Do
    • Tom Fitzpatrick – Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It

Mentor Graphics will host its traditional lunch at DVCon on Wednesday on the theme of Accelerating Verification.  And we have lively panel participants for the Tuesday and Wednesday panels.  And, as always, the Exhibit, CEO Keynote and Panels are open to all a no charge – you just have to REGISTER!

I look forward to seeing you there!

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