Posts Tagged ‘RevCom’

14 March, 2013

IEEE 1801™-2013 Enters Pre-Publish Phase

The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.

If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).

As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication.  So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet.  So I won’t do that.  If you do need something, the superseded version from 2009 is the only one available at this moment.  I will keep you updated as to when it is published and ready for access to the global design community.

imageMentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled Bringing Verification and Validation under One Umbrella The Evolution of UPF: What’s Next?  (Free access; no registration required; 81KB)

Erich gives a good introduction to the new standard, also known as UPF 2.1.  He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.

Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot.  This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification.  If you are interested to join in with the IEEE 1801 team, visit here for more information.

DVCon UPF Tutorial

The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon.  For those who registered for the conference, the tutorial presentation is still available online.  Unfortunately, the material has not yet been made available to the general public.  If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy.  The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.

As for planning you can do now.  The IEEE 1801 team will host a tutorial at DAC on Sunday.  I will share more information with you on that once the DAC registration site goes live.  Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.

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5 December, 2012

IEEE Std. 1800™-2012 Officially Ratified

The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard.  The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.

What’s New?

The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification.  DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard.  The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics).  You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.

For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance.  As Stu and Tom said in their presentation, “This is BIG!”  If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.

Major work was done to augment the current notion of constraints in SystemVerilog.  In past versions of the standard they were known as hard constraints.  What this meant was all the conditions of the constraints had to be met otherwise there would be an error.  There was no built-in method to relax the need to satisfy the constraints.  Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high.  To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard.  If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard.  Stu and Tom said that “This is also a big enhancement!”


IEEE 1800™-2012 has only now been approved.  The standard itself is not ready to be published yet.  Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013.  I will  share publication information as it becomes available.  And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.

sva3rdE_cover-wsWhile the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now.  For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more.  You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well.  You can find more information about it on here.

The Story Continues…

There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead.  The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.

Stay tuned!  For now, I encourage you to get informed!

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