Posts Tagged ‘register package’

14 October, 2010

23rd Synopsys EDA Interoperability Forum Features a Verification Session with focus on the UVM Register Package

UVM_Logo As readers of the Verification Horizons BLOG know from recent posts, progress towards a register & memory facility in UVM 1.0 is well underway.  While the Accellera VIP-TSC is making good progress, limited information is available to non-participants.  This limited knowledge is true for both eventual users of the standard as well as for many EDA, IP and VIP companies that don’t participate directly in the development activities but whom could benefit from planning for tool and IP interoperability.  As the standard nears completion, it is important for other EDA and IP companies to know how they might collaborate with others in support of the pending standard.

The 23rd Synopsys EDA Interoperability Forum offers EDA and IP companies and others who will integrate the use of tools and Verification IP from several vendors a first look at the new UVM 1.0 Register Package.    The Forum’s 3:15 p.m. – 4:15 p.m. session will focus on Verification and UVM Register Package interoperability.

Mark Glasser, Methodology Architect at Mentor Graphics, will share the presentation time with a couple other presenters.  His presentation is “Building Register Verification Environment in UVM.” We encourage those who can make it to the event and have the time on October 21st to attend to do so.  Mark and other experts will be able to share their UVM development experiences and offer key insight into the newer UVM 1.0 Register Package features.

The event is free of charge, but registration is required to attend this session and any others at the Forum.  Forum details are:

Date: 21 October 2010
Time: 9:30 a.m. – 4:30 p.m.
Location: Oracle Conference Center at Agnews Historic Park, Santa Clara, CA 95054 USA
Forum Website:

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7 September, 2010


Mentor Announces Collaboration with Synopsys on Joint Register Package Candidate

Mentor has recently teamed with Synopsys to collaborate on the Synopsys RAL candidate to provide extensions that meet our register package requirements.  Because of this, it allowed us to withdraw our candidate from consideration by the Accellera VIP-TSC recently.

Further, as part of the Accellera VIP-TSC UVM development process, a request was made for companies that would have candidate solutions to hold public review meetings to share high-level information about their proposals.  There is such a review meeting for this candidate on Wednesday, 8 September 2010 at 8am PDT.

You are invited to join the presentation on WebEx and listen live on the teleconference by Mentor’s Tom Fitzpatrick and Synopsys’ Janick Bergeron as they cover the details of Synopsys RAL for UVM.  For more information on the event, visit the Main UVM Forum on by clicking here.

There are more elements to UVM 1.0 that are not part of a public review process and I invite you to visit the committee website where you can find official status on Accellera UVM development or to participate in the committee.  The committee website is located at

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28 May, 2010

UVM_Logo UVM Layering Package updated from OVM Layering Package

In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM.  This package has been updated and tested to work with UVM 1.0 EA and is ready for download.

As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementations.  The package also provides the DVCon paper and presentation that describes it in more detail in case you did not attend DVCon.

Users have found layered sequences can make verification life easier as sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in.  The package is a companion to the UVM 2.0 Register Package that was also updated from OVM to UVM.

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19 May, 2010

UVM_Logo Mentor supplies the first Register Package for UVM

As I mentioned in my earlier blog post to disclose Mentor’s support of UVM-EA on the Questa Verification Platform, we would bring forward other OVM elements and make them UVM ready.  We have done this for the OVM register package.

For those who are looking at the UVM-EA and want to avail themselves of additional UVM-ready value added elements, you can download the UVM Register Package 2.0 and use it today.

Users noted that the HTML documentation for the OVM version was missing.  This been corrected and complete online documentation is now at your fingertips.  You can use the navigation bar at the left to expand categories and click on the topic of choice.  The body of the documentation is also hyperlinked for convenient navigation to related topics and more detailed descriptions of the particular class method or variable.

For completeness, the updated OVM Register Package 2.0 that has corrected HTML documentation can be found here.

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12 May, 2010


Download Now

A new OVM Layering Package that provides a means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementation is available for download.

The DVCon 2010 paper on this topic, You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction, is also part of the download kit.  The paper demonstrates building layered stimulus using OVM sequences and sequencers. Virtual sequences and virtual sequencers are highlighted by building a small collection of examples that can be used in layered stimulus verification environments. The main contribution of this paper is a new layering component that performs the standard layering task while minimizing user programming without requiring exotic connectivity, extended components or the use of the factory.

Using layered sequences can make your verification life easier, since sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in.  To learn more, download the kit.  You will also find a presentation in the kit and how to use  it with the OVM 2.0 Register Package mentioned in my last blog.

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10 May, 2010

logo_OVM In January 2010 we released the OVM 1.0 Register Package.  It has now been updated to enhance capabilities and address issues raised by users.  The updated contribution can be downloaded from OVM World.

The OVM 2.0 Register Package builds on 1.0 with new built-in register tests, easier cloning and copying of registers and register maps.  The code has been ported to other implementations besides Questa.

A list of some of the new features for OVM 2.0 Register Package include:

  • Added built-in tests
    • register_alias – write one register, read all
    • power_on_reset – read all registers, check against reset value
    • walking_zeros – write walking zeros, read back, compare
    • walking_ones – write walking ones, read back, compare
    • write_read – do a write then a read
  • Ported to other implementations
    Certain SystemVerilog features and capabilities are re-implemented for other implementations. Those changes are wrapped with the appropriate `ifdef. You can run Questa with those turned on if you like.Due to the port, any function that returned a list had to be changed to return the list as an output argument to the function.
  • Added compare_read_only_bits for selective inclusion or exclusion of read-only bits in the compare
  • Added mapped_register_container (replaces ovm_register_map_base)
    You can now add a register file to another register file (in addition to all previous behavior)
  • ‘resetvalue’ in register constructor is now deprecated

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23 February, 2010

Duolog Joins Agnisys to Add Reg Pac Support

The OVM 1.0 Register Package has had a lot of interest since uploaded a few weeks back.  With more than 1,100 downloads and counting, it is being qualified for use and deployment in a growing number of user verification environments.

Complementing the availability of the OVM 1.0 Register Package is support by partners with their applications that promote greater verification efficiency and use of the register package.  Today, Duolog joined Agnisys to announce an update to their OVM auto-generation solution to now support the OVM 1.0 Register Package on the Mentor Questa verification platform.

OVMWorld offers a unique, active and vibrant contributions area tfor the OVM community to explore supplemental packages from any source to augment the base OVM kit.  There are a large number of partners that, as in the case of Doulog and Agnisys, have added to the user experience with the direct support of the OVM 1.0 Register Package..

You can catch Duolog representatives around DVCon this week to see how they can help you take advantage of the ever expanding OVM contributions.

What OVMWorld contributions have you liked the best?  Which ones should be added to the base OVM kit?  Do you have something to share?  We would like to understand what your priorities are to promote community contributions into the main kit.

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26 January, 2010

logo_OVM After months of field testing and several beta releases the past few years, Mentor Graphics has released the OVM 1.0 Register Package.  The package can be download from the contributions area.

The download includes complete online HTML-based documentation at your fingertips. You can use the navigation bar at left to expand categories and click on the topic of choice. The body of the documentation is also hyperlinked for convenient navigation to related topics for more detailed descriptions of a
particular class method or variable.  The download also includes the OVM Register Package User Guide and the  OVM Register Package Reference Guide to help you.

Requirements for continue verification productivity improvements show no signs of easing.  Demands on OVM to manage and control registers in SOC designs is just one example of the pressing productivity improvement requirements.  SOC’s not only have high registers counts, but the relationship between operating modes defined by the resisters can be very complex. The OVM 1.0 Register Package addresses those issues.

We continue to seek feedback on your application of the OVM 1.0 Register Package at to enhance and advance verification productivity.

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