Posts Tagged ‘questa’

7 April, 2016

We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how Questa VIP PCIe Starter Kits make a Verification engineer’s life easy.

Xilinx® recently posted the “UltraScale PCIe PIPE Simulation with Mentor QVIP” YouTube video that demonstrates how easy it is to hook Questa Verification IP to a Xilinx® PCIe IP.

Some key take-aways from the video:

  • Generate a PCIe IP using the Xilinx Vivado® tool
  • Download the starter kits from Mentor Supportnet
  • Use the starter kit to plug in a UVM testbench for your PCIe
  • This UVM testbench has scoreboarding and coverage enabled
  • Ready to use sequences
  • Plug & Run the UVM simulation using PCIe QVIP starter Kit.
  • Check the log for generated transactions e.g TLP packets.

I hope you take 10 minutes to check out the video. Bring up of a UVM environment for Xilinx® PCIe IP could not have been easier.

Are you using Xilinx® PCIe IP in your project? If so, try out the PCIe starter kit and let me know how easy it is to get your UVM testbench up and running so you can spend your cycles on Verification.

Looking forward to hearing your comments on the video and the PCIe starter kit.

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29 July, 2015

VA DAC2015 smlIf you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed an opportunity to get a printed copy of the DAC 2015 issue of Verification Horizons, don’t worry.  You can also download it as well.

Questa Vanguard Partners Highlighted

Eight of the eleven articles were authored or co-authored by our partners and represent a wide range of topics.  There are two articles on DO-254 (Partners: eInfochips and Verisense).  There is an article on Formal and ABV of MBIST MCPs (Parnter: FishTail Design Automation).  There is an article on how to start formal analysis “right” (Partner: OSKI).  For UVM users, reuse of MATLAB® functions and Simulink® functions is covered (Partner: Mathworks).  Continuing with another article for the UVM users, intelligent testbench automation with UVM and Questa® is explored (Partner: Codasip Ltd.).  For the Agile community, unit testing your way to a reliable testbench is explored (Partner: XtremeEDA & User company: NVIDIA).  Lastly, a noted emulation consultant (Lauro Rizzatti) shares part 2 of his three decades of emulation evolution and a customer paper (Marvell) covers techniques to accelerate RTL simulation.

VH DAC 2015 CoverAll of this is inside the 60-page mega-issue of Verification Horizons in 11 articles.  Direct links to each of the articles is shared below along with the article titles and authors.  The editor introduction by Tom Fitzpatrick gives even more detail and background on this issue.  If you don’t already have some summer or vacation reading, get your electronic copy today!

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3 April, 2015

It is always good to pause to recognize the companies and individuals with whom we collaborate to create the verification flows and solutions that allow the simplest and most complex devices and systems to come to life.  It is this time of year when the fruit of collaboration has generally been shared publicly.  This is probably the case, in no small part, to the nearing of the annual trek to the Design Automation Conference (DAC).  As we get closer to that week in June this year, I will discuss it even more.  But now I would like to offer a look back at two major milestones around this time of the year that shaped our future.

20 Years Ago

On April 3, 1995, we announced “Device Vendors Providing Library Support to Mentor.”  Our ModelSim simulator gained support from 12 ASIC and programmable logic vendors.  Until then, Mentor’s gate-level simulation was provided by QuickSim and its large collection of ASIC vendor libraries and flows.  With the emergence of VITAL (VHDL Initiative Towards ASIC Libraries) and as an IEEE standards project for it (1976.4) emerged, we continued our activities to drive knowledge about VITAL and educate and help the rest of the ASIC vendor community so they could bring to market their own simulation libraries for ModelSim.

As we added Verilog to the language mix, those Verilog libraries were likewise qualified and offered to the mutual customers we shared with our valued ASIC Vendor partners.  ModelSim grew to be a very popular product and the value of collaboration taught us the importance of shared collaboration.

10 Years Ago

In mid May 2005, we launched our Questa Vanguard Partnership (QVP) program modeled on the ModelSim program.  SystemVerilog 3.1a had been released by Accellera and was in the final stages of IEEE certification which was to come in November 2005.  But to get a jump on solidifying business relationships with our partners and to encourage support of SystemVerilog we began to work with companies around the world who expressed an interest to build a vibrant ecosystem.  A lot was accomplished in the six months between the launch of the QVP program to the approval of the first IEEE SystemVerliog 1800-2005 standard.

But it was good to pause then too and celebrate the standard with our new Questa partners, our mainstay semiconductor library partners and competitors in Japan.  Upon IEEE approval of the standard, Accellera in conjunction with the Big-3 EDA companies and CQ Publishing (Japan), held a “Happy Birthday” celebration reception.  I have to offer special thanks to my friends at Synopsys for the idea.  And, yes, we all know that this November will be lucky 10 years for SystemVerilog and we have already started to discuss what can be done at the annual fall standards meetings in Japan to celebrate this milestone.

Tomorrow (DAC)

As I mentioned, the great thing about this time of the year is the planning for DAC.  Many good things have happened in the last year.  Last year, at Mentor Graphics’ urging and our public commitment to donate technology, Accellera started a “Proposed Working Group” on Portable Stimulus to determine the viability of a standards project.  Accellera formally approved the formation of the Portable Stimulus Working Group in December 2014.  At the Verification Academy booth at DAC, we will certainly offer updates on this work and affirm our sustained commitment to the development of this standard.  I will share full details about what, when and where for the Verification Academy booth at DAC later.

But wait!  There will probably be more.  I can assure you, I will post a few more times during this final two-month journey to DAC.  And as the daily program for the Verification Academy booth is finalized, I will share its content my thoughts on this.  And as industry events, like the Accellera DAC Breakfast are finalized, I will make this part of my commentary on DAC 2015 as well.  It seems this DAC will be a busy DAC.

But this is something you can do now!  If you don’t know if you want to attend the technical program yet, you should at a minimum secure a free pass to the exhibit floor and access to some open industry events.  If you register by May 19th, you can choose the “I Love DAC” registration – complements of ATopTech, Atrenta, and Calypto.  After May 19th, it is no longer free.  So why not register now?  I look forward to seeing you at DAC.

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19 March, 2013

We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to get your hands on 10.2 and take a more in-depth look for yourself.

The first thing you’ll notice is that we’ve enhanced to Structure Window (usually located in the upper left of the debugger) to show the class type of each UVM component in your testbench. This will make it easier to know exactly what your factory settings and other configuration settings have yielded as you built your testbench.

One of the most common requests we’ve gotten is to provide a way to see what exactly is happening with the configuration database (uvm_config_db). In the UVM Details window, you can now see the values that are available to the selected component, and by right-clicking you can see who wrote the value and where the write occurred.

In the Stream view of the Details window, you can see all of the transaction streams being recorded by the selected component.

Also, when debugging UVM processes, the Processes Window now includes the hierarchical path to the component that initiated the process.

Lastly, for those of you who may not be GUI-centric, we’ve added a new “uvm” command to the command-line interface in the transcript window (or via “.do” files):

uvm subcommand [args...] 

where the “subcommand” lets you choose from a number of options. The default subcommand (and in my opinion, the coolest) is the “call” command, which allows you to call UVM functions directly from the command line. You can even call functions in UVM components by referring to the components via their hierarchical name

uvm call test_top.env1.fab.get_full_name

or via a handle provided by Questa (as seen in the Class Instances window).

call @myClassType@223.get_full_name 

There are other useful UVM commands that I won’t go into here, but you should definitely check them out. So, what are you waiting for? To find out more information about Questa with this link:


21 February, 2012

Is my car trying to tell me something?

This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA).  (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology – demonstrated by a standing room only training event – has got to be a tipping point indication for iTBA.

I turned my car on.  (Actually, I “pushed” it on as there is no place to put a key to turn anymore.)

Tornado-bp2Moments after starting my car a winter storm alert interrupted the music on the radio and displayed two notices.  One I am familiar with when the temperature falls and snow begins to collect on the mountain passes.  I’m not going to drive in the direction of the snow, so no problem.  The other alert was of grave concern.  It was a tornado watch.  And the tornado watch was not off in some other direction many miles away, it was “0 miles” from me.  I looked up, I scanned the horizon and dark black was in one direction and sun in the other.  I changed the radio channel to a local AM evening drive station, but no mention of a tornado watch.  I headed in the direction of the sun.  It seemed the safest direction to head.  But before I did, I snapped a quick picture as proof I actually read “Tornado Watch” on the car’s navigation screen.

iTBA to the Rescue?

I returned to ponder if functional verification has just gotten too big for current techniques that iTBA is going from a nice to have, to a must have.

Several years back it was popular to brag about the compute farms & ranches one had.  With 5,000 machines here and another 5,000 machines there it seemed a sane demonstration of one’s design and verification prowess.  But this gave way to 50,000 multicore machines and who is talking about this with pride?  All talk is out of necessity.  And what about the next step?  Who has 500,000 or 5,000,000 on the drawing board or in their data centers?  Looking around, it seems very few admit to more than 100,000 and even fewer have more than 500,000.

Verification may be in crisis, as many will say, but it you hold verification technology constant, it is not in crisis, is on a  collision coarse with disaster.  Addressing this crisis has been the theme of many of Mentor Graphics CEO Wally Rhines’ keynotes at DVCon.  His 2011 keynote was taken to heart by many who attended.  The need to improve by a several orders of magnitude the “Velocity of Verification” has been followed by several examples over the year.

One example was shared several months after DVCon when Mentor Graphics and TSMC announced we had partnered to validate advanced functional verification technology.  While not all test results at TSMC or our common customer, AppliedMicro, were revealed, one of the slower tests demonstrated the value of iTBA to shorten time-to-coverage by over 100x.  Even days after that announcement we disclosed Mentor’s Veloce emulation platform offered 400x OVM/UVM driven verification improvement.

100x  and 400x seem like a large numbers, but it appears even bigger when you put it into the context of the time it was measured.  With current constrained random techniques, a project that takes 6 weeks of simulator run time to reach 100% closure can reach it in about 10 hours with Questa inFact or about 2.5 hours with Veloce.  Instead of using complex scripts to peek in on a simulation run over the course of a month and a half, a verification team could actually leave work for the day, return the next morning and have a full, complete and exhaustive verification run.  And when even faster turnaround time is needed, emulation returns results during the work day.

SoC Verification: A Balance of simulation, iTBA & emulation

Wally’s DVCon 2011 keynote referenced 8 customer results coming from Mentor’s Questa inFact tool.  Many more have discovered what this can do for them as well.  And with each success, come the requests from more to see what it can do for them.

But changing the “Velocity of  SoC Verification” has not rested on one technique alone.  Stop by the Mentor Graphics DVCon booth and we can share with you the advances we have made to address system-level verification since last year.

Crossing The Chasm

Which brings me to the point of the “Tornado Watch.”  As I pondered the iTBA tipping point, about “how little things can make big differences” as can be found in Malcolm Gladwell’s book, my car must have been channeling Geoffrey Moore of  “Crossing The Chasm” fame instead.  For that reason it must have issued the Tornado Watch.  Could it be that iTBA is set to cross the chasm from early adopters to the early majority?

And thankfully, I don’t think my car is programmed to issue tipping point warnings, nor do I want to see if it can.

In the end, it will be with the benefit of hindsight that let’s us know if we are crossing the chasm into the tornado or not now or soon.  But for Mentor’s part, full and advanced support of iTBA technology with Questa inFact is ready now, and we are set to cross the chasm into the tornado.   My colleague, Mark Olen, blogs about iTBA here.   If you have not had a chance yet to read his blog on iTBA delivering 10x to 100x faster functional verification, it is worth the time to do so.  You can look for him to give frequent updates on iTBA and comment on the positive impact is has on SoC design and verification teams in the months ahead.

I look forward to seeing you at DVCon.

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8 March, 2011

by Rich Edelman and Dave Rich


The UVM is a derivative of OVM 2.1.1. It has similar use model, and is run in generally the same way.

One significant change is that the UVM requires a DPI compiled library in order to enable regular expression matching, backdoor access and other functionality.

When running UVM based testbenches, we recommend using the built-in, pre-compiled UVM and DPI compiled libraries. This will remove the need to install any compilers or create a “build” environment.

One other issue to mention if you are converting from OVM to UVM, and if you use stop_request() and/or global_stop_request(), then you will need to use the following plusarg, otherwise your testbench will end prematurely without awaiting your stop_request().


Simulating with UVM Out-Of-The-Box with Questa

The UVM base class libiraries can be used out of the box with Questa 10.0b or higher very easily. There is no need to compile the SystemVerilog UVM package or the C DPI source code yourself. The Questa 10.0b release and every release afterwards contains a pre-compiled DPI library, as well as a pre-compiled UVM library. The only dependency is that your host system requires glibc-2.3.4 or later installed. Questa 10.0c Windows users only, please read this important note about the location of the DPI libraries.

You can easily use these steps:

vlib work
vsim hello …

Notice that we don’t have to specify +incdir+$(UVM_HOME)/src,  $(UVM_HOME)/src/  to vlog, or add a -sv_lib command to the vsim command to load the uvm_dpi shared object.

Controling UVM Versions

Each release of Questa comes with multiple versions of the UVM pre-compiled and ready to load.  By default, a fresh install of Questa will load the latest version of UVM that is available in the release.  If an older version of UVM is needed, this version can be selected in one of two ways.

Modify the modelsim.ini File

Inside the modelsim.ini file, it contains a line which defines a library mapping for Questa.  That line is the mtiUvm line.  It looks something like this:

mtiUvm = $MODEL_TECH/../uvm-1.1b

This example is pointing to the UVM 1.1b release included inside the Questa release.  If we wanted to downgrade to UVM 1.1a, then we would simply modify the line to look like this:

mtiUvm = $MODEL_TECH/../uvm-1.1a

Command Line Switch

The Questa commands can also accept a switch on the command line to tell it which libraries to look for.  This switch overrides what is specified in the modelsim.ini file if there is a conflict.  The switch is ‘-L’.  If this switch is used, then all Questa commands with the exception of vlib will need to use the switch.

vlib work
vlog -L $QUESTA_HOME/uvm-1.1a
vsim hello -L $QUESTA_HOME/uvm-1.1a ...

If you are using some other platform, or you want to compile your own DPI library, please follow the directions below.

If you use an earlier Questa installation, like 6.6d or 10.0, then you must supply the +incdir, and you must compile the UVM.

For example, with 10.0a on linux, you can do

vlib work
vsim -c -sv_lib $UVM_HOME/lib/uvm_dpi …

if you use your own UVM download, or you use Questa 6.6d or 10.0 you need to do the following:

vlib work
vlog +incdir+$UVM_HOME/src $UVM_HOME/src/
mkdir -p $UVM_HOME/lib
g++ -m32 -fPIC -DQUESTA -g -W -shared
-o $UVM_HOME/lib/
vlog +incdir+$UVM_HOME/src
vsim -c -sv_lib $UVM_HOME/lib/uvm_dpi …

Building the UVM DPI Shared Object Yourself

If you don’t use the built-in, pre-compiled UVM, then you must provide the vlog +incdir+ and you must compile the UVM yourself, including the DPI library.

In $UVM_HOME/examples, there is a Makefile.questa which can compile and link your DPI shared object.

For Linux (linux):

cd $UVM_HOME/examples
setenv MTI_HOME /u/release/10.0a/questasim/
make -f Makefile.questa dpi_lib

> mkdir -p ../lib
> g++ -m32 -fPIC -DQUESTA -g -W -shared
>   -I/u/release/10.0a/questasim//include
>   ../src/dpi/ -o ../lib/

For Linux 64 (linux_x86_64)

cd $UVM_HOME/examples
setenv MTI_HOME /u/release/10.0a/questasim/
make LIBNAME=uvm_dpi64 BITS=64 -f Makefile.questa dpi_lib

> mkdir -p ../lib
> g++ -m64 -fPIC -DQUESTA -g -W -shared
>   -I/u/release/10.0a/questasim//include
>   ../src/dpi/ -o ../lib/

For Windows (win32):

cd $UVM_HOME/examples
setenv MTI_HOME /u/release/10.0a/questasim/
make -f Makefile.questa dpi_libWin

> mkdir -p ../lib
> c:/QuestaSim_10.0a/gcc-4.2.1-mingw32vc9/bin/g++.exe
>   -g -DQUESTA -W -shared
>   -Bsymbolic -Ic:/QuestaSim_10.0a/include
>   ../src/dpi/ -o
>   ../lib/uvm_dpi.dll
>   c:/QuestaSim_10.0a/win32/mtipli.dll -lregex

Note: For Windows, you must use the GCC provided on the Questa download page: (

Save to /tmp/
unzip /tmp/
<creates the GCC directories in the MTI_HOME>

Using the UVM DPI Shared Object

You should add the -sv_lib switch to your vsim invocation. You do not need to specify the extension, vsim will look for ‘.so’ on linux and linux_x86_64, and ‘.dll’ on Windows.


vsim -sv_lib $UVM_HOME/lib/uvm_dpi -do “run -all; quit -f”


vsim -sv_lib $UVM_HOME/lib/uvm_dpi64 -do “run -all; quit -f”


cp $UVM_HOME/lib/uvm_dpi.dll .
vsim -sv_lib uvm_dpi -do “run -all; quit -f”

Running the examples from the UVM 1.1 Release

If you want to run the examples from the UVM 1.0 Release you need to get the Open Source kit – it contains the examples.

1. Download the UVM tar.gz and unpack it.

2. set your UVM_HOME to point to the UVM installation.

  • setenv UVM_HOME /tmp/uvm-<version#>

3. Go to the example that you want to run.

  • cd $UVM_HOME/examples/simple/hello_world

4. Invoke make for your platform:

  • For Windows (win32)
cd $UVM_HOME/examples/simple/hello_world
make DPILIB_TARGET=dpi_libWin -f Makefile.questa all
# Note: for windows, you need a "development area", with make, gcc/g++, etc. Using cygwin is the easiest solution
  • For Linux (linux)
cd $UVM_HOME/examples/simple/hello_world
make -f Makefile.questa all
  • For Linux 64 (linux_x86_64)
cd $UVM_HOME/examples/simple/hello_world
make BITS=64 -f Makefile.questa all

Migration from OVM to UVM

An OVM design can be migrated to UVM using a script. Many OVM designs can work without any hand coded changes or other intervention. It is a good idea to first get your design running on the latest version of OVM 2.1.2, before starting the migration process.

These designs can be converted from OVM to UVM using the distributed conversion script:


In certain cases hand coded changes might be required.

Using the ovm2uvm script, you can run a “dry run” try and see what must be changed. There are many options to the script. Before using it, you should study it carefully, and run it in ‘dry-run’ mode until you are comfortable with it. In all cases, make a backup copy of your source code, before you use the script to replace-in-place.

By default it does not change files.

Here is a simple script which copies the ovm code, then applies
the script.

# Copy my ovm-source to a new place.
(cd ovm-source; tar cf – .) | (mkdir -p uvm-source; cd uvm-source; tar xf -)

# Do a dry-run
$UVM_HOME/bin/ -top_dir uvm-source

# Examine the *.patch file

# If satisfied with the analysis, change in place
$UVM_HOME/bin/ -top_dir uvm-source -write

If you are migrating to the UVM from OVM, you are NOT required to use this script, but you must do a conversion by some means.

Once your OVM design is converted to UVM, you are almost ready to run.

The UVM requires that you use some DPI code. Additionally, the UVM defines a different semantic for run(). If you are using an OVM design converted to UVM, and you use stop_request() or global_stop_request(), then you need to add a switch:


In order to NOT use this switch, you need to change your OVM design. You need to NOT use stop_request() or global_stop_request(). You should cause your test and testbench to be controlled by raising objections as the first thing in your run tasks, and then lowering your objections where you previously had your stop requests.

More information about migrating from OVM to UVM can be found in the Verification Academy Cookbook (registration required).

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19 May, 2010

UVM_Logo Mentor supplies the first Register Package for UVM

As I mentioned in my earlier blog post to disclose Mentor’s support of UVM-EA on the Questa Verification Platform, we would bring forward other OVM elements and make them UVM ready.  We have done this for the OVM register package.

For those who are looking at the UVM-EA and want to avail themselves of additional UVM-ready value added elements, you can download the UVM Register Package 2.0 and use it today.

Users noted that the HTML documentation for the OVM version was missing.  This been corrected and complete online documentation is now at your fingertips.  You can use the navigation bar at the left to expand categories and click on the topic of choice.  The body of the documentation is also hyperlinked for convenient navigation to related topics and more detailed descriptions of the particular class method or variable.

For completeness, the updated OVM Register Package 2.0 that has corrected HTML documentation can be found here.

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