Posts Tagged ‘emulation’

6 December, 2016

Emulation technology has been around for a long time—more than four decades by my count—and industry observers believe more than ever that it’s a key ingredient in the IC verification strategy, albeit with a rebirth. The question is, what is this new era of emulation all about and why is hardware emulation, which remained on the fringes of IC design ecosystem with a small customer base for many years, now becoming a mainstream design tool for system-on-chip (SoC) verification? The answer can be found in the advent of bigger and more complex chips that often contain multiple processor cores and exceed 100 million gates.

In a nutshell, a register-transfer-level (RTL) simulator, a go-to verification tool is being challenged as design capacity surpasses 100 million gates.  Greater gate counts are possible because of the scaling roadmap for processors.  After all, there is only so much you can do with multi-threading. Next, even hardware-description-language (HDL) software simulators running in parallel over PC farms don’t create a viable option because design-under-test (DUT) environments are sequential in nature.

On the other hand, hardware emulation, once the staple of large IC designs like processors and graphic chips, is now becoming a popular verification tool precisely because it runs faster than HDL simulators for full-chip verification. A hardware emulation tool can run the verification of large, SoC designs over 10 times and sometimes much greater than 10 times faster than software simulation.

Graphic 1 for blog

The view of the key verification modes supported by Mentor Graphics’ Veloce emulator platform.

Hardware emulation has been steadily evolving over the past decade or so, as the cost of ownership is coming down while emulation tools are becoming easier to install and operate. And with the changing equation of emulator ROI and SoC design imperatives, an increasing number of IC designers are inclined to use emulation tools for debugging the hardware and testing hardware and software integration. Moreover, emulation tools are becoming more versatile, ranging from in-circuit emulation (ICE), where physical devices are cabled to the emulator, to more innovative co-emulation solutions like Veloce VirtuaLAB that virtualizes the interfaces amid the growing functionality of today’s SoC designs.

Software simulation or hardware emulation

A simulator tries to model the behavior of the SoC or system-level design while an emulator creates an actual implementation of the design. Here, it’s important to note that both software simulators and hardware emulators are employed for design verification—a stage also known as design-under-test or DUT—where a compiler converts the design model into a data structure stored in memory.

However, in the case of simulation, a software algorithm processes the data representing a design model using a design language, while an emulator processes the data structure using a compute engine enabled by a processor array. Although hardware emulation is growing beyond a $300 million market, it doesn’t mean that it’s going to be the end of the road for HDL simulation tools.

 large SoC graphic

The Veloce emulator, which supports both traditional ICE and transaction-based verification, runs verification of SoCs with multiple protocol interfaces.

HDL-based software simulation will most likely remain the verification engine of choice, especially at the early stage of verification process—for instance, at the IP and subsystem levels—as it represents an economical, easy-to-use, and quick-to-setup EDA tool. On the other hand, emulation will gain traction in larger SoC designs that encompass millions of verification cycles and where hardware bugs are difficult to find. In other words, the two EDA tool markets for SoC and system-level design verification will co-exist for the foreseeable future.

, , , , , , , , ,

22 September, 2016

Join us for the Verification Academy Live Seminar on Enterprise Debug & Analysis

Your designs are larger and more complex than ever and your verification solutions are generating more information that needs to be managed and analyzed.  Your need to build and validate systems with pre-built design IP that comes from multiple sources places time-to-market burdens on you that need to be addressed. Your ability to debug your system from the design described in RTL running on simulation farms to emulators and FPGA prototypes with eventual debug of post silicon implementation drives even more complexity.  And in the face of the adoption of newer methodologies like UVM, often embraced in unstructured ways, poses its own productivity burdens.

This pressure shows itself in our annual semi-annual industry survey results that illustrates there are now more verification engineers than design engineers for a team (a recent phenomena) and the time spent on debug now approaches 40% of an engineer’s total project time budget.

Clearly, improving debug productivity for an enterprise flow from block to system pre-silicon verification, virtual prototyping, emulation, as well as post-silicon validation is critical to stay on schedule and at the same time meet your end product quality goals.

We invite you to join us for a comprehensive seminar to learn the very latest verification techniques to address these challenges.  Harry Foster, Mentor Graphics Chief Verification Scientist, will review the 2016 Wilson Research Group Functional Verification Study in his featured keynote to open the seminar.  The seminar will review enterprise-level requirements, solutions and offer additional end-user keynotes that will help address your key challenges.  Click here for more information about the seminar and how to register.  Event details are below:

Verification Academy Live Seminar

  • Location: Santa Clara, CA USA
  • Date: Thursday – October 6, 2016
  • Agenda:
    • 08:30 – 09:00 Check in and Registration
    • 09:00 – 09:50 Industry Trends in Today’s Functional Verification Landscape
    • 09:50 – 10:10 Enterprise Verification Required
    • 10:15 – 11:00 Enterprise Debug for Simulation & Formal
    • 11:00 – 11:15 Break
    • 11:15 – 12:00 Shortcut to Productive Enterprise Verification with VIP, a UVM framework and a configuration GUI
    • 12:00 – 12:40 Lunch
    • 12:40 – 13:10 User Keynote Session
    • 13:10 – 13:40 Enterprise System Level Analysis
    • 13:40 – 14:00 Break
    • 14:00 – 14:40 System-Level Debug with Emulation
    • 14:40 – 15:10 User Keynote Session
    • 15:10 – 15:50 FPGA Prototyping: Maximize your Enterprise Debug Productivity
    • 15:50 – 16:00 Closing Remarks and Prize Drawing

, , , , , , ,

2 May, 2016

Just over a decade ago, Mentor Graphics had initiated a technology forum in India called the ‘EDA Tech Forum’, this Industry event focused on diverse technologies in the EDA & Semiconductor domains. I, as a customer was regular in attending these forums to get a first-hand knowledge and experience in the ever-changing technology world. This was a great platform for me to learn about the upcoming technologies and methodologies. This also provided an opportunity to interact and network with various technology leaders from the industry.

The EDA Tech Forum was an overwhelming success with larger and larger participation year on year. About seven years ago, this forum got diversified from a combined tech forum to technology-focused forum, thus emerged the Mentor Verification Forum.

It has been close to five years since I have joined Mentor. I have been driving this event for over four years. Being amongst the audience in the past has undoubtedly helped me relate to what most participants would like to take away from such an event and keeping that perspective in mind helps me create an agenda that is appreciated by the audience.

This years’ Mentor Verification Forum is on 5th May 2016 at Vivanta by Taj at M.G Road. Here are the highlights of this year’s event:

  • Mentor’s Keynote – Fight for Future of Verification: Live In It Today by Steve Bailey, Director of Emerging Technologies, Mentor Graphics
  • Industry Keynote – Doing more for less – Verification for the IoT age by Namratha Jaisimha, Sr. Director – Engineering, Qualcomm India
  • Industry Vision Talk by Gyana Bardhan Pattanaik, Group Head, Embedded Division, L&T Technology Services

The agenda also comprises of Industry testimonials and technology discussions on various latest trends in the industry such as Portable Stimulus, Easy to use Memory Models, Verification of Security Domain and using emulation for Low power verification. You will also have the opportunity to visit the booths of IEEE, Mentor Channel partners & Questa Vanguard Partners.

If you haven’t already registered, here is the link to the registration. Don’t miss this opportunity to participate, network and take something away from this forum.

, ,

25 April, 2016

Having been deeply involved with Universal Verification Methodology (UVM) from its inception, and before that, with OVM from its secret-meetings-in-a-hidden-hotel-room beginnings, I must admit that sometimes I forget some of the truly innovative and valuable aspects of what has become the leading verification methodology for both ASIC (see here) and FPGA (see here) verification teams. So I thought it might be helpful to all of us if I took a moment to review some of the key concepts in UVM. Perhaps it will help even those of us who may have become a bit jaded over the years just how cool UVM really is.

I have long preached that UVM allows engineers to create modular, reusable, randomized self-checking testbenches. Of course, these qualities are all inter-related. For example, modularity is the key to reuse. UVM promotes this through the use of transation-level modeling (TLM) interfaces. By abstracting the connections using ports on the “calling” side and exports on the “implementation” side, every component in a UVM testbench is blissfully unaware of the internal details of the component(s) to which it is connected. One of the most important places where this abstraction comes in handy is between sequences and drivers.

seq2driverconnection Figure 1: Sequence-to-Driver Connection(s)

Much of the “mechanical” details are, of course, hidden by the implementation of the sequencer, and the user view of the interaction is therefore rather straightforward:

seqdriverapi Figure 2: The Sequence-Driver API

Here’s the key: That “drive_item2bus(req)” call inside the driver can be anything. In many cases, it will be a task call inside the driver that manipulates signals inside the virtual interface, or the calls could be inline:

task run_phase(uvm_phase phase);
  forever begin
    my_transaction tx;
    @(posedge dut_vi.clock);
    dut_vi.cmd  = tx.cmd;
    dut_vi.addr = tx.addr; =;
    @(posedge dut_vi.clock)
endtask: run_phase

As long as the get_next_item() and item_done() calls are present in the driver, everything else is hidden from the rest of the environment, including the sequence. This opens up a world of possibilities.

One example of the value of this setup is when emulation is a consideration. In this case, the task can exist inside the interface, which can itself exist anywhere. For emulation, the interface often will be instantiated inside a protocol module, which includes other protocol-specific information:

dualtop Figure 3: Dual Top Architecture

You can find out more about how to set up your environment like this in the UVM Cookbook. And if you’re interested in learning more about setting up your testbench to facilitate emulation, you can download a very interesting paper here.

The flexibility of the TLM interface between the sequence and the driver gives UVM users the flexibility to reuse the same tests and sequences as the project progresses from block-level simulation through emulation. All that’s needed is a mechanism to allow a single environment to instantiate different components with the same interfaces without having to change the code. That’s what the factory is for, and we’ll cover that in our next session.

I’m looking forward to hearing from the new and advanced UVM users out there!

, , , , , ,

25 October, 2015

Verification Academy Brings “UVM Live” to the Santa Clara Convention Center

Uvm logoFor everyone involved in the functional verification of electronic systems, you know about the Universal Verification Methodology (UVM) and are probably using it in one fashion or another.  And if you have been reading this blog, you have undoubtedly seen blogs by Harry Foster on the adoption and use of UVM by the FPGA and ASIC/SoC community.  It has clearly become the world’s most popular and accepted verification methodology.  It is odd to point out that with this popularity, there has not been a UVM-only event to bring UVM users together this year.  We believe it is time for UVM users to come together to explore its use and share productivity tips and tricks with each other.  You are invited to register and attend.  The details of the event are:

          Event: UVM Forum – Verification Academy Live Seminar
          Location: Santa Clara Convention Center, Santa Clara, CA USA
          Date: 17 November 2015
          Time: 8:30 a.m. – 4:00 p.m. PT
          More Information & Agenda: Click Here
          Register: Click Here

Experts Learn Something New

If you are an UVM Expert, and already know just about everything about UVM, you might be interested in some new topics that will be introduced and expanded upon.  Here are four:

The first is UVM Framework.  UVM Framework supports reuse across projects, sites and companies from block to chip to system for both simulation and emulation.  Those using it have seen at least a four week reduction in verification product schedules.

The second is Verification IP.  VIP can help you overcome your IP verification challenges.  One session will explore integrating VIP into a UVM environment with examples based on protocols such as AMBA®, MIPI® and PCI Express®.  If you are not an expert on a specific protocol, you can use VIP to drive stimulus and verify protocol compliance for you.

The third is Automating Scenario-Level UVM Test with Portable Stimulus.  In this session you will learn to rise above the transaction level to make scenario creation more productive.  You will learn how to leverage lower-level descriptions, such as sequence items, into larger scenarios.  You will learn how to leverage graph-based methods to efficiently and predicable exercise the scenario space to deliver high quality verification results.  It should also be noted, that an ongoing Accellera Working Group is exploring standardization of Portable Stimulus.  While Accellera working group details are not part of the session, UVM Forum attendees might consider augmenting their knowledge by visiting the Accellera Portable Stimulus group.

The fourth is Improved UVM Testbench Debug Productivity and Visibility.  For those who debug UVM on a daily basis, you might hear a common question “Are we having fun yet?” asked.  The debug of UVM can be particularly difficult.  We will have a session to show you how to navigate complex UVM environments to quickly find your way around the code – whether its your own or inherited.  You will see how SystemVerilog/UVM dynamic class activity is as easy to debug as it is with RTL signals.  Want to learn how to solve the top 10 common UVM bring-up issues with config_db, the factory, and sequence execution?  Attend and you will learn.

Novices Welcome (and will learn something too!)

While I can’t promise that if you come as a novice you will leave as an expert, you can learn about UVM in the morning as one of the sessions is a technology overview to ensure you won’t be lost when the experts speak.  If you know very little about UVM, the UVM Forum will help you.  There will be a couple presentations from UVM users.  One session is on how UVM enabled advanced storage IP silicon success (presented by Micron) and another session on UVM and emulation to ease the path to advanced verification and analysis (presented by Qualcomm).

Still want to know more before you attend?  You can also boost your UVM knowledge by attending an online UVM Basics course at Verification Academy.  Visit here to learn more about the UVM Basics course.  The Basic UVM course consists of 8 sessions with over an hour of instructional content. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The goal of the course is to raise the level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption – and makes the UVM Forum 2015 more meaningful for you.

I look forward to seeing you there.

, , , , , , , , , ,

25 August, 2015

I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines calls “the largest verification market in the world”. So when I first accompanied the affable Dennis Brophy to the IEEE India office back in April of 2014 to discuss the possibility of having a DVCon in India, I knew I was at the right place at the right time and it was opportunity to contribute to this community.

I has been two years since that meeting, I don’t have to write about how big a success the first ever DVCon India in 2014 was. I’m glad I played a small part by being on the Technical Program Committee on the DV track, reviewing various abstracts. It is a responsibility which I thoroughly enjoyed. This year in addition to being on the TPC, I am contributing as the Chair for Tutorials and Posters. I am eagerly looking forward to the second edition of the Verification Extravaganza which is on 10th and 11th Sept 2015 and the amazing agenda we have planned for attendees.

Day 1 of the conference is dedicated to keynotes, panel discussions and tutorials while day 2 is dedicated fully to Papers with a DV track and a panel in addition to papers in a ESL track. Participants are free to attend any track and can move between tracks. This year we had many sponsored tutorials submissions hence, there will be three parallel tutorial tracks, one on the DV side and two on the ESL track.

Below please find a list of those that Mentor Graphics will be presenting at:

  • Keynote from Harry Foster discussing the growing complexity across the entire design ecosystem
    Thursday, September 10, 2015
    9:45am – 10:30am
    Grand Ball Room, The Leela Palace
    More Information >
    Register for this event >
  • Creating SystemVerilog UVM Testbenches for Simulation and Emulation Platform Portability to Boost Block-to-System Verification Productivity
    Thursday, September 10, 2015
    1:30pm – 3:00pm
    DV Track, Diya, The Leela Palace
    More Information >
    Register for this event >
  • Expediting the code coverage closure using Static Formal Techniques – A proven approach at block and SoC Levels!
    Thursday, September 10, 2015
    1:30pm – 3:00pm
    DV Track, Grand Ball Room, The Leela Palace
    More Information >
    Register for this event >

The papers on day 2 are primarily split into 3 parallel tracks, one on DV track and 2 parallel tracks on ESL. Within the DV track, one area is dedicated to UVM/SV. The other categories within the DV track will cover Portable Stimulus & Graph Based Stimulus, AMS, SoC & Stimulus Generation, Emulation, Acceleration and Prototyping & a generic selected category. The surprise among the categories is Portable Stimulus, which was a tutorial in last year however has continued to be of high interest and sessions will build on last year’s initial tutorial.

Overall there is an exciting mix of keynotes, tutorials, panels, papers and posters, which will make two exceptional days of learning, networking and fun. I look forward to seeing at DVCon India, 2015 and if you see me at the show, please come say hello and let me know what you think of the conference.

, , , , , , , ,

12 August, 2015

Content delivery through the Internet gateway is ever changing and evolving. Today’s mechanism for delivery is more efficient, less power consuming, and better performing than previous generations. Competition is fierce for companies who want to support this gateway. It’s a crowded field and the chips driving high-capacity networks are large and massively complex.  In fact, these network switches and routers routinely have more than 500,000 gates. Project teams aim for a large number of ports, expanded throughput, while decreasing latency and beefing up security and ease of use.

Verifying the design of these chips requires a broad set of verification solutions, including hardware emulation. One verification team recently used hardware emulation in an in-circuit-emulation (ICE) mode to test a SoC design with a 128-port Ethernet interface, and a variable bandwidth of 1/10/40/100/120Gbps. This team elected to use hardware emulation because it could test a design with real traffic with one Ethernet tester per port. A speed rate adapter was inserted between the fast tester and the slow emulated design under test (DUT) since a direct connection is not possible due to rather different speed domains. The setup had 128 Ethernet testers, 128 Ethernet speed adapters and heaps of cables. Sadly, the entire setup could only support a single user who used the setup in an emulation lab.

Another verification team took an entirely different approach using the Mentor Ethernet VirtuaLAB, where Ethernet testers are modeled in software running under Linux on a workstation connected to the emulator. The model, an accurate representation of the actual physical tester, is based on intellectual property (IP) blocks that have already been implemented.

The virtual tester includes an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets within the DUT and can configure GMII, XGMII, XLGMII/CGMII and CXGMII interfaces for 1G, 10G, 40G/100G and 120G. VirtuaLAB software conducts off-line analysis of the traffic, provides statistics, and supports a variety of other functions.

An interface between the VirtuaLAB virtual tester and the DUT has one instance of VirtuaLAB-DPI communicating to a Virtual Ethernet xRTL (extended Register Transfer Level) transactor connected to a Null-PHY linked to the DUT. One xRTL transactor is required for each port of any xMII supported type.

Multiple VirtuaLAB applications can be bundled together across multiple workstations–– known as a multi co-model –– to support large port-count configurations. High Speed Link (HSL) cards are used to connect co-model channels from workstations to the emulator. This tightly integrated transport mechanism is tuned for maximum wall clock performance and transparent to the testbench. Data plane emulation throughput scales linearly with the port count because of this parallel runtime and debug architecture.

Reconfiguring the virtual tester to perform various functions is done through remote access to a workstation, a stable and reliable piece of equipment less costly than a complex Ethernet tester with equivalent functionality. It has the ability to concurrently support multiple users. VirtuaLAB can be used as an enterprise-wide resource in a datacenter, using Enterprise Server’s IT management capabilities.

If you want to know more, download the Accelerating Networking Products to Market Using Ethernet VirtuaLAB whitepaper

, , ,

10 August, 2015

ASIC/IC Power Trends

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I presented our study findings on various verification language and library adoption trends. In this blog, I focus on power trends.

Today, we see that about 73 percent of design projects actively manage power with a wide variety of techniques, ranging from simple clock-gating, to complex hypervisor/OS-controlled power management schemes. What is interesting from our 2014 study is that the data indicates that there has been a 19% increase in the last two years in the designs that actively manage power (see Figure 1).


Figure 1. ASIC/IC projects working on designs that actively manage power

Figure 2 shows the various aspects of power-management that design projects must verify (for those 73 percent of design projects that actively manage power). The data from our study suggest that many projects are moving to more complex power-management schemes that involve software control. This adds a new layer of complexity to a project’s verification challenge, since these more complex power management schedules often require emulation to fully verify.


Figure 2. Aspects of power-managed design that are verified

Since the power intent cannot be directly described in an RTL model, alternative supporting notations have recently emerged to capture the power intent. In the 2014 study, we wanted to get a sense of where the industry stands in adopting these various notations. For projects that actively manage power, Figure 3 shows the various standards used to describe power intent that have been adopted. Some projects are actively using multiple standards (such as different versions of UPF or a combination of CPF and UPF). That’s why the adoption results do not sum to 100 percent.


Figure 3. Notation used to describe power intent

In an earlier blog in this series, I provided data that suggest a significant amount of effort is being applied to ASIC/IC functional verification. An important question the various studies have tried to answer is whether this increasing effort is paying off. In my next blog (click here), I present verification results findings in terms of schedules, number of required spins, and classification of functional bugs.

Quick links to the 2014 Wilson Research Group Study results

, , , , , ,

29 July, 2015

VA DAC2015 smlIf you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed an opportunity to get a printed copy of the DAC 2015 issue of Verification Horizons, don’t worry.  You can also download it as well.

Questa Vanguard Partners Highlighted

Eight of the eleven articles were authored or co-authored by our partners and represent a wide range of topics.  There are two articles on DO-254 (Partners: eInfochips and Verisense).  There is an article on Formal and ABV of MBIST MCPs (Parnter: FishTail Design Automation).  There is an article on how to start formal analysis “right” (Partner: OSKI).  For UVM users, reuse of MATLAB® functions and Simulink® functions is covered (Partner: Mathworks).  Continuing with another article for the UVM users, intelligent testbench automation with UVM and Questa® is explored (Partner: Codasip Ltd.).  For the Agile community, unit testing your way to a reliable testbench is explored (Partner: XtremeEDA & User company: NVIDIA).  Lastly, a noted emulation consultant (Lauro Rizzatti) shares part 2 of his three decades of emulation evolution and a customer paper (Marvell) covers techniques to accelerate RTL simulation.

VH DAC 2015 CoverAll of this is inside the 60-page mega-issue of Verification Horizons in 11 articles.  Direct links to each of the articles is shared below along with the article titles and authors.  The editor introduction by Tom Fitzpatrick gives even more detail and background on this issue.  If you don’t already have some summer or vacation reading, get your electronic copy today!

, , , , , , , , , , , , , , , ,

19 July, 2015

ASIC/IC Verification Technology Adoption Trends

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I focused on the growing ASIC/IC design project resource trends due to rising design complexity. In this blog I examine various verification technology adoption trends.

Dynamic Verification Techniques

Figure 1 shows the ASIC/IC adoption trends for various simulation-based techniques from 2007 through 2014, which include code coverage, assertions, functional coverage, and constrained-random simulation.


Figure 1. ASIC/IC Dynamic Verification Technology Adoption Trends

One observation from these adoption trends is that the electronic design industry is maturing its verification processes. This maturity is likely due to the growing complexity of designs as discussed in the previous section. Another observation is that constrained-random simulation adoption appears to be leveling off. This trend is likely due to the scaling limitations of constrained-random simulation. This technique generally works well at the IP block or subsystem level in simulation, but does not scale to the entire SoC integration level.

ASIC/IC Static Verification Techniques

Figure 2 shows the ASIC/IC adoption trends for formal property checking (e.g., model checking), as well as automatic formal applications (e.g., SoC integration connectivity checking, deadlock detection, X semantic safety checks, coverage reachability analysis, and many other properties that can be automatically extracted and then formally proven). Formal property checking traditionally has been a high-effort process requiring specialized skills and expertise. However, the recent emergence of automatic formal applications provides narrowly focused solutions and does not require specialized skills to adopt. While formal property checking adoption is experiencing incremental growth between 2012 and 2014, the adoption of automatic formal applications increased by 62 percent. In general, formal solutions (i.e., formal property checking combined with automatic formal applications) are one of the fastest growing segments in functional verification.


Figure 2. ASIC/IC Formal Technology Adoption

Emulation and FPGA Prototyping

Historically, the simulation market has depended on processor frequency scaling as one means of continual improvement in simulation performance. However, as processor frequency scaling levels off, simulation-based techniques are unable to keep up with today’s growing complexity. This is particularly true when simulating large designs that include both software and embedded processor core models. Hence, acceleration techniques are now required to extend ASIC/IC verification performance for very large designs. In fact, emulation and FPGA prototyping have become key platforms for SoC integration verification where both hardware and software are integrated into a system for the first time. In addition to SoC verification, emulation and FPGA prototyping are also used today as a platform for software development.

Today, 35 percent of the industry has adopted emulation, while 33 percent of the industry has adopted FPGA prototyping. Figure 3 describes various reasons why projects are using these techniques. You might note that the results do not sum to 100 percent since multiple answers were accepted from each study participant. Also, we are unable to show trend analysis here since previous studies did not examine this aspect of functional verification.


Figure 3. Why Was Emulation or FPGA Prototyping Used?

Figure 4 partitions the data for emulation and FPGA prototyping adoption by the design size as follows: less than 5M gates, 5M to 80M gates, and greater than 80M gates. Notice that the adoption of emulation continues to increase as design sizes increase. However, the adoption of FPGA prototyping rapidly drops off as design sizes increase beyond 80M gates. Actually, the drop-off point is more likely around 40M gates or so since this is the average capacity limit of many of today’s FPGAs. This graph illustrates one of the problems with adopting FPGA prototyping of very large designs. That is, there can be an increased engineering effort required to partition designs across multiple FPGAs. However, better FPGA partitioning solutions are now emerging from EDA to address these challenges. In addition, better FPGA debugging solutions are also emerging from EDA to address today’s lab visibility challenges. Hence, I anticipate seeing an increase in adoption of FPGA prototyping for larger gate counts as time goes forward.


Figure 4. Emulation and FPGA Prototyping Adoption by Design Size

In my next blog (click here) I plan to discuss various ASIC/IC language and library adoption trends.

Quick links to the 2014 Wilson Research Group Study results

, , , , , ,

@dennisbrophy tweets

Follow dennisbrophy

@dave_59 tweets

Follow dave_59

@jhupcey tweets

  • #ARM now hiring formal verification engineers in Austin: exciting tech challenge + Ram is a great guy to work with.…
  • Attention all SF Bay Area formal practitioners: next week Wednesday 7/26 on Mentor's Fremont campus the Verificatio…
  • This is a very hands-on, creative role for a verification expert -- join us!

Follow jhupcey