Posts Tagged ‘dvcon’

13 March, 2017

Just getting around to gathering my thoughts about the great week we had at DVCon U.S. As Program Chair for the conference, I felt a great sense of pride that, with a great deal of help from my colleagues on the conference Steering Committee and especially the great team of experts on the Technical Program Committee, we were able to provide the attendees with a packed program of interesting, informative and entertaining events. But, as always happens, there was one topic that seemed to get the lion’s share of attention. This year, it was Portable Stimulus.

Starting with a standing-room-only crowd (even after bringing in more chairs) of nearly 200 people on Monday morning for the Accellera Day tutorial presented by the members of the Portable Stimulus Working Group (including yours truly), Portable Stimulus never seemed to be far from any of the discussions.

Full house at the DVCon U.S. 2017 Portable Stimulus Tutorial

Full house at the DVCon U.S. 2017 Portable Stimulus Tutorial

If you weren’t able to attend the conference, Accellera will be presenting the tutorial as a series of webinars in early April, so you’ll be able to see what got everyone so excited. In addition to the tutorial, there was a “Users Talk Back” panel session on Wednesday morning that gave several user companies a chance to voice their opinions about the upcoming Portable Stimulus standard. Having been so involved in the standardization effort, I was gratified to hear the generally positive feedback by these industry leaders.

We were pleased also to have two great Portable Stimulus articles in our most recent issue of Verification Horizons. The first article  is from our friends at CVC showing how they used Questa inFact to create a portable graph-based stimulus model that they used in their UVM environment to verify a memory controller design. The second is from my colleague Matthew Ballance, who is also a key technical contributor to the PSWG efforts, and discusses Automating Tests with Portable Stimulus from IP to SoC Level. In this article, you’ll learn about some of the concepts and language constructs of the proposed standard to see how the declarative nature of the standard makes it easier to specify complex scenarios for block-level verification and to combine those into SoC-level scenarios that are often difficult to express with UVM sequences.

The other exciting news I wanted to share with you is our new Portable Stimulus Basics video course on Verification Academy. We can’t yet share all the details of the upcoming standard, since things are still being finalized in the Working Group, but as things are made public, we’ll be sharing what we can so you’ll be the first to learn about this exciting new standard. As we add new sessions to the course, we’ll be sure to let you know. Please go check it out.

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24 February, 2017

My last blog post was written a few years ago before attending a conference when I was reminiscing about the 10-year history of SystemVerilog. Now I’m writing about going to another conference, DVCon, and being part of a panel reminiscing about the 15-year history of SystemVerilog and envisioning its future. My history with SystemVerilog goes back much further.

Soul of a New MachineMy first job out of college was working with a group of Data General (DG) engineers made public in the book, Soul of a New Machine, by Tracy Kidder in 1981. Part of my job was writing a program that simulated the microcode of the CPUs we designed. Back then, there were no hardware description languages and you had to hard code everything for each CPU. If you were lucky you could reuse some of the code for the user interface between projects. Later, DG came up with a somewhat more general-purpose simulation language. It was general-purpose in the sense that it could be used for a wider range of projects based on the way DG developed hardware. But getting it to work in another company’s environment would have been a challenge.  By the way, Badru Agarwala was the DG simulation developer I worked with who later founded the Verilog simulation companies Frontline and Axiom. He now manages the Calypto division at Mentor Graphics.

Many other processor companies like DEC, IBM and Intel had their own in-house simulation languages or were in the process of developing one because no commercially viable technologies existed. Eventually, Phil Moorby at Gateway Design began developing the Verilog language and simulator. One of the benefits of having an independent language, although not an official standard yet, was you could now share or bring in models from outside your company. This includes being able to hand off a Verilog netlist to another company for manufacturing. Another benefit was that companies could now focus on the design and verification of their products instead of the design and verification of tools that design and verify their products.

I evaluated Verilog in its first year of release back in 1985/1986. DG decided not to adopt Verilog at that point, but I liked it so much I left DG and joined Gateway Design as one of its first application engineers. Dropping another name, Karen Bartleson was one of my first customers as a CAD manager working at UTMC. She recently took the office of President and CEO of the IEEE.

IEEEFast forward to the next decade, when Verilog became standardized as IEEE 1364-1995. But by then it had already lost ground in the verification space. Companies went back to developing their own in-house verification solutions. Sun Microsystems developed Vera and later released it as a commercial product marketed by Systems Science. Arturo Salz was one of its developers and will be on the DVCon panel with me as well. Specman was developed for National Semiconductor and a few other clients and later marketed by Verisity. Once again, we had the problem of competing independent languages and therefore limiting the ability to share or acquire verification models. So, in 1999, a few Gateway alums and others formed a startup which I joined a year later hoping to consolidate design and verification back into one standard language. That language was SUPERLOG and became the starting point for the Accellera SystemVerilog 3.0 standard in 2002, fifteen years ago.

IEEE Std 1800-2012There are many dates you could pick for the start of SystemVerilog. You could claim it couldn’t exist until there was a simulator supporting some of the features in the standard. For me, it started when I first read an early Verilog Language Reference Manual and executed my first initial block 31 years ago. I’ve been using Verilog almost every day since. And now all of Verilog is part of SystemVerilog. I’ve been so much a part of the development of the language from its early beginnings; that’s why some of my colleagues call me “The Walking LRM”. Luckily, I don’t dream about it. I hope I never get called “The Sleeping LRM”.

So, what’s next for SystemVerilog? Are we going to repeat the cycle of fragmentation and re-consolidation? Various extensions have already begun showing up in different implementations. SystemVerilog has become so complex that no one can keep a good portion of it in their head anymore. It is very difficult to remove anything once it is in the LRM. Should we start over? We tried to do that with SUPERLOG, but no one adopted it until it was made fully backward compatible with Verilog.

The Universal Verification Methodology (UVM) was designed to cut down the complexity of learning and using SystemVerilog. There are now a growing number of sub-methodologies for using the UVM because the UVM itself has exploded in complexity  (UVM Framework and Easier UVM to name a couple). I have also taken my own approach when teaching people SystemVerilog by showing a minimal subset (See my SystemVerilog OOP for UVM Verification course).

DVConI do believe in the KISS principle of Engineering and I hope that is what prevails in the next version of SystemVerilog, whether we start over or just make refinements. I hope you will be able to join the discussion with others and me at the DVCon panel next week, or in the forums in the Verification Academy, or on Twitter.


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15 December, 2016

Technical Program is Live

For the past several months, the DVCon U.S. Steering Committee has been meeting to craft a compelling event of technical papers, panels, keynotes, poster sessions and more for you.  With the hard work of authors who supply this content and the Technical Program Committee that reviews and selects from this content, a 4-day event schedule is now published.  You can find the event schedule here.

I am pleased to chair DVCon U.S. 2017 and work with such an august body of people – from the electronic design automation industry, design and verification practitioners and professionals from large systems houses to small consultancies – all who work hard for you to make this happen.  As has been the tradition of DVCon U.S. the past several years, the event starts with Accellera Day on Monday (Feb 27th) followed by two days of paper presentations, keynotes, panels and an exhibition.  The exhibition starts Monday, Accellera Day.  The last day of DVCon U.S. features a full day of tutorials split in to half-day parts.

Accellera Day

DVCon U.S. will feature something for advanced users and those who may be more novice.  The conference will showcase emerging standards and updates to those standards well used.  On Monday, Accellera Day, DVCon U.S. begins with a tutorial devoted to work underway within Accellera on a new standard, “Portable Stimulus,” that is set to give design and verification engineers a boost in overall design and verification productivity.  Given the work by the Accellera Portable Stimulus Working Group to put as much of the standard in place that it can, this tutorial, Creating Portable Stimulus Models with the Upcoming Accellera Standard, is sure to be an important educational opportunity.  If you are a user of UVM (Universal Verification Methodology) you will find the Portable Stimulus standard is set to remove many of the limitations of reuse at the subsystem and full-chip level and address the lack of portability across execution platforms.  Are you ready for Portable Stimulus?  You will be ready after attending this tutorial.

As the Monday luncheon evolves, I anticipate a moderated panel discussion hosted by Accellera on the emerging Portable Stimulus standard based on what you learned in the morning session.  As lunch ends, two parallel tutorials will start, one on IEEE P1800.2™ (aka UVM) and the other on System C design and verification advances.  Accellera Day is a great event to learn about the latest in the evolution of standards coming from Accellera and the IEEE.

Special Session

DVCon U.S. will make one departure from prior years’ programs and offer a special session on Tuesday on Trends in Functional Verification: A 2016 Industry Study presented by Harry Foster.  Harry has been reporting on the 2016 Wilson Research Group Study here at the Verification Horizon’s BLOG, and he has shared regional information at DVCon Europe and DVCon India on adoption and use of design and verification tools, technology and standards.  At DVCon U.S. he will pull all this together to show trends and offer predictions for the future.

There is much more to DVCon U.S. 2017 that I think you will find useful.  I leave it to you to explore the program more to discover this for yourself.  And if you can make it to DVCon U.S., registration is also open with advanced rates available until January 26th.  I hope to see you there!

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29 March, 2016

If you were wondering whether formal verification is becoming a cornerstone of mainstream verification flows, several events at the recent DVCon USA 2016 should leave you without any doubt.  Consider the evidence:

* The consensus of the panel on “Emulation + Static Verification Will Replace Simulation”

First, out of all the possible topics for a panel on “futures”, this one was chosen (vs. a panel on something really futuristic, like “Is Quantum Computing Ready for EDA?”), suggesting that formal is collectively at the top of people’s minds when they step back and assess the effectiveness of their verification flows today.

2016-3 DVCon 2016 USA

Of course, the panel’s animating question was chosen to be deliberately provocative – harkening back to the first wave of formal, with its claims of formal being able to eliminate the need for simulation. However, the panelists – who were heavily weighted toward formal expertise – didn’t renew or update this boast. Instead, they spoke of how formal can be incredibly effective in solving quite a few types of verification challenges, and flatly awful at others. Same goes for simulation and emulation. The consensus that emerged can be paraphrased as, “use the right tool for the job” and “because there are so many different jobs to be done, every verification environment should use formal, simulation, and emulation to some degree”.  The larger point here is that in the eyes of these verification experts, formal apps and classical property checking have clearly matured into being an essential component of a complete verification tool kit.

2016-3 DVCon 2016 USA

* The formal-specific elements of the EDA CEO keynote

Mentor’s CEO Wally Rhines gave a very expansive keynote – part history lesson, part “state of the art today” snapshot, and part future outlook (Article; Wally’s slides).  In synchronicity with the aforementioned panel discussion (that followed right after his speech, so he couldn’t likely have known the independent panel’s consensus beforehand), woven into his remarks were multiple examples of how formal is (A) the exact right tool for the job for several critical verification tasks (e.g. CDC, SoC Connectivity verification, code coverage unreachability & closure, X-corruption, secure path verification, etc.), and (B) is an integral part of a complete verification flow comprised of virtual prototyping, formal, simulation, emulation, and FPGA prototyping.

2016-3 DVCon 2016 USA

* The Thursday afternoon tutorial on pure formal basic training was a full house

I don’t mean to brag [ok, I do, just a little], but the tutorial I produced on “Back to Basics: Doing Formal the Right Way” on the last day in the last time slot of the conference – i.e. a historically challenging time slot to draw a sizable audience – was a full house! Apparently, our intuition was correct: there IS a new generation of D&V engineers who are very interested learning classical formal property checking (whether they were inspired by the success with an automated formal app, or sensed the technology is truly ready for prime time). Granted, there were quite a few familiar faces from prior events who no doubt knew of my colleagues Doug Smith and Mark Eslinger’s abilities to distill complex topics into concise, actionable examples. But speaking as a veteran DVCon tutorial producer and presenter, I would have been happy with a gentleman’s 40-45 attendees. Thus we were positively stunned when we filled the room with 70+ people, and held them throughout the length of the program.

Do you agree — are we in a new wave of formal?  Please share your thoughts in the comments below, or contact me offline.

Joe Hupcey III


21 March, 2016

As I’m sure I’ve mentioned before, DVCon (in the US – I haven’t made it to any of the new, international events yet) is one of my favorite weeks of the year. In addition to seeing friends and colleagues, I really enjoy seeing how the industry has progressed from year to year. As one of the early (and still enthusiastic) proponents of UVM, I was especially interested to see all the UVM-related activity at this year’s conference.

The UVM emphasis started first thing Monday morning with the tutorial “Preparing for IEEE UVM Plus: UVM Tips and Tricks,” which by my unofficial tally was the most well-attended tutorial on Monday. Judging by the audience’s attentiveness, it was apparent that they found the “Tips and Tricks” discussion, which was divided into compile-time and run-time categories, to be very helpful, although many of them are already included in the online UVM Cookbook on Verification Academy. In addition, there were three separate “UVM Applications” sessions, each of which was the most popular session in its timeslot, and 9 posters on UVM.

One poster in particular caught my eye, “Slaying the UVM Reuse Dragon: Issues and Strategies for Achieving UVM Reuse,” (viewable here) by my Mentor Graphics colleague Bob Oden and Mike Baird of Willamette HDL. Bob is the creator of our new UVM Framework reuse environment (more about that in a future post) and, besides being one of the leading UVM and SystemVerilog trainers out there, Mike holds the distinction of being the guy who taught me Verilog way back in the dark ages. These guys really know their stuff, and the paper lays out a straightforward approach to organizing, grouping, and packaging the different parts of your UVM component library to maximize their reuse from project to project. It also shows you how to architect your components and environments to make them self-contained and configurable so you’ll be able to use them in whatever context you need to.

Given the remarkable and still-growing popularity of UVM, I’m going to take some time over the next few weeks and months to highlight some of the key points of effective UVM usage here on Verification Horizons. As you know, there’s a wealth of UVM-related information on Verification Academy, but I think it might help to point out some of the more important features. Stay tuned!

By the way, you can see all of the papers and posters written by Mentor Graphics authors here. Enjoy!

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24 February, 2016


It’s that time of the year again – time for verification engineers and vendors alike to show off the state of the art in design verification at DVCon 2016. Last year at DVCon, Accellera’s Portable Stimulus Proposed Working Group (PSPWG) was transformed into a full-fledged Working Group (PSWG) with the charter to accept contributions and define a stimulus specification standard that enables the definition of stimulus that is portable from block to system level verification, and portable across the verification engines – simulation, emulation, and FPGA prototype.


It’s been a busy year in the Portable Stimulus Working Group. We’ve spent time discussing, understanding, and clarifying usage examples contributed by user companies, whose purpose it is to help illustrate how a portable stimulus specification addresses industry verification challenges. We’ve spent time reviewing and understanding language contributions from vendors and users. With all of this activity and focus around a specification that still (at least in its entirety) lives on paper, I’m sure it would easy for an observer to lose sight of the fact that there are Portable Stimulus tools already in the market that are providing great results to production users. DVCon is a great reminder that, while the Portable Stimulus Specification standard is in process, Portable Stimulus is here now!

To learn more about how users are applying Portable Stimulus, attend the SystemVerilog Programming and Techniques session on Tuesday afternoon. Microsoft will be presenting a paper about techniques using the Questa inFact Graph-Based Portable Stimulus tool for efficient bug hunting.

If you’re curious about how existing descriptions, specifically SystemVerilog, relate to the emerging standard, drop by my poster on Tuesday morning. My paper and poster present guidelines for structuring SystemVerilog to make portions easily reusable in a Portable Stimulus Specification description.

Of course, Portable Stimulus appears in other places at DVCon too! Check out the full program to find other papers and tutorials highlighting how Portable Stimulus is providing value to users today!

If you’d like to learn more about Portable Stimulus, or just discuss verification techniques in general, drop by the Verification Academy booth on the exhibition floor. I’ll be there, as will Mentor’s standards and methodology experts Harry Foster, Tom Fitzpatrick, Dennis Brophy, and others. So, come find us. I’d love to hear your thoughts on Portable Stimulus, and getting to interact with other verification practitioners is truly the best part of DVCon!


8 February, 2016

Join Us at DVCon

As an annual conference, DVCon has set itself apart from others.  With a high focus on the application of design and verification tools and technology the venue is a prime location to exchange best practices and learn about emerging and current standards for the practicing engineer.  DVCon has also gone global to promote locally the sharing of best practices and building a wider global audience.  The flag ship event, DVCon U.S. has grown into an event that brackets two days of paper and poster sessions with tutorials on sessions on emerging standards from Accellera and how-to practical information by producers and users of design automations technology.  Building knowledge, skill and proficiency that can be applied in one’s design and verification engineering profession is unique.  What can you learn?  How can you share?

The answer to those questions has one simple answer: Attend DVCon U.S.  What specifically might apply to your current engineering demands are best found examining the conference program.  DVCon U.S. runs Monday – Thursday (29 February – 3 March 2016).  Monday is “Accellera Day” and features a focus on emerging and popular standards.  Content is geared for both beginners and advanced users.  Tuesday and Wednesday will feature papers, panels, posters and keynotes.  The topics will take you from system level to gates and from design to verification and hardware to software and portable stimulus to low power design.  These two days are organized as more of a traditional technical conference with parallel track, complemented by sponsored lunches and afternoon/evening exhibition for tool and services suppliers to share their latest product offerings.  Wednesday concludes with announcing the best paper and poster awards.  But that is not the end of the conference.  Thursday is “Tutorial Day.”  Four parallel half-day tutorials will be presented on a variety of topics.  The Mentor Graphics team has sponsored two of the tutorials, one in the morning and one in the afternoon:

  • Tutorial 5: Advanced Validation and Functional Verification Techniques for Complex Low Power System-on-Chips
  • Tutorial 9: Back to Basics: Doing Formal the Right Way

Low Power Tutorial: New IEEE 1801 Standard

In this blog, I would like to focus in on Tutorial 5 as it relates to one of the most daunting challenges today: low power design of SoC’s.  And, this tutorial will explore how new constructs in IEEE Std. 1801™-2015 (UPF 3.0) can facilitate power modeling at high levels of abstraction and improve application of Successive Refinement methodology.  At the publication of this blog, the IEEE has not yet published this new standard.  It was approved at the IEEE Standards Association meeting series in December 2015.  If you were a member of the IEEE ballot group or a member of the IEEE 1801 Working Group, you have a copy of the last draft of the standard and have access to all the information you might need on the new constructs that were added.  For everyone else, my recommendation is to attend DVCon U.S. and this tutorial to learn more in advance of the publication from the experts who created the standard and the Successive Refinement methodology.

You can find full information about DVCon U.S. here and to join us, register here.  And if your time is really limited and you can’t make the full conference, the Exhibition runs into the evening (Monday – Wednesday) for those who are local and might want to visit after work.  Even better news, the Exhibits-only pass is fee free.  See you there!

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25 August, 2015

I have always been wanting to contribute to the growing verification engineering community in India, which Mentor’s CEO Wally Rhines calls “the largest verification market in the world”. So when I first accompanied the affable Dennis Brophy to the IEEE India office back in April of 2014 to discuss the possibility of having a DVCon in India, I knew I was at the right place at the right time and it was opportunity to contribute to this community.

I has been two years since that meeting, I don’t have to write about how big a success the first ever DVCon India in 2014 was. I’m glad I played a small part by being on the Technical Program Committee on the DV track, reviewing various abstracts. It is a responsibility which I thoroughly enjoyed. This year in addition to being on the TPC, I am contributing as the Chair for Tutorials and Posters. I am eagerly looking forward to the second edition of the Verification Extravaganza which is on 10th and 11th Sept 2015 and the amazing agenda we have planned for attendees.

Day 1 of the conference is dedicated to keynotes, panel discussions and tutorials while day 2 is dedicated fully to Papers with a DV track and a panel in addition to papers in a ESL track. Participants are free to attend any track and can move between tracks. This year we had many sponsored tutorials submissions hence, there will be three parallel tutorial tracks, one on the DV side and two on the ESL track.

Below please find a list of those that Mentor Graphics will be presenting at:

  • Keynote from Harry Foster discussing the growing complexity across the entire design ecosystem
    Thursday, September 10, 2015
    9:45am – 10:30am
    Grand Ball Room, The Leela Palace
    More Information >
    Register for this event >
  • Creating SystemVerilog UVM Testbenches for Simulation and Emulation Platform Portability to Boost Block-to-System Verification Productivity
    Thursday, September 10, 2015
    1:30pm – 3:00pm
    DV Track, Diya, The Leela Palace
    More Information >
    Register for this event >
  • Expediting the code coverage closure using Static Formal Techniques – A proven approach at block and SoC Levels!
    Thursday, September 10, 2015
    1:30pm – 3:00pm
    DV Track, Grand Ball Room, The Leela Palace
    More Information >
    Register for this event >

The papers on day 2 are primarily split into 3 parallel tracks, one on DV track and 2 parallel tracks on ESL. Within the DV track, one area is dedicated to UVM/SV. The other categories within the DV track will cover Portable Stimulus & Graph Based Stimulus, AMS, SoC & Stimulus Generation, Emulation, Acceleration and Prototyping & a generic selected category. The surprise among the categories is Portable Stimulus, which was a tutorial in last year however has continued to be of high interest and sessions will build on last year’s initial tutorial.

Overall there is an exciting mix of keynotes, tutorials, panels, papers and posters, which will make two exceptional days of learning, networking and fun. I look forward to seeing at DVCon India, 2015 and if you see me at the show, please come say hello and let me know what you think of the conference.

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17 March, 2015


With a name like “Fitzpatrick,” you knew I’d be celebrating today, right?

Well, there’s no better way to celebrate this fine day than to announce that our latest edition of Verification Horizons is available online! Now that Spring is almost here, there’s a bit less snow on the ground than there was when I wrote my introduction, but everything is still covered. I’m considering spray-painting it all green in honor of the occasion, so at least it looks like I have a lawn again.

In this issue of Verification Horizons, I’d particularly like to draw your attention to “Successive Refinement: A Methodology for Incremental Specification of Power Intent,” by my friend and colleague Erich Marschner and several of our friends at ARM® Ltd. In this article, you’ll find out how the Unified Power Format (UPF) specification can be used to specify and verify your power architecture abstractly, and then add implementation information later in the process. This methodology is still relatively new in the industry, so if you’re thinking about making your next design PowerAware, you’ll want to read this article to be up on the very latest approach.

In addition to that, we’ve also got Harry Foster discussing some of the results from his latest industry study in “Does Design Size Influence First Silicon Success?” Harry is also blogging about his survey results on Verification Horizons here and here (with more to come).

Our friends at L&T Technology Services Ltd. share some of their experience in doing PowerAware design in “PowerAware RTL Verification of USB 3.0 IPs,” in which you’ll see how UPF can let you explore two different power management architectures for the same RTL.

Next, History class is in session, with Dr. Lauro Rizzatti, long-time EDA guru, giving us part 1 of a 3-part lesson in “Hardware Emulation: Three Decades of Evolution.”

Our friends at Oracle® are up next with “Evolving the Use of Formal Model Checking in SoC Design Verification,” in which they share a case study of their use of formal methods as the central piece in verifying an SoC design they recently completed with first-pass silicon success. By the way, I’d also like to take this opportunity to congratulate the author of this article, Ram Narayan, for his Best Paper award at DVCon(US) 2015. Well done, Ram!

We round out the issue with our famous “Partners’ Corner” section, which includes two articles. In “Small, Maintainable Tests,” our friends at Sondrel IC Design Services show you a few tricks on how to make use of UVM virtual sequences to raise the level of abstraction of your tests. In “Functional Coverage Development Tips: Do’s and Don’ts,” our friends at eInfochips give you a great overview of functional coverage, especially the covergroup and related features in SystemVerilog.

I’d also like to take a moment to thank all of you who came by our Verification Academy booth at DVCon to say hi. I found it incredibly humbling and gratifying to hear from so many of you who have learned new verification skills from the Verification Academy. That’s a big part of why we do what we do, and I appreciate you letting us know about it.

Now, it’s time to celebrate St. Patrick’s Day for real!

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23 February, 2015

It’s my favorite time of year again—DVCon!  And I believe that the DVCon 2015 technical program committee has put together one of the technically best DVCon’s in years. In this blog I plan on highlighting a few DVCon events that you might want to put on your calendar.


First, at this year’s conference the Verification Academy has a dedicated booth (#301), and I hope you stop by to say hello to myself, my friend Tom Fitzpatrick, and an amazing lineup of other Verification Academy subject matter experts.

Next, on Wednesday morning March 4 I have the honor of participating on a verification panel, titled: “Art of Science.” Here, my fellow panelist and I will debate the issue that verification today is considered by some to be more of an art than a science—and one which is perceived as difficult to master. To learn my position on this topic, you’ll have to stop by!

Also on Wednesday at the Mentor sponsored lunch, my colleague Steve Bailey and I have put together both an informative and entertaining talk we’ve title: “From Tightly Coupled (Loosely Bolted) to Verification Convergence.” Here, we discuss the state of verification past, present and future while examining the results from our recently industry world-wide study, which I started blogging about a few weeks ago (click here for more details). Our talk will examine how advanced techniques are taking hold in mainstream design and provide insights on the recent convergence of verification solutions to meet today’s growing challenges.

Finally, there are two tutorials I’d like to encourage you to attend while at DVCon this year:

  1. Advanced, High-Throughput Debug from Architectural Modeling Through Post-Silicon SoC Validation (click here for more details)
  2. Dead or Alive: Using Automated Formal Techniques to Characterize Dead Code, Reveal Paths to Hit Uncovered States, and Reach Coverage Closure Faster (click here for more details)

I look forward to meeting you at DVCon 2015!

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