Posts Tagged ‘dac’

1 June, 2017

Accellera’s Emerging Portable Stimulus Standard Is Pervasive at DAC 54

For the past few years, Accellera’s Portable Stimulus Working Group has been busy at work on the new standard to elevate stimulus generation to improve overall verification productivity.  As the call to attend the annual Accellera breakfast DAC 54 informs us, the Accellera Portable Stimulus early adopter release is planned to be made available prior to DAC.  I’m certain that a download of the early adopter release will make for good reading for those traveling to DAC and have not participated in the development of the standard.  I predict it will be a “page-turner.”  You will be in a much better position to attend the following events in and around DAC (some of which require DAC registration fee payment and some that are fee-free) if you download and read it when ready.  Here are some of the DAC 54 Portable Stimulus activities:

Monday June 19th

Tuesday June 20th

Wednesday June 21st

And for those who will not be attending DAC, I will update this blog with information on how you can download the Accellera Portable Stimulus early adopter release.  There is also online educational videos about the emerging Portable Stimulus standard.  You can find a two sessions at the Mentor Verification Academy on Portable Stimulus Basics. And the DVCon U.S. 2017 technical tutorial, Creating Portable Stimulus Models with the Upcoming Accellera Standard, presented in three parts is located at the Accellera website.  Both online educational video offerings require registration.

, , , ,

24 May, 2016

Join us at the 53rd Design Automation Conference

DAC is always a time of jam-packed activity with multiple events that merit your time and attention.  As you prepare your own personal calendars and try your best to reduce or eliminate conflicts, let me share with you some candidate events that you may wish to consider having on your calendar.  I will highlight opportunities to learn more about ongoing and emerging standards from Accellera and IEEE.  I will focus on a few sessions at the Verification Academy booth (#627) that feature Partner presentations.  And I will spotlight some venues where other industry collaboration will be detailed.  You will also find me at many of these events as well.

Standards

Accellera will host its traditional Tuesday morning breakfast.  Registration is required – or you might not find a seat.  As always, breakfast is free.  The morning will feature a “Town Hall” style meeting that will cover UVM (also known as IEEE P1800.2) and other technical challenges that could help evolve UVM into other areas.   Find out more and learn about all things UVM, register here.

Partners

The Verification Academy is “partner-central” for us this year.  Each day will feature partner presentations that highlight evolving design and verification methodologies, standards support and evolution, and product integrations.  Verification Academy is booth #627, which is centrally located and easy to find.  Partner presentations include:

  • Back to the Stone Ages for Advanced Verification
    Monday June 6th
    2:00 PM | Neil Johnson – XtremeEDA

    Modern development approaches are leaving quality gaps that advanced verification techniques fail to address… and the gaps are growing in spite of new innovation. It’s time for a fun, frank and highly interactive discussion around the shortcomings of today’s advanced verification methods.

  • SystemVerilog Assertions – Bind files & Best Known Practices
    Monday June 6th
    3:00 PM | Cliff Cummings – Sunburst Design

    SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. 13 years of professional SVA usage strongly suggests that Best Known Practices use bindfiles to add assertions to RTL code.

  • Specification to Realization flow using ISequenceSpec™ and Questa® InFact
    Tuesday June 7th
    10:00 AM | Anupam Bakshi – Agnisys, Inc.

    Using an Ethernet Controller design, we show how complete verification can be done in an automated manner, saving time while improving quality. Integration of two tools will be shown. InFact creates tests for a variety of scenarios which is more efficient and exhaustive than a pure constrained random methodology. ISequenceSpec forms a layer of abstraction around the IP/SoC from a specification.

  • Safety Critical Verification
    Wednesday June 8th
    10:00 AM | Mike Bartley – TVS

    The traditional environments for safety-related hardware and software such as avionics, rail and nuclear have been joined by others (such as automotive and medical devices) as systems become increasingly complex and ever more reliant on embedded software. In tandem, further industry-specific safety standards (including ISO 26262 for automotive applications and IEC 62304 for medical device software) have been introduced to ensure that hardware and software in these application areas has been developed and tested to achieve a defined level of integrity. In this presentation, we will be explaining some of these changes and how they can be implemented.

  • Using a Chessboard Challenge to Discover Real-world Formal Techniques
    Wednesday June 8th
    3:00 PM | Vigyan Singhal & Prashant Aggarwal – Oski Technology

    In December 2015, Oski challenged formal users to solve a chessboard problem. This was an opportunity to show how nifty formal techniques might be used to solve a fun puzzle. Design verification engineers from a variety of semiconductor companies and research labs participated in the contest. The techniques submitted by participants presented a number of worthy solutions, with varying degrees of success.

Industry Collaboration

Debug Data API: “Cadence and Mentor Demonstrate Collaboration for open Debug Data API in Action”  It was just a year ago that the project to create an open debug data API was announced at DAC 52.  Since there several possible implementation styles were reviewed, an agreed specification created and early working prototypes demonstrated.  On Tuesday, June 7th at 2:00pm we will host a session at the Verification Academy (Booth #627).  You are encouraged to register for the free session – but walkups are always welcome!  You can find more information here.

Portable Stimulus Tutorial: “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges”  As part of the official DAC program, there will be a tutorial on the emerging standardization work in Accellera.  The tutorial is Monday, June 6th from 1:30pm – 3:00pm in the Austin Convention Center, Room 15.  You can register here for the tutorial.  There is a fee for this event.  Want to know more about the tutorial?  You can find more information here.

Fun

It is always good to end the day on a light note.  To that end, on Monday June 6th, will invite you to “grab a cold one” at the Verification Academy booth and continue discussions and networking with your colleagues.  If past year’s experience is any guide to this year, you may want to get here early for your drink!  There is no registration to guarantee a drink, unfortunately!  So, come early; stay late!  See you in Austin!

And if you miss me at any of the locations above, tweet me @dennisbrophy – your message is sure to reach me right away.

, , , , , , , , , , , , , , , , ,

21 October, 2015

Join us to review the first public review of the Debug Data API specification!

At DAC 2015 we introduced Verification Academy attendees to a “New Verification Debug API” project at DAC.  Since that time we have held several teleconferences and a face-to-face meeting as we have extended and refined what was presented at DAC to match use cases for portable debug data based on user feedback.  The public group that is participating in this feedback and refinement is now reviewing the first version of the specification.  While we invite everyone to download a copy and review it, you must be a member of the group to download it and post questions and comments.  Everyone is welcome to join and there is not fee to participate, or just observe.

NewImageThe Debug Data API is a modernized way to share waveform information than VCD.  If VCD still works for you, don’t worry, we are not doing anything to change that flow.  But we are looking to extend and augment a traditional live simulation vpi-scheme with one that works for post simulation run datasets as well.  The specification is now being juxtaposed against use models to ensure that post-simulation waveform information can be used in a way you want to use it and in a more efficient way than you have available today.  The plan is to avoid the pitfalls for multi-step translation processes and allow you to author a verification function or set of functions once and perform that function on any dataset from all producers.

We invite you to join with us in building this.  Once you have joined, login and click this link to download the first version of the specification that is now out for review. In addition to being able to download the specification you will also be sent meeting notifications to join in with us if you wish.

, , , , ,

8 June, 2015

Do you have a really tough verification problem – one that takes seemingly forever for a testbench simulation to solve – and are left wondering whether an automated formal application would be better suited for the task?

Are you curious about formal or clock-domain crossing verification, but are overwhelmed by all the results you get from a Google search?

Are you worried that adding in low power circuitry with a UPF file will completely mess up your CDC analysis?

Good news: inspired by the success of the UVM courses on the Verification Academy website, the Questa Formal and CDC team has created all new courses on a whole variety of formal and CDC-related subjects that address these questions and more.  New topics that are covered include:

* What’s a formal app, and what are the benefits of the approach?

* Reviews of automated formal apps for bug hunting, exhaustive connectivity checking and register verification, X-state analysis, and more

* New topics in CDC verification, such as the need for reconvergence analysis, and power-aware CDC verification

* How to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines AND ensure reuse with simulation and emulation, how to setup the analysis for rapidly reaching a solution, and how to measure formal coverage and estimate whether you have enough assertions

The best part: all of this content is available NOW at www.verificationacademy.com, and it’s all FREE!

Enjoy!

Joe Hupcey III,
on behalf of the Questa Formal and CDC team

P.S. If you’re coming to the DAC in San Francisco, be sure to come by the Verification Academy booth (#2408) for live presentations, end-user case studies, and demos on the full range of verification topics – UVM, low power, portable stimulus, formal, CDC, hardware-software co-verification, and more.  Follow this link for all the details & schedule of events (including “Formal & CDC Day” on June 10!): http://www.mentor.com/events/design-automation-conference/schedule

, , , , , , , , ,

4 June, 2015

Learn more about DDA at DAC

At DAC – Mentor Graphics and Cadence Design Systems are coming together to usher in another level of productivity in verification results data access and portability with a modern design debug data application programming interface standard. We call this emerging standard the Debug Data API, or DDA for short.  We want to share more details with you in person at DAC.  Join us on Tuesday, June 9th, at the Verification Academy Booth (#2408) at 5:00pm for a joint presentation and unveiling.  And to get a bit of background and hint of what’s to come, please read on.

History: It Started with VCD

In the beginning we had VCD as the universal standard format to exchange simulation results as part of the IEEE 1364 (Verilog) standard.   Anyone trying to use VCD today on those large SoC’s or complex FPGA’s knows the size of VCD files has all but excluded this portion of the IEEE standard from use in modern design verification practice. So the question is when will it be replaced?

To ask that question today seems fine.  But I was even skeptical in the mid 1990’s when we at Mentor Graphics created Extended VCD to support the IEEE 1076.4 (VITAL) gate level simulation standard.  At that time the largest designs were around 1 million gates. While Extended VCD never became an official IEEE standard, we shared it with our ASIC Vendor and FPGA partners along with our major competitors to ensure debug data access and portability for VITAL users was on par with Verilog.  But Extended VCD also suffers the same fate of being almost impossible to support modern large designs.

Today: VCD Replaced by a Proprietary World

VCD and Extended VCD have remained static for about 20 years. But commercial simulator, emulator and other verification technology suppliers have not stopped innovating to advance support for larger design sizes with larger result data sets. As we move to 2 billion gate designs and beyond, the dependence on these private and closed technological advances and innovations has never been more important.

But that proprietary dependence comes with a cost. We stand at a crossroads where consumers of verification results information lose the open and unencumbered use offered by VCD or they need a path forward that preserves their current benefits while protecting and encouraging producers of such information to continue to innovate by private means.  The only alternative are fully integrated solutions from a single supplier that rarely get consumer endorsement in a best-of-breed; mix-and-match world.

Near Future: Federating the Proprietary World with DDA

Federating proprietary solutions almost sounds like something that is impossible to do. But Mentor and Cadence will share their emerging work on a standard to federate the different sources of verification results that can come from private sources with unencumbered access for the consumer. The Debug Data API standard will offer consumers the benefits of VCD interoperability, data portability and openness while preserving the benefits of private innovation for tool and solution producers. It will not impose data format translations from one format to another as a means to promote data portability.  It will not require the means by which one supplier or another stores verification results to be exposed.  It will offer the best of both worlds to producers and consumers.  I guess in some cases, you can have your cake and eat it too! There are more details to share, and the best place start is to meet us at DAC.

VA DDA Session AbstractMentor and Cadence Share DDA Details at DAC

  • Location: Verification Academy Booth (#2408)
  • Date: Tuesday, June 9th
  • Time: 5:00pm PT
    More Information >

We will discuss the details of DDA and show a proof of concept demonstration that will highlight each company’s simulator and results viewer in action.  Since there is no other session following this one at the Verification Academy booth, we will also be around to discuss the next steps with all present afterwards.

You can read more about this from my colleague and competitor, Cadence’s Adam Sherer, on his blog at the Cadence site here.  He bring his own perspective to this.

See you at DAC!

, , , , , , , , , , , ,

7 May, 2015

For all things verification, you will want to stop by the Verification Academy booth #2408 at DAC to interact with experts exploring the challenges of IC design and verification.  At the top of each hour, the Verification Academy will feature a presentation followed by a lively conversation.  Presentations will not be repeated so each hour will be unique.

We have themed each of the days as well:

  • Monday is “Debug Day
  • Tuesday is “Standards & FPGA Day
  • Wednesday is “Formal Verification Day

Naturally, you will find a few exceptions to those rules when you look at the program in detail.  Please register for Verification Academy sessions here: Monday Registration | Tuesday Registration | Wednesday Registration.  [NOTE: the Verification Academy sessions are highlighted with a blue background when you visit the registration site.]  A concise listing of all the Verification Academy sessions can be found here.

We will feature an end of the day reception on Monday at the Verification Academy booth after the last presentation.  Neil Johnson (XtremeEDA) and Mentor’s Harry Foster will explore Agile Evolution in SoC Verification in that last session.  The session begins at 5pm.  Neil is a proponent of this methodology as a means to to help build in design quality and simplify the task of verification.  In addition to being an advocate for this, he is also a practitioner of it.  He is an open-source hardware developer and Moderator at www.AgileSoC.com.  We think the conversation that follows this informative session will be a lively one in which we invite everyone to continue over cocktails and hor d’oeuvres at 5:30pm.

We are sponsoring other events outside of the Verification Academy as well.  Tuesday is truly “Standards Day” at DAC.  In addition to the standards theme at the Verification Academy booth, you can kick off the day at the Accellera Breakfast and later in the day attend the IEEE DASC, Accellera and Si2 System Level Low Power Workshop.  Here is a partial list of Standards Day activities:

Registration

If you have not yet registered for DAC, do so now.  If you do not have plans to register for the full technical conference, many conference events are fee free if you select the “I LOVE DAC” registration option before May 19th!  In fact, all the “Standards Day” events listed above are free with early I Love DAC registration. Simply click here and you will be taken to the “I Love DAC” location to register.  Register before May 19th as after that date a $95 minimum fee sets in.

See you at DAC!

, , , , , , , , , ,

3 April, 2015

It is always good to pause to recognize the companies and individuals with whom we collaborate to create the verification flows and solutions that allow the simplest and most complex devices and systems to come to life.  It is this time of year when the fruit of collaboration has generally been shared publicly.  This is probably the case, in no small part, to the nearing of the annual trek to the Design Automation Conference (DAC).  As we get closer to that week in June this year, I will discuss it even more.  But now I would like to offer a look back at two major milestones around this time of the year that shaped our future.

20 Years Ago

On April 3, 1995, we announced “Device Vendors Providing Library Support to Mentor.”  Our ModelSim simulator gained support from 12 ASIC and programmable logic vendors.  Until then, Mentor’s gate-level simulation was provided by QuickSim and its large collection of ASIC vendor libraries and flows.  With the emergence of VITAL (VHDL Initiative Towards ASIC Libraries) and as an IEEE standards project for it (1976.4) emerged, we continued our activities to drive knowledge about VITAL and educate and help the rest of the ASIC vendor community so they could bring to market their own simulation libraries for ModelSim.

As we added Verilog to the language mix, those Verilog libraries were likewise qualified and offered to the mutual customers we shared with our valued ASIC Vendor partners.  ModelSim grew to be a very popular product and the value of collaboration taught us the importance of shared collaboration.

10 Years Ago

In mid May 2005, we launched our Questa Vanguard Partnership (QVP) program modeled on the ModelSim program.  SystemVerilog 3.1a had been released by Accellera and was in the final stages of IEEE certification which was to come in November 2005.  But to get a jump on solidifying business relationships with our partners and to encourage support of SystemVerilog we began to work with companies around the world who expressed an interest to build a vibrant ecosystem.  A lot was accomplished in the six months between the launch of the QVP program to the approval of the first IEEE SystemVerliog 1800-2005 standard.

But it was good to pause then too and celebrate the standard with our new Questa partners, our mainstay semiconductor library partners and competitors in Japan.  Upon IEEE approval of the standard, Accellera in conjunction with the Big-3 EDA companies and CQ Publishing (Japan), held a “Happy Birthday” celebration reception.  I have to offer special thanks to my friends at Synopsys for the idea.  And, yes, we all know that this November will be lucky 10 years for SystemVerilog and we have already started to discuss what can be done at the annual fall standards meetings in Japan to celebrate this milestone.

Tomorrow (DAC)

As I mentioned, the great thing about this time of the year is the planning for DAC.  Many good things have happened in the last year.  Last year, at Mentor Graphics’ urging and our public commitment to donate technology, Accellera started a “Proposed Working Group” on Portable Stimulus to determine the viability of a standards project.  Accellera formally approved the formation of the Portable Stimulus Working Group in December 2014.  At the Verification Academy booth at DAC, we will certainly offer updates on this work and affirm our sustained commitment to the development of this standard.  I will share full details about what, when and where for the Verification Academy booth at DAC later.

But wait!  There will probably be more.  I can assure you, I will post a few more times during this final two-month journey to DAC.  And as the daily program for the Verification Academy booth is finalized, I will share its content my thoughts on this.  And as industry events, like the Accellera DAC Breakfast are finalized, I will make this part of my commentary on DAC 2015 as well.  It seems this DAC will be a busy DAC.

But this is something you can do now!  If you don’t know if you want to attend the technical program yet, you should at a minimum secure a free pass to the exhibit floor and access to some open industry events.  If you register by May 19th, you can choose the “I Love DAC” registration – complements of ATopTech, Atrenta, and Calypto.  After May 19th, it is no longer free.  So why not register now?  I look forward to seeing you at DAC.

, , , , , , , , , , ,

14 January, 2015

“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18.  More specifically the article states, “Who knew VIP was big and that Wally had a good piece of it?”  We knew.

We knew that ASIC and FPGA design engineers can choose to buy design IP from several alternative sources or build their own, but that does not help with the problem of verification.  We knew that you don’t really want to rely on the same source that designed your IP, to test it.  We knew that you don’t want to write and maintain bus functional models (BFMs) or more complete VIP for standard protocols.  Not that you couldn’t, but why would you if you don’t have to?

We also knew that verification teams want easy-to-use VIP that is built on a standard foundation of SystemVerilog, compliant with a protocol’s specification, and is easily configurable to your implementation.  That way it integrates into your verification environment just as easily as if you had built it yourself.

Leading design IP providers such as ARM®, PLDA, and Northwest Logic knew that Mentor Graphics’ VIP is built on standards, is protocol compliant, and is easy to use.  In fact you can read more about what Jim Wallace, systems and software group director at ARM; Stephane Hauradou, CTO of PLDA; and Brian Daellenbach, president of Northwest Logic; have to say about Mentor Graphics’ recently introduced EZ-VIP technology for PCIe 4.0 (at this website http://www.mentor.com/company/news/mentor-verification-ip-pcie-4 ), and why they know that their customers can rely on it as well.

Verification engineers knew, too.  You can read comments from many of them (at Cooley’s website http://www.deepchip.com/items/dac14-06.html ), about their opinions on VIP.  In addition, Mercury Systems also knew.  “Mentor Graphics PCIe VIP is fully compliant with the PCIe protocol specification and with UVM coding guidelines. We found that we could drop it into our existing environment and get it up and running very quickly”, said Nick Solimini, Consulting DV Engineer at Mercury Systems. “Mentor’s support for their VIP is excellent. All our technical questions were answered promptly so we were able to be productive throughout the project”.

So, now you know,  Mentor Graphics’ Questa VIP is built on standard SV UVM, is specification compliant, is easy to get up and running and is an integral part of many successful verification environments today.  If you’d like to learn more about Questa VIP and Mentor Graphics’ EZ-VIP technology, send me an email, and I’ll let you in on what (thanks to Cooley and our customers) is no longer the best kept secret in verification.  Who knew?

, , , , , , , ,

31 May, 2013

Hi Everyone,

Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles:

We’ll have plenty of copies available at DAC. Be sure to stop by the Mentor booth (2046) or the Verification Academy booth (1215) to pick one up, or just to say “Howdy.”

,

29 May, 2013

Download the standard now – at no charge

The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance and enhancement to the IEEE.  Further – Courtesy of Accellera – the standard is available for download without charge directly from the IEEE.

1801-2013_Page_001The latest update to IEEE 1801 is ready for download.  It joins other EDA standards, like SystemVerilog and SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF.  (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)

The official IEEE announcement on the standard’s publication can be found here.  And the official Accellera announcement that it has partnered with the IEEE-SA to offer the standard to all at no charge can be found here.  This revision of the standard had one of the largest number of IEEE-SA entity members of any corporate standards program.  Participation from the IEEE-SA global community of entity participants ensures the needs of a broad set of companies are captured to support this worldwide standard.

Just In Time For DAC

50th DACDAC 2013 has many events that will allow you to learn more about the new standard and how to use it to your maximum benefit.  And for those who cannot attend DAC, visit the Verification Academy, you will find the Low Power sessions cover the new standard as well. [Registration required; restrictions apply.]

Sunday
Topic: DAC Workshop:  Low-Power Design with the New IEEE 1801-2013 Standard
Date: 2 June 2013
Time: 1:00 p.m. – 5:00 p.m.
Location: Convention Center: Room 18C
Registration: Official DAC Workshop registration required ($). For more information and to register, click here.


Monday
Accellera Breakfast & Town Hall Meeting
Topic: The Standard for Low Power Design and Verification is here!  What’s next?
Date: 3 June 2013
Time: 7:00 a.m. – 8:45 a.m.
Location: Convention Center: Ballroom D
Registration: This is a free Accellera event, but registration is required.  Form more information click here and to register, click here.


Monday
Verification Academy
Topic: “Low Power Monday”
Date: 3 June 2013
Time: 11:00 a.m. – 6:00 p.m.
Location: Tradeshow Floor – Booth 1215
Registration: The DAC Tradeshow floor is open to all DAC registrants. Visit www.dac.com to register.

The Verification Academy is open to all DAC registrants.  There are no restrictions and we invite everyone to visit booth 1215 for Low Power sessions that may be of interest to you on Monday.  To help judge attendance, please feel free to pre-register at here.  I look forward to see you there as you will find me here most of the time Monday-Wednesday.

Time Description Presenter
11:00 a.m. – 12:00 p.m. Low Power Verification Tim Jordon
MicroChip Technlogy
1:00 p.m. – 2:00 p.m What’s New in UPF 2.1? Erich Marschner
IEEE 1801 Vice-chair
Mentor Graphics
2:00 p.m. – 3:00 p.m. UPF-Based Verification for Cypress PSOC Ellie Burns
Mentor Graphics
4:00 p.m. – 5:00 p.m. Optimizing for Power Efficient Design Abhishek Ranjan
Calypto
5:00 p.m. – 6:00 p.m. IEEE 1801 UPF Commands and Methodology John Biggs
ARM
IEEE 1801 Chair

If you are coming to DAC and participating in the DAC Low Power Workshop on Sunday, or in other events, download your person copy of the new IEEE 1800-2013 standard today.  The PDF form allows you to take it with you and read it using your favorite e-reader or i-device.  Let’s me know what you think of the standard.  And – See you at DAC!

, , , , , , ,

@dennisbrophy tweets

Follow dennisbrophy

@dave_59 tweets

Follow dave_59

@jhupcey tweets

  • #ARM now hiring formal verification engineers in Austin: exciting tech challenge + Ram is a great guy to work with.…https://t.co/uwIXLHWqvg
  • Attention all SF Bay Area formal practitioners: next week Wednesday 7/26 on Mentor's Fremont campus the Verificatio…https://t.co/9Y0iFXJdYi
  • This is a very hands-on, creative role for a verification expert -- join us! https://t.co/jXWFGxGrpn

Follow jhupcey