Archive for Dennis Brophy

5 September, 2017

There is certainly demand for what the Accellera DVCon events bring the global design and verification engineering community.  Not more than a few years back, there was only one DVCon in Silicon Valley.  And the design and verification community has expanded it to sister events in Europe, India, China and Japan.  User support is the reason for this growth.  Along the way, each conference has had its own regional focus on design and verification challenges.  Because the other DVCon’s are shorter in duration, some elements of those conferences have had to shrink to accommodate allotted time.  What has been found, some of those reduced timed sessions have been valuable and yielded meaningful information that could be immediately used in daily design and verification practice.

New for 2018: Short Workshops

As the DVCon U.S. Chair for 2017, I thought it would be good to pull in the short format focused technical sessions to broaden the conference topics and expand the number of design and verification practitioners that would find the conference an important event to attend.  The Short Workshop concept comes out of this.  On the Thursday Tutorial Day, in addition to the in-depth half-day tutorials, we have added shorter sponsored workshops.  The intent of this change is to expand the conference content and support newer sponsors to participate more fully in DVCon U.S.  Some ideas are better discussed in a workshop format in shorter time.  I look forward to the ideas we get from this conference addition.  To learn more about the Short Workshops, click here.  The deadline for idea submissions is 29 September 2017.

I am always open to more feedback how we can improved DVCon U.S.  And I hope this change will bring a focus on topic areas you may have felt we have not had the time to include.

Sister Conference Update

For those in India and Europe, DVCon India is only a few weeks away, 14-15 September 2017 and DVCon Europe is the following month, 16-17 October 2017.  The fourth edition of these conferences are set and I look forward to continued growth in user participation and practical information one gets that can be applied to one’s current work. Check them out!  Your peers have been working hard to bring a focus on issues you probably share with them at these two conferences.

, , , , , ,

1 June, 2017

Accellera’s Emerging Portable Stimulus Standard Is Pervasive at DAC 54

For the past few years, Accellera’s Portable Stimulus Working Group has been busy at work on the new standard to elevate stimulus generation to improve overall verification productivity.  As the call to attend the annual Accellera breakfast DAC 54 informs us, the Accellera Portable Stimulus early adopter release is planned to be made available prior to DAC.  I’m certain that a download of the early adopter release will make for good reading for those traveling to DAC and have not participated in the development of the standard.  I predict it will be a “page-turner.”  You will be in a much better position to attend the following events in and around DAC (some of which require DAC registration fee payment and some that are fee-free) if you download and read it when ready.  Here are some of the DAC 54 Portable Stimulus activities:

Monday June 19th

Tuesday June 20th

Wednesday June 21st

And for those who will not be attending DAC, I will update this blog with information on how you can download the Accellera Portable Stimulus early adopter release.  There is also online educational videos about the emerging Portable Stimulus standard.  You can find a two sessions at the Mentor Verification Academy on Portable Stimulus Basics. And the DVCon U.S. 2017 technical tutorial, Creating Portable Stimulus Models with the Upcoming Accellera Standard, presented in three parts is located at the Accellera website.  Both online educational video offerings require registration.

, , , ,

3 May, 2017

VIP: Accelerating SoC Design Verification

Your SoC designs have grown more complex, not just by the sheer number of transistors that can be packed into one design, but the emergence of different interconnect methods you must use to connect chip internals and to connect to the outside world.  With each of these interconnect methods, design IP blocks support a faster SoC design process.  However, being an expert on each of the interconnect methods or protocols is not likely leading to protracted SoC verification schedules, reduced design productivity and exposing your designs to bugs that might only be found when in use by the end consumer.

These complex industry standard interfaces can be more rapidly verified in your SoC design with the use of Verification IP (VIP).  You will still need to understand the specific protocols, but when VIP is used you improve design quality and reduce verification time which allows you to hit aggressive time-to-market goals.

To foster industry discussion and share best practices we invite you to the Silicon Valley Design & Verification IP Forum 2017.  The forum brings DIP and VIP designers, integrators and partners together to learn the latest in IP-driven verification trends and solutions.  The forum will have presentations on numerous protocols include MIPI CSI-2, USB 3.1, PCIe Gen 4, DDR & Flash memory and IEEE 802.3 Ethernet PHY.

The day will be full of presentation from those protocol experts and will start with an opening keynote from Mentor’s verification chief scientist, Harry Foster. Harry will explore “Conquering the New IP Economy” in his keynote.  Several of our Questa Vanguard Partners who supply design IP will also be present to show how all this works together to accelerate SoC design verification closure.

Silicon Valley Design & Verification IP Forum 2017 Details

Date: May 9, 2017
Time: 8:30 a.m. – 4:15 p.m. PT
Location: San Jose, CA USA
Register: Click here.

The event is free of charge to qualified registrants and includes lunch.  The lunch keynote will be presented by Niraj Mathur, VP High Speed Interface Products, Rambus.  Niraj will share is 20 years of experience in advanced SoC & IP design, verification, software and cross-functional, global engineering team challenges.

I look forward to seeing your there!

, , , , , , , , , ,

15 December, 2016

Technical Program is Live

For the past several months, the DVCon U.S. Steering Committee has been meeting to craft a compelling event of technical papers, panels, keynotes, poster sessions and more for you.  With the hard work of authors who supply this content and the Technical Program Committee that reviews and selects from this content, a 4-day event schedule is now published.  You can find the event schedule here.

I am pleased to chair DVCon U.S. 2017 and work with such an august body of people – from the electronic design automation industry, design and verification practitioners and professionals from large systems houses to small consultancies – all who work hard for you to make this happen.  As has been the tradition of DVCon U.S. the past several years, the event starts with Accellera Day on Monday (Feb 27th) followed by two days of paper presentations, keynotes, panels and an exhibition.  The exhibition starts Monday, Accellera Day.  The last day of DVCon U.S. features a full day of tutorials split in to half-day parts.

Accellera Day

DVCon U.S. will feature something for advanced users and those who may be more novice.  The conference will showcase emerging standards and updates to those standards well used.  On Monday, Accellera Day, DVCon U.S. begins with a tutorial devoted to work underway within Accellera on a new standard, “Portable Stimulus,” that is set to give design and verification engineers a boost in overall design and verification productivity.  Given the work by the Accellera Portable Stimulus Working Group to put as much of the standard in place that it can, this tutorial, Creating Portable Stimulus Models with the Upcoming Accellera Standard, is sure to be an important educational opportunity.  If you are a user of UVM (Universal Verification Methodology) you will find the Portable Stimulus standard is set to remove many of the limitations of reuse at the subsystem and full-chip level and address the lack of portability across execution platforms.  Are you ready for Portable Stimulus?  You will be ready after attending this tutorial.

As the Monday luncheon evolves, I anticipate a moderated panel discussion hosted by Accellera on the emerging Portable Stimulus standard based on what you learned in the morning session.  As lunch ends, two parallel tutorials will start, one on IEEE P1800.2™ (aka UVM) and the other on System C design and verification advances.  Accellera Day is a great event to learn about the latest in the evolution of standards coming from Accellera and the IEEE.

Special Session

DVCon U.S. will make one departure from prior years’ programs and offer a special session on Tuesday on Trends in Functional Verification: A 2016 Industry Study presented by Harry Foster.  Harry has been reporting on the 2016 Wilson Research Group Study here at the Verification Horizon’s BLOG, and he has shared regional information at DVCon Europe and DVCon India on adoption and use of design and verification tools, technology and standards.  At DVCon U.S. he will pull all this together to show trends and offer predictions for the future.

There is much more to DVCon U.S. 2017 that I think you will find useful.  I leave it to you to explore the program more to discover this for yourself.  And if you can make it to DVCon U.S., registration is also open with advanced rates available until January 26th.  I hope to see you there!

, , , , , , ,

22 September, 2016

Join us for the Verification Academy Live Seminar on Enterprise Debug & Analysis

Your designs are larger and more complex than ever and your verification solutions are generating more information that needs to be managed and analyzed.  Your need to build and validate systems with pre-built design IP that comes from multiple sources places time-to-market burdens on you that need to be addressed. Your ability to debug your system from the design described in RTL running on simulation farms to emulators and FPGA prototypes with eventual debug of post silicon implementation drives even more complexity.  And in the face of the adoption of newer methodologies like UVM, often embraced in unstructured ways, poses its own productivity burdens.

This pressure shows itself in our annual semi-annual industry survey results that illustrates there are now more verification engineers than design engineers for a team (a recent phenomena) and the time spent on debug now approaches 40% of an engineer’s total project time budget.

Clearly, improving debug productivity for an enterprise flow from block to system pre-silicon verification, virtual prototyping, emulation, as well as post-silicon validation is critical to stay on schedule and at the same time meet your end product quality goals.

We invite you to join us for a comprehensive seminar to learn the very latest verification techniques to address these challenges.  Harry Foster, Mentor Graphics Chief Verification Scientist, will review the 2016 Wilson Research Group Functional Verification Study in his featured keynote to open the seminar.  The seminar will review enterprise-level requirements, solutions and offer additional end-user keynotes that will help address your key challenges.  Click here for more information about the seminar and how to register.  Event details are below:

Verification Academy Live Seminar

  • Location: Santa Clara, CA USA
  • Date: Thursday – October 6, 2016
  • Agenda:
    • 08:30 – 09:00 Check in and Registration
    • 09:00 – 09:50 Industry Trends in Today’s Functional Verification Landscape
    • 09:50 – 10:10 Enterprise Verification Required
    • 10:15 – 11:00 Enterprise Debug for Simulation & Formal
    • 11:00 – 11:15 Break
    • 11:15 – 12:00 Shortcut to Productive Enterprise Verification with VIP, a UVM framework and a configuration GUI
    • 12:00 – 12:40 Lunch
    • 12:40 – 13:10 User Keynote Session
    • 13:10 – 13:40 Enterprise System Level Analysis
    • 13:40 – 14:00 Break
    • 14:00 – 14:40 System-Level Debug with Emulation
    • 14:40 – 15:10 User Keynote Session
    • 15:10 – 15:50 FPGA Prototyping: Maximize your Enterprise Debug Productivity
    • 15:50 – 16:00 Closing Remarks and Prize Drawing

, , , , , , ,

18 August, 2016

A great technical program awaits you for DVCon India 2016!  The DVCon India Steering Committee and Technical Program Committee have put together another outstanding program.  The two-day event splits itself into two main technical tracks: one for the Design Verification professional [DV Track] and the other from the Electronic System Design professional [ESL Track].  The conference will be held on Thursday & Friday, 15-16 September 2016 at the Leela Palace in Bangalore.  The conference opens with industry keynotes and a round of technical tutorials the first day.  Wally Rhines, Mentor Graphics CEO, will be the first keynote of the morning on “Design Verification – Challenging Yesterday, Today and Tomorrow.”

Mentor Graphics at DVCon India

In addition to Wally’s keynote, Mentor Graphics has sponsored several tutorials which when combined with other conference tutorials shares information, techniques and tips-and-tricks that can be applied to your current design and verification challenges.

The conference’s other technical elements (Posters, Panels & Papers) will likewise feature Mentor Graphics participants.  You should visit the DVCon India website for the full details on the comprehensive and deep program that has been put together.  The breadth of topics makes it an outstanding program.

Accellera Portable Stimulus Standard (PSS)

The hit of the first DVCon India was the early discussion about the emerging standardization activity in Accellera on “Portable Stimulus.”  In fact, at the second DVCon India a follow-up presentation on PSS standardization was requested and given as well (Leveraging Portable Stimulus Across Domains and Disciplines).  This year will be no exception to cover the PSS topic.

The Accellera Tutorial for DVCon India 2016 is on the emerging Portable Stimulus Standard.  The last thing any design and verification team wants to do is to rewrite a test as a design progresses along a path from concept to silicon.  The Accellera PSS tutorial will share with you concepts being ratified in the standard to bring the next generation of verification productivity and efficiency to you to avoid this.  Don’t be surprised if the PSS tutorial is standing room only.  I suggest if you want a seat, you come early to the room.

Register

To attend DVCon India, you must register.  A discounted registration rates available through 30 August 2016.  Click here to register!  I look forward to see you at DVCon India 2016! If you can’t join us in person, track the Mentor team on social media or on Twitter with hashtag #DVCon.

, , , , , , , ,

24 May, 2016

Join us at the 53rd Design Automation Conference

DAC is always a time of jam-packed activity with multiple events that merit your time and attention.  As you prepare your own personal calendars and try your best to reduce or eliminate conflicts, let me share with you some candidate events that you may wish to consider having on your calendar.  I will highlight opportunities to learn more about ongoing and emerging standards from Accellera and IEEE.  I will focus on a few sessions at the Verification Academy booth (#627) that feature Partner presentations.  And I will spotlight some venues where other industry collaboration will be detailed.  You will also find me at many of these events as well.

Standards

Accellera will host its traditional Tuesday morning breakfast.  Registration is required – or you might not find a seat.  As always, breakfast is free.  The morning will feature a “Town Hall” style meeting that will cover UVM (also known as IEEE P1800.2) and other technical challenges that could help evolve UVM into other areas.   Find out more and learn about all things UVM, register here.

Partners

The Verification Academy is “partner-central” for us this year.  Each day will feature partner presentations that highlight evolving design and verification methodologies, standards support and evolution, and product integrations.  Verification Academy is booth #627, which is centrally located and easy to find.  Partner presentations include:

  • Back to the Stone Ages for Advanced Verification
    Monday June 6th
    2:00 PM | Neil Johnson – XtremeEDA

    Modern development approaches are leaving quality gaps that advanced verification techniques fail to address… and the gaps are growing in spite of new innovation. It’s time for a fun, frank and highly interactive discussion around the shortcomings of today’s advanced verification methods.

  • SystemVerilog Assertions – Bind files & Best Known Practices
    Monday June 6th
    3:00 PM | Cliff Cummings – Sunburst Design

    SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. 13 years of professional SVA usage strongly suggests that Best Known Practices use bindfiles to add assertions to RTL code.

  • Specification to Realization flow using ISequenceSpec™ and Questa® InFact
    Tuesday June 7th
    10:00 AM | Anupam Bakshi – Agnisys, Inc.

    Using an Ethernet Controller design, we show how complete verification can be done in an automated manner, saving time while improving quality. Integration of two tools will be shown. InFact creates tests for a variety of scenarios which is more efficient and exhaustive than a pure constrained random methodology. ISequenceSpec forms a layer of abstraction around the IP/SoC from a specification.

  • Safety Critical Verification
    Wednesday June 8th
    10:00 AM | Mike Bartley – TVS

    The traditional environments for safety-related hardware and software such as avionics, rail and nuclear have been joined by others (such as automotive and medical devices) as systems become increasingly complex and ever more reliant on embedded software. In tandem, further industry-specific safety standards (including ISO 26262 for automotive applications and IEC 62304 for medical device software) have been introduced to ensure that hardware and software in these application areas has been developed and tested to achieve a defined level of integrity. In this presentation, we will be explaining some of these changes and how they can be implemented.

  • Using a Chessboard Challenge to Discover Real-world Formal Techniques
    Wednesday June 8th
    3:00 PM | Vigyan Singhal & Prashant Aggarwal – Oski Technology

    In December 2015, Oski challenged formal users to solve a chessboard problem. This was an opportunity to show how nifty formal techniques might be used to solve a fun puzzle. Design verification engineers from a variety of semiconductor companies and research labs participated in the contest. The techniques submitted by participants presented a number of worthy solutions, with varying degrees of success.

Industry Collaboration

Debug Data API: “Cadence and Mentor Demonstrate Collaboration for open Debug Data API in Action”  It was just a year ago that the project to create an open debug data API was announced at DAC 52.  Since there several possible implementation styles were reviewed, an agreed specification created and early working prototypes demonstrated.  On Tuesday, June 7th at 2:00pm we will host a session at the Verification Academy (Booth #627).  You are encouraged to register for the free session – but walkups are always welcome!  You can find more information here.

Portable Stimulus Tutorial: “How Portable Stimulus Addresses Key Verification, Test Reuse, and Portability Challenges”  As part of the official DAC program, there will be a tutorial on the emerging standardization work in Accellera.  The tutorial is Monday, June 6th from 1:30pm – 3:00pm in the Austin Convention Center, Room 15.  You can register here for the tutorial.  There is a fee for this event.  Want to know more about the tutorial?  You can find more information here.

Fun

It is always good to end the day on a light note.  To that end, on Monday June 6th, will invite you to “grab a cold one” at the Verification Academy booth and continue discussions and networking with your colleagues.  If past year’s experience is any guide to this year, you may want to get here early for your drink!  There is no registration to guarantee a drink, unfortunately!  So, come early; stay late!  See you in Austin!

And if you miss me at any of the locations above, tweet me @dennisbrophy – your message is sure to reach me right away.

, , , , , , , , , , , , , , , , ,

23 February, 2016

https://farm2.staticflickr.com/1667/25218331075_2089dcd80c.jpgFirst Debut of Working API at DVCon U.S. 2016

The Debug Data API is set to make its first public debut at a “meet up” of interested people at DVCon U.S.  The meet up will be from 5:15pm – 5:45pm on Tuesday, March 1st in the Fir ballroom at the DoubleTree Hotel in San Jose, CA.  You are invited to see a demonstration of a debug function written in C running on first prototypes from Mentor and Cadence that take a common design with simulation datasets from two simulators and produce identical debug results.  In addition, we will present current status on the Debug Data API development and projected timeline of support.  The industry has invested decades in access methods for live simulation, but common post simulation results data access has been generally limited to ASCII file dumps in the VCD or eVCD format that have reached their end-of-life.

For more complex designs, the one-engineer to one-simulator day has passed and long replaced by verification runs leveraging the Universal Verification Methodology (UVM) that is deeply connected to constrained random simulation techniques within simulation data centers that produce a magnitude more information.  Add to that the impact of emulation and the massive amount of verification results is daunting and motivates us to support an industry-wide common data read API.

Register for DVCon

The Tuesday evening meet up will be during DVCon exhibition hours.  If you have  registered to attend DVCon U.S., you already have an exhibit pass.  If you have not yet registered and only wish to attend this event, it is free, but you need to register for exhibit access.  In addition to being able to attend the exhibition for free, Expo-only registrants can also attend panels and Wally Rhines’ keynote on Tuesday fee free as well.

The meet up is not the only place to learn more about the emerging prototype implementation of the Debug Data API.  Feel free to visit the demo booths Monday – Wednesday to learn more.  You will find Mentor Graphics at booth (#501).  You can always stop me at DVCon too and I would be more than happy to update you on our progress and plans.

It was not too long ago at DAC 2015, a project to incubate a debug data API standard was launched and I blogged about the need for it.  At DAC we demonstrated data exchange between simulation and debug environments and shared an overall architectural outline.  Then in October 2015, the initial Debug Data API specification was released for public comment and input and I blogged about it at that time.  This resulted in several months of industry interaction and a refined specification, which is now taking first implementation steps.

Join us Tuesday evening to witness and celebrate these first steps.  See you at DVCon U.S.!

, , , , , ,

8 February, 2016

Join Us at DVCon

As an annual conference, DVCon has set itself apart from others.  With a high focus on the application of design and verification tools and technology the venue is a prime location to exchange best practices and learn about emerging and current standards for the practicing engineer.  DVCon has also gone global to promote locally the sharing of best practices and building a wider global audience.  The flag ship event, DVCon U.S. has grown into an event that brackets two days of paper and poster sessions with tutorials on sessions on emerging standards from Accellera and how-to practical information by producers and users of design automations technology.  Building knowledge, skill and proficiency that can be applied in one’s design and verification engineering profession is unique.  What can you learn?  How can you share?

The answer to those questions has one simple answer: Attend DVCon U.S.  What specifically might apply to your current engineering demands are best found examining the conference program.  DVCon U.S. runs Monday – Thursday (29 February – 3 March 2016).  Monday is “Accellera Day” and features a focus on emerging and popular standards.  Content is geared for both beginners and advanced users.  Tuesday and Wednesday will feature papers, panels, posters and keynotes.  The topics will take you from system level to gates and from design to verification and hardware to software and portable stimulus to low power design.  These two days are organized as more of a traditional technical conference with parallel track, complemented by sponsored lunches and afternoon/evening exhibition for tool and services suppliers to share their latest product offerings.  Wednesday concludes with announcing the best paper and poster awards.  But that is not the end of the conference.  Thursday is “Tutorial Day.”  Four parallel half-day tutorials will be presented on a variety of topics.  The Mentor Graphics team has sponsored two of the tutorials, one in the morning and one in the afternoon:

  • Tutorial 5: Advanced Validation and Functional Verification Techniques for Complex Low Power System-on-Chips
  • Tutorial 9: Back to Basics: Doing Formal the Right Way

Low Power Tutorial: New IEEE 1801 Standard

In this blog, I would like to focus in on Tutorial 5 as it relates to one of the most daunting challenges today: low power design of SoC’s.  And, this tutorial will explore how new constructs in IEEE Std. 1801™-2015 (UPF 3.0) can facilitate power modeling at high levels of abstraction and improve application of Successive Refinement methodology.  At the publication of this blog, the IEEE has not yet published this new standard.  It was approved at the IEEE Standards Association meeting series in December 2015.  If you were a member of the IEEE ballot group or a member of the IEEE 1801 Working Group, you have a copy of the last draft of the standard and have access to all the information you might need on the new constructs that were added.  For everyone else, my recommendation is to attend DVCon U.S. and this tutorial to learn more in advance of the publication from the experts who created the standard and the Successive Refinement methodology.

You can find full information about DVCon U.S. here and to join us, register here.  And if your time is really limited and you can’t make the full conference, the Exhibition runs into the evening (Monday – Wednesday) for those who are local and might want to visit after work.  Even better news, the Exhibits-only pass is fee free.  See you there!

, , , , ,

25 October, 2015

Verification Academy Brings “UVM Live” to the Santa Clara Convention Center

Uvm logoFor everyone involved in the functional verification of electronic systems, you know about the Universal Verification Methodology (UVM) and are probably using it in one fashion or another.  And if you have been reading this blog, you have undoubtedly seen blogs by Harry Foster on the adoption and use of UVM by the FPGA and ASIC/SoC community.  It has clearly become the world’s most popular and accepted verification methodology.  It is odd to point out that with this popularity, there has not been a UVM-only event to bring UVM users together this year.  We believe it is time for UVM users to come together to explore its use and share productivity tips and tricks with each other.  You are invited to register and attend.  The details of the event are:

          Event: UVM Forum – Verification Academy Live Seminar
          Location: Santa Clara Convention Center, Santa Clara, CA USA
          Date: 17 November 2015
          Time: 8:30 a.m. – 4:00 p.m. PT
          More Information & Agenda: Click Here
          Register: Click Here

Experts Learn Something New

If you are an UVM Expert, and already know just about everything about UVM, you might be interested in some new topics that will be introduced and expanded upon.  Here are four:

The first is UVM Framework.  UVM Framework supports reuse across projects, sites and companies from block to chip to system for both simulation and emulation.  Those using it have seen at least a four week reduction in verification product schedules.

The second is Verification IP.  VIP can help you overcome your IP verification challenges.  One session will explore integrating VIP into a UVM environment with examples based on protocols such as AMBA®, MIPI® and PCI Express®.  If you are not an expert on a specific protocol, you can use VIP to drive stimulus and verify protocol compliance for you.

The third is Automating Scenario-Level UVM Test with Portable Stimulus.  In this session you will learn to rise above the transaction level to make scenario creation more productive.  You will learn how to leverage lower-level descriptions, such as sequence items, into larger scenarios.  You will learn how to leverage graph-based methods to efficiently and predicable exercise the scenario space to deliver high quality verification results.  It should also be noted, that an ongoing Accellera Working Group is exploring standardization of Portable Stimulus.  While Accellera working group details are not part of the session, UVM Forum attendees might consider augmenting their knowledge by visiting the Accellera Portable Stimulus group.

The fourth is Improved UVM Testbench Debug Productivity and Visibility.  For those who debug UVM on a daily basis, you might hear a common question “Are we having fun yet?” asked.  The debug of UVM can be particularly difficult.  We will have a session to show you how to navigate complex UVM environments to quickly find your way around the code – whether its your own or inherited.  You will see how SystemVerilog/UVM dynamic class activity is as easy to debug as it is with RTL signals.  Want to learn how to solve the top 10 common UVM bring-up issues with config_db, the factory, and sequence execution?  Attend and you will learn.

Novices Welcome (and will learn something too!)

While I can’t promise that if you come as a novice you will leave as an expert, you can learn about UVM in the morning as one of the sessions is a technology overview to ensure you won’t be lost when the experts speak.  If you know very little about UVM, the UVM Forum will help you.  There will be a couple presentations from UVM users.  One session is on how UVM enabled advanced storage IP silicon success (presented by Micron) and another session on UVM and emulation to ease the path to advanced verification and analysis (presented by Qualcomm).

Still want to know more before you attend?  You can also boost your UVM knowledge by attending an online UVM Basics course at Verification Academy.  Visit here to learn more about the UVM Basics course.  The Basic UVM course consists of 8 sessions with over an hour of instructional content. This course is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained random verification or object-oriented programming. The goal of the course is to raise the level of UVM knowledge to the point where users have sufficient confidence in their own technical understanding that it becomes less of a barrier to adoption – and makes the UVM Forum 2015 more meaningful for you.

I look forward to seeing you there.

, , , , , , , , , ,

@dennisbrophy tweets

Follow dennisbrophy

@dave_59 tweets

Follow dave_59

@jhupcey tweets

Follow jhupcey