Portable Stimulus the Hot Topic at DVCon U.S. ’17
Just getting around to gathering my thoughts about the great week we had at DVCon U.S. As Program Chair for the conference, I felt a great sense of pride that, with a great deal of help from my colleagues on the conference Steering Committee and especially the great team of experts on the Technical Program Committee, we were able to provide the attendees with a packed program of interesting, informative and entertaining events. But, as always happens, there was one topic that seemed to get the lion’s share of attention. This year, it was Portable Stimulus.
Starting with a standing-room-only crowd (even after bringing in more chairs) of nearly 200 people on Monday morning for the Accellera Day tutorial presented by the members of the Portable Stimulus Working Group (including yours truly), Portable Stimulus never seemed to be far from any of the discussions.
If you weren’t able to attend the conference, Accellera will be presenting the tutorial as a series of webinars in early April, so you’ll be able to see what got everyone so excited. In addition to the tutorial, there was a “Users Talk Back” panel session on Wednesday morning that gave several user companies a chance to voice their opinions about the upcoming Portable Stimulus standard. Having been so involved in the standardization effort, I was gratified to hear the generally positive feedback by these industry leaders.
We were pleased also to have two great Portable Stimulus articles in our most recent issue of Verification Horizons. The first article is from our friends at CVC showing how they used Questa inFact to create a portable graph-based stimulus model that they used in their UVM environment to verify a memory controller design. The second is from my colleague Matthew Ballance, who is also a key technical contributor to the PSWG efforts, and discusses Automating Tests with Portable Stimulus from IP to SoC Level. In this article, you’ll learn about some of the concepts and language constructs of the proposed standard to see how the declarative nature of the standard makes it easier to specify complex scenarios for block-level verification and to combine those into SoC-level scenarios that are often difficult to express with UVM sequences.
The other exciting news I wanted to share with you is our new Portable Stimulus Basics video course on Verification Academy. We can’t yet share all the details of the upcoming standard, since things are still being finalized in the Working Group, but as things are made public, we’ll be sharing what we can so you’ll be the first to learn about this exciting new standard. As we add new sessions to the course, we’ll be sure to let you know. Please go check it out.
Posted March 13th, 2017, by Tom Fitzpatrick
- Evolving Product Lifecycle Requires New Debugging Skills
- Portable Stimulus Specification Released for Public Review
- Reusing Existing Descriptions with New Languages
- DAC 54 Spotlight on “Portable Stimulus”
- Going With The Flow – Overview
- DVCon China: Formal Technology Is Set for Growth in Asia
- Design & Verification IP Forum 2017
- Portable Stimulus: Standard vs. Tool vs. Language
- Portable Stimulus the Hot Topic at DVCon U.S. ’17
- The Walking LRM