How To Connect Your Testbench to Your Low Power UPF Models

Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL. But proper connection and behaviors of power nets and logic – power down, retention, recovery, etc. – must be verified like any other DUT element. As such, the question is how can D&V engineers link their testbench code to the IEEE 1801 Unified Power Format (UPF) files that describe the design’s low power structures and behaviors, so verification of all that low power “stuff” can be included in the verification plan?

A real power distribution setup

Fortunately, the answer is relatively straightforward.  In a nutshell, the top level UPF supply ports and supply nets provide hooks for the design, libraries, and annotated testbenches through the UPF connect_supply_net and connect_supply_set commands – these define the complete power network connectivity. Additionally, the top level UPF supply ports and supply nets are collectively known as supply pads or supply pins (e.g. VDD, VSS etc.), where the UPF low power standard recommends how supply pads may be referenced in the testbenches and extended to manipulate power network connectivity in a testbench simulation. Hence it becomes possible to control power ‘On’ and ‘Off’ for any power domain in the design through the supply pad referenced in the testbench.

All the necessary HDL testbench connections are done through importing UPF packages available under the power-aware simulation tool distribution environment. Even better: the IEEE 1801 LRM provides standard UPF packages for Verilog, SystemVerilog, and VHDL testbenches to import the appropriate UPF packages to manipulate the supply pads of the design under verification. The following are syntax examples for UPF packages to be imported or used in different HDL variants.
Example of UPF package setup for Verilog or SystemVerilog testbench

import UPF::*;
module testbench;
...
endmodule

Note: UPF packages can be imported within or outside of the module-endmodule declaration.

Example UPF package setup for a VHDL testbench

library ieee;
use ieee.UPF.all;

entity dut is
...
end entity;

architecture arch of dut is

begin
...
end arch;

The “import UPF::*” package and “use ieee.UPF.all;” library actually embeds the functions that are used to utilize and drive the design supply pads directly from the testbench. Thus, once these packages are referenced in the testbench, the simulator automatically searches for them from the simulator installation locations and makes the built-in functions of these packages available to utilize in the simulation environment. The following examples explain these functions, namely supply_on and supply_off with their detailed arguments.

Example functions for Verilog and SystemVerilog testbenches to drive supply pads

supply_on( string pad_name, real value = 1.0, string file_info = "");

supply_off( string pad_name, string file_info = "" );

Note: Questa Power Aware Simulator (PA SIM) users do not have to deal with the third argument, string file_info = “” – Questa will be automatically take care of this automatically.

Example functions for a VHDL testbench driving supply pads

supply_on ( pad_name : IN string ; value : IN real ) return boolean;

supply_off ( pad_name : IN string ) return boolean;

Regardless of the language used, the pad_name must be a string constant, and a valid top level UPF supply port must be passed to this argument along with a “non-zero” real value to denote power “On”, or “empty” to denote power “Off”. Questa PA-SIM will obtain the top module design name from the UPF set_scope commands defined below.

Now that the basic package binding and initial wiring is setup, how do you actually control the design supply pad through a testbench?  This is where the aforementioned UPF connect_supply_net or connect_supply_set and set_scope commands come in, as per the following code examples.

Example UPF with connect_supply_net for utilizing supply pads from the testbench

set_scope cpu_top
create_power_domain PD_top
......

# IMPLEMENTATION UPF Snippet
# Create top level power domain supply ports
create_supply_port VDD_A -domain PD_top
create_supply_port VDD_B -domain PD_top
create_supply_port VSS -domain PD_top

# Create supply nets
create_supply_net VDD_A -domain PD_top
create_supply_net VDD_B -domain PD_top
create_supply_net VSS -domain PD_top

# Connect top level power domain supply ports to supply nets
connect_supply_net VDD_A -ports VDD_A
connect_supply_net VDD_B -ports VDD_B
connect_supply_net VSS -ports VSS

Next, the UPF connect_supply_net specified supply ports VDD_A, VDD_B, VSS, etc. can be directly driven from the testbench as shown in the following code example.

import UPF::*;
module testbench;
...
reg VDD_A, VDD_B, VSS;
reg ISO_ctrl;
...
initial begin
#100
ISO_ctrl = 1’b1;
supply_on (VDD_A, 1.10); // Values represent voltage & non zero value

// (1.10) signifies Power On

supply_on (VSS, 0.0); // UPF LRM Specifies Ground VSS On at 0.0
...
#200
supply_on (VDD_B, 1.10);
...
#400
supply_off (VDD_A);   // empty real value argument indicates Power Off

...
end
endmodule

That’s all there is to it!

As you can glean from the examples, it is pretty easy to design a voltage regulator or a power management unit in the testbench through the functions supply_on and supply_off to mimic a real chip’s power operations. Of course there are many more functions available under these UPF packages, but hopefully this article is enough to get you started.

Joe Hupcey III
Progyna Khondkar
for the Questa Low Power Design & Verification product team

Related posts:

Part 11: The 2016 Wilson Research Group Functional Verification Study on ASIC/IC Low Power Trends

3 Things About UPF 3.0 You Need to Know Now

Whitepaper: Advanced Verification of Low Power Designs

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