DVCon U.S. 2017: Bigger and Better!
For the past several months, the DVCon U.S. Steering Committee has been meeting to craft a compelling event of technical papers, panels, keynotes, poster sessions and more for you. With the hard work of authors who supply this content and the Technical Program Committee that reviews and selects from this content, a 4-day event schedule is now published. You can find the event schedule here.
I am pleased to chair DVCon U.S. 2017 and work with such an august body of people – from the electronic design automation industry, design and verification practitioners and professionals from large systems houses to small consultancies – all who work hard for you to make this happen. As has been the tradition of DVCon U.S. the past several years, the event starts with Accellera Day on Monday (Feb 27th) followed by two days of paper presentations, keynotes, panels and an exhibition. The exhibition starts Monday, Accellera Day. The last day of DVCon U.S. features a full day of tutorials split in to half-day parts.
DVCon U.S. will feature something for advanced users and those who may be more novice. The conference will showcase emerging standards and updates to those standards well used. On Monday, Accellera Day, DVCon U.S. begins with a tutorial devoted to work underway within Accellera on a new standard, “Portable Stimulus,” that is set to give design and verification engineers a boost in overall design and verification productivity. Given the work by the Accellera Portable Stimulus Working Group to put as much of the standard in place that it can, this tutorial, Creating Portable Stimulus Models with the Upcoming Accellera Standard, is sure to be an important educational opportunity. If you are a user of UVM (Universal Verification Methodology) you will find the Portable Stimulus standard is set to remove many of the limitations of reuse at the subsystem and full-chip level and address the lack of portability across execution platforms. Are you ready for Portable Stimulus? You will be ready after attending this tutorial.
As the Monday luncheon evolves, I anticipate a moderated panel discussion hosted by Accellera on the emerging Portable Stimulus standard based on what you learned in the morning session. As lunch ends, two parallel tutorials will start, one on IEEE P1800.2™ (aka UVM) and the other on System C design and verification advances. Accellera Day is a great event to learn about the latest in the evolution of standards coming from Accellera and the IEEE.
DVCon U.S. will make one departure from prior years’ programs and offer a special session on Tuesday on Trends in Functional Verification: A 2016 Industry Study presented by Harry Foster. Harry has been reporting on the 2016 Wilson Research Group Study here at the Verification Horizon’s BLOG, and he has shared regional information at DVCon Europe and DVCon India on adoption and use of design and verification tools, technology and standards. At DVCon U.S. he will pull all this together to show trends and offer predictions for the future.
There is much more to DVCon U.S. 2017 that I think you will find useful. I leave it to you to explore the program more to discover this for yourself. And if you can make it to DVCon U.S., registration is also open with advanced rates available until January 26th. I hope to see you there!
Posted December 15th, 2016, by Dennis Brophy
- Portable Stimulus: Standard vs. Tool vs. Language
- Portable Stimulus the Hot Topic at DVCon U.S. ’17
- The Walking LRM
- Will UVM 1800.2 Leave You Behind?
- How Any Verification Engineer Can Quickly Create a Complex Testbench
- How To Connect Your Testbench to Your Low Power UPF Models
- Holiday UVM Register Indigestion
- Conclusion: The 2016 Wilson Research Group Functional Verification Study
- DVCon U.S. 2017: Bigger and Better!
- Emulation and simulation; invaluable tools for IC verification