DVCon 2014 Issue of Verification Horizons Now Available
DVCon is always one of my favorite events in our industry, and I am proud to let you know that the latest issue of Verification Horizons is available “hot off the presses” at the Verification Academy to mark the occasion. For those of you attending the conference, please consider this issue as an addendum to the great technical program being offered (especially paper 8.1, “Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It” by Dave Rich and yours truly). For those of you not able to join us at DVCon this year, consider this your consolation prize.
Although fewer in number, I’m sure you’ll find the articles in Verification Horizons as informational and useful as any you’ll see at DVCon. In particular, I’d like to make sure you check out these articles by our partners:
- “Don’t Forget the Little Things That Can Make Verification Easier” by our friend Stu Sutherland of Sutherland HDL
- “Taming Power-Aware Bugs with Questa Ultra” by SmartPlay Technologies
- “Using Mentor Questa for pre-silicon validation of IEEE 1149.1-2013 based Silicon Instruments” by Intellitech
- “Dealing With UVM and OVM Sequences” by eInfochips
If you’re at DVCon, please make sure to stop by the Mentor Graphics booth (#501) to say hi. Please join us on Wednesday for our luncheon presentation at noon, right after Session 8, in which I’ll present my paper mentioned above (that’s right. I’m not above shameless self-promotion). And we’ll wrap up the week with two Mentor-sponsored tutorials on Thursday:
- Tutorial 7 on Thursday morning, “Block to System Verification: Smooth Sailing from Simulation to Emulation”
- Tutorial 11 on Thursday afternoon, “Formal Verification in Practice: Technology, Methods and Applications”
Both of these tutorials feature a mix of Mentor presenters and customers to offer some practical examples that will give you some new ideas for improving your verification process. I hope to see you at DVCon.
Posted March 3rd, 2014, by Tom Fitzpatrick
- IEEE-SA EDA & IP Interoperability Symposium
- Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification
- Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker
- Ready for a Verification Extravaganza in the Land of Verification Engineers?
- Conclusion: The 2014 Wilson Research Group Functional Verification Study
- How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 2 of 2
- Part 12: The 2014 Wilson Research Group Functional Verification Study
- Beating Design Complexity with VirtuaLAB
- Part 11: The 2014 Wilson Research Group Functional Verification Study
- How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 1 of 2