Archive for July, 2012

27 July, 2012

At the 2012 Design Automation Conference, I had the pleasure of moderating a panel at a workshop titled “Post-Silicon Debug: Technologies, Methodologies, and Best-Practices.” This workshop brought together a collection of experts from industry, academia, and EDA to discuss the emerging challenges and solutions associated with post-silicon validation. The speakers presented different instrumentation strategies, as well as methods of using data collected by the debug logic to facilitate fast and efficient debug.

Performing verification on real silicon introduces a number of new and unique challenges. On the one hand, real silicon offers great execution speed, which enables a long test run that reaches deep into the design’s state-space. On the other hand, real silicon lacks both good controllability and observability, which serve an important role in pre-silicon verification. Assertions, which have always been one of my passions, have been shown to address both the controllability and observability challenges associated pre-silicon verification (for example, RTL simulation). And now, there is emerging interest in addressing these same challenges in post-silicon validation.

I’d like to invite you to check out my Tech Design Forum article titled Synthesizing assertion into hardware for faster debug.   Obviously, synthesizing hardware assertions is only one of many new solutions that are currently being explored to contain the growing cost and effort associated with post-silicon debug. One attractive benefit of assertion-based techniques is that they provide a nice natural link between pre-silicon verification and post-silicon validation, in terms of reuse.

I’d like to hear your opinions concerning synthesizing hardware assertions, as well as post-silicon debugging challenges in general.

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26 July, 2012

A system-level verification engineer once told me that his company consumes over 50% of its emulation capacity debugging failures. According to him there was just no way around consuming emulators while debugging their SoC design emulation runs. In fact when failures occur during emulation, verification engineers often turn to live debugging with JTAG interfaces to the Design Under Test. This enables one engineer to debug one problem at a time, while consuming expensive emulation capacity for extended periods of time. After all, when some of the intricate interactions between system software and design hardware fail, it can take days if not weeks to debug. To say this is painful, slow, and expensive would be an understatement.

Would you be interested to learn about a better alternative for debugging SoC emulation runs? Veloce Codelink offers instant replay capability for emulation. This allows multiple engineers to debug multiple problems at the same time, without consuming any emulation capacity, leaving the emulators to be used where they’re most needed – running more regression tests. And Veloce Codelink is non-invasive – no additional clock cycles needed to extract emulation data.

If you consume as much time debugging emulation failures as the system-level verification engineer above, Veloce Codelink could double your emulation capacity, too. To learn more about Veloce Codelink’s “virtual emulation” that enables “DVR” control of emulation runs, check out our On-Demand Web Seminar titled “Off-line Debug of Multi-Core SoCs with Veloce Emulation“. In this web seminar you’ll also learn about Veloce Codelink’s “flight data recording” technology that enables long emulation runs to be debugged, without requiring huge amount of memory to store all of the data.

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20 July, 2012

Live & In-Person at DAC 2012!

DAC 2012 4Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year.  Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.

The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design.  The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well.  A whole host of educational modules and seminars can also be found there too.

If you know about the Verification Academy, you know all about  the content mentioned above and that there is much more to be found there.  For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum.  (Flash is required to watch Harry discuss Verification Academy with Luke.)

The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends.  Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations.  While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations.  Verification Academy “Total Access” members now have access to many of the presentations.






Thales Alenia Space


Test & Verification Solutions


Willamette HDL


Sunburst Design


Mentor Graphics

Total Access members can also download all the presentations in a .zip file.  Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.

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16 July, 2012

Open-Source Proof-of-Concept Library Released

Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion to the recently minted IEEE Std. 1666™-2011, SystemC Language Reference Manual standard

In November 2011, the IEEE Standards Association approved IEEE Std. 1666-2011.  The completed and published standard was made available to the community as a whole for free in an agreement between Accellera Systems Initiative and the IEEE Standards Association in February 2012.   As a reminder, you can download your personal copy of IEEE 1666 here for free.

IEEE 1666-2011In the nearly 6 months since this version of the standard has been available about 7,000 copies have been downloaded under the IEEE Get program.

The previous version was also made available for free download and was just as popular as this version of the standard is.

1666-2011_Page_001While the approved standard was being made ready for publication, Accellera Systems Initiative was also busy completing the open-source proof-of-concept library.  After taking comments and feedback from a public review process, version 2.3.0 of the library was completed and is now available.

IEEE 1666-2011 added a number of important new features, including support for transaction-level modeling (TLM) that has proven to be an important element to enable high-level design and is a key component upon which the Universal Verification Methodology (UVM) is built from.

For those who want to used the SystemC library directly, it is now available for wide industry access.

Download Resources

The downloads from the IEEE and Accellera Systems Initiative will require some license agreement approvals.  The links are not one-click access to the material below.

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12 July, 2012

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)

For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency.  Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification goals.  Collecting information on how each tool adds to verification closure and sharing this information for ever larger designs among different tools has become a daunting challenge.

As a precursor to addressing this from a standardization point of view, many companies built their own way of collecting and sharing this information.  Users recognized the need for a standard and market participants responded.  For Mentor Graphics part, we developed and deployed the Unified Coverage Database (UCDB) technology for our verification products several years back.  Via our Questa Vanguard Partnership program, many partners have integrated into the UCDB to help drive further verification efficiency and productivity for mutual customers.

Yet, users were still left with the challenge to use the emerging coverage database technologies from multiple vendors.  Those users sought a solution to this dilemma from Accellera.  After users completed a requirements document that outlined their needs, we at Mentor Graphics noted that our UCDB technology offered a good match.  We offered to seed the standards development with our tested technology, as did other suppliers.  In the end and with extensions from consultations with other suppliers, an updated UCDB Application Programming Interface (API) specification from Mentor Graphics formed the basis from which Accellera created the UCIS API standard.

UCIS CoverpageIn July 2008 we announced the Mentor Graphics technology donation to this Accellera standards effort.  And on the day Accellera announced completion and availability of the standard at DAC 2012, Mentor Graphics was the first to announce product support.

To read more about support of UCIS and how it plays a critical role in verification, you may wish to read the article in the DAC issue of Verification Horizons.

The UCIS co-chair, Dr. Richard Ho from D.E. Shaw Research presented a comprehensive overview of UCIS at DAC.  Dr. Ho along with his co-chair, Dr. Ambar Sarkar of Paradigm Works, Inc. also presented a tutorial at DVCon 2012 titled An Introduction to the Unified Coverage Interoperability Standard.  The tutorial is available online.  Accellera does require registration for the tutorial.  The DVCon 2012 website on the UCIS tutorial goes into detail about what is covered in this 1 hour presentation.

I highly recommend you register and watch the DVCon 2012 tutorial for a good overview of UCIS.  You can also download, for free and without registration, your copy of the Unified Coverage Interoperability Standard here.  It makes a good companion for the tutorial.

What will you do with UCIS?

After reading the standard and watching the tutorial you should have a solid understanding of the importance it plays to reach coverage closure.  You will learn how you can create applications to improve your own verification productivity and efficiency.  Do you want to share the applications you write?  The new UCIS forum and contribution area was created just for this purpose by Accellera.  Please visit the site, register and contribute.

As more users begin to adopt UCIS, I envision this site will provide a good site for users to share applications.

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9 July, 2012

Hi Everyone,

Just wanted to make sure you’re aware of our next Recipe of the Month online Web Seminar: Scoreboards and Results Predictors in UVM on Thursday, July 12 at 9am PDT. You can register for the seminar here. This will be the ninth seminar in our ongoing Recipe of the Month seminar (see the full list here) and the reviews have been universally positive.

This particular seminar will outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

Overview: If verification is the art of determining that your design works correctly under all specified conditions, then it is imperative that we are able to create an environment that can tell you if this is truly the case. Scoreboards are verification components that determine that the DUT is working correctly, including ensuring that the DUT properly handles all stimuli it receives. Predictors are components that represent a “golden” model of all or part of the DUT that generate an expected response against which the scoreboard can compare the actual response of the DUT.

Hope to “see” you on Thursday.


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