Dave Rich Featured on EEWeb
I’m sure many of you know my colleague, Dave Rich. I’ve known Dave since our days at Co-Design Automation when we worked together defining the Superlog language, which eventually became SystemVerilog after being donated to Accellera. Hard to believe that was 11 years ago. Having gotten to know Dave as a friend as well as a colleague over that time, I really enjoyed learning even more about him in his recent interview as the Featured Engineer on EEWeb.
It’s been a great source of pride, both personal and professional, to be able to say that I’ve worked for over 10 years with the person who probably knows more about SystemVerilog than anyone else on the planet. Back when I was working on the IEEE 1364 Verilog standard, whenever there was confusion about spec, we always used to say “what does Verilog-XL do?” With SystemVerilog, whenever there’s a question about the spec, I just ask Dave (and you should too).
- IEEE-SA EDA & IP Interoperability Symposium
- Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification
- Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker
- Ready for a Verification Extravaganza in the Land of Verification Engineers?
- Conclusion: The 2014 Wilson Research Group Functional Verification Study
- How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 2 of 2
- Part 12: The 2014 Wilson Research Group Functional Verification Study
- Beating Design Complexity with VirtuaLAB
- Part 11: The 2014 Wilson Research Group Functional Verification Study
- How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 1 of 2