Archive for February, 2012

26 February, 2012

The philosophy behind our Verification Academy is to provide a comprehensive resource for evolving and maturing your functional verification process skills. We believe that each step an organization takes in evolving verification skills should have measurable results and benefits. With that in mind, I am excited to announce two new modules we are adding to the Verification Academy: UVM Express and Advanced UVM.

Figure 1. Screen shot for the Verification Academy UVM Epxress module.

For some verification teams, the hurdle to implement a UVM-based verification environment is simply getting started. To eliminate this hurdle, Mentor Graphics has just introduced UVM Express, which is a suggested systematic way to progressively adopt a UVM methodology. The beauty of this approach is that UVM Express makes getting started easy and intuitive, and provides measurable productivity gains to a broader scope of design projects, regardless of their past experience and existing skills with UVM. 

Our new UVM Express module consists of four sessions for evolving UVM capability.  It is not necessary for a project to implement all the recommendations from the four sessions to receive measurable benefits. For example, a project might decide to only adopt the recommendations presented in the first session in the UVM Express module, and then at some future point, decide to evolve their skills further by adopting the recommendations from the second session.

In addition to the UVM Express module, we have released an Advanced UVM module.  This module consists of 10 sessions and provides over three hours of material.  In this module, we build on the concepts originally covered in our Basic UVM Module to take your UVM understanding to the next level. You will learn how to build tests and verification environments, use the factory and configuration database to customize your verification IP, and create reusable stimulus sequences, including those for multi-layer protocols. We will also introduce the UVM Register layer, showing you how to create a register model and how to write and reuse register-level tests.

We are excited to now offer you three UVM modules within the Verification Academy: Basic UVM, Advanced UVM, and UVM Express. And as always, I welcome your feedback and suggestions.

For more information, visit


24 February, 2012

Advanced verification techniques including functional coverage and constrained random stimulus generation have proven themselves invaluable in the design of the smallest FPGAs to the largest SoCs today. Still many design and verification teams that need to and are willing to embrace these technologies have yet to do so. Verification environments written with basic hardware description languages like Verilog and VHDL, as well as home grown environments patched together with C, Tcl, or PERL scripts are entrenched and difficult to move away from. Adopting these new techniques requires training on several fronts. You need to learn the SystemVerilog language along with Object-Oriented programming skills. And to make your verification environments reusable and interchangeable with Verification IP (VIP) that you may want to get from outside sources, you need to learn the Universal Verification Methodology (UVM).

Or do you?

Maybe you can get started by using the minimal amount of things to get started. But how can you know what you need to know when there is so much to learn? That’s where the UVM Express comes in.

The UVM Express is a carefully planned path with a few key steps along the way to get you up and running. You learn just the things you need to be more productive at each step and advance at your own pace. There’s no need to digest everything at once to get up and running. The UVM Express path has four key steps:

Step #1 Organize your Testbench into a BFM

  • Use a SystemVerilog Interface to group your Signals
  • Write your test in terms of transactions
  • Call tasks to execute transactions

Step #2 Add Functional Coverage

  • Use Metrics to check Verification quality- How good are your tests?
  • Add coverage agents
  • Leverage pre-built VIP in passive mode

Step #3 Add Constrained Random Stimulus

  • Improve your test quality by generating stimulus efficiently
  • Leverage pre-built VIP in active mode

Step #4 Use the full power of the UVM

  • Modify your environment to improve reusability and configurability
  • Leverage all your code from the previous steps

The UVM Express adds to the many guides and examples in the UVM/OVM Online Methodology Cookbook on the Verification Academy. There is also a new UVM Express module that provides a multi-media walk through each of the steps. You can discuss this with me at next week’s DVCon 2012.

, , ,

22 February, 2012

In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this topic at our last face-to-face with the VIP-TSC.  With demand coming from our users, and some positive feedback on our proposal, we have just released UVM Connect, an open-source library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).


You can find much more information on the UVM Connect page of Verification Academy.

Mentor has always believed that SystemVerilog and SystemC each have their own strengths and that the most productive way to combine them in a system-level environment is to preserve the strengths of each while allowing the free exchange of data between them. Instead of trying to re-implement UVM in SystemC, or to extend SystemC to try and recreate SystemVerilog functional coverage or constrained-random stimulus, UVM Connect provides the framework needed to interoperate between languages. This lets you:

  • Reuse your SystemC architectural models as reference models in UVM verification
  • Reuse your stimulus generation agents in SystemVerilog to verify models in SystemC
  • Have access to a wider array of VIP since you are no longer confined to a single language
  • Utilize and interact with the UVM infrastructure from SystemC, including wait for and control UVM phase transitions, set and get configuration, issue UVM-style reports, set factory type and instance overrides, and more

UVM Connect provides object-based data transfer across the language boundary via TLM1 and TLM2 interfaces, which are natively supported in both languages. It works out-of-the-box with UVM 1.1a and later and lets you use your existing TLM models, regardless of language, in a mixed-language context without modification. In a nutshell, UVM Connect fulfills the principles and purpose of the TLM interface standard, letting you design independent models that communicate without directly referring to each other. The models thus work equally well in both native and mixed-language environments.I encourage you to download the kit and give it a try. In the spirit of “co-op-etition” I also encourage our competitors to qualify the library on their simulators.

In addition to the great material in the UVM/OVM Online Methodology Cookbook on Verification Academy, the kit also includes an HTML User’s Guide, based on extensive, well-documented examples, that includes detailed information on all aspects of the API. Please make sure to stop by the Mentor booth at DVCon and let us know what you think.

, , , , , , , ,

21 February, 2012

Is my car trying to tell me something?

This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA).  (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology – demonstrated by a standing room only training event – has got to be a tipping point indication for iTBA.

I turned my car on.  (Actually, I “pushed” it on as there is no place to put a key to turn anymore.)

Tornado-bp2Moments after starting my car a winter storm alert interrupted the music on the radio and displayed two notices.  One I am familiar with when the temperature falls and snow begins to collect on the mountain passes.  I’m not going to drive in the direction of the snow, so no problem.  The other alert was of grave concern.  It was a tornado watch.  And the tornado watch was not off in some other direction many miles away, it was “0 miles” from me.  I looked up, I scanned the horizon and dark black was in one direction and sun in the other.  I changed the radio channel to a local AM evening drive station, but no mention of a tornado watch.  I headed in the direction of the sun.  It seemed the safest direction to head.  But before I did, I snapped a quick picture as proof I actually read “Tornado Watch” on the car’s navigation screen.

iTBA to the Rescue?

I returned to ponder if functional verification has just gotten too big for current techniques that iTBA is going from a nice to have, to a must have.

Several years back it was popular to brag about the compute farms & ranches one had.  With 5,000 machines here and another 5,000 machines there it seemed a sane demonstration of one’s design and verification prowess.  But this gave way to 50,000 multicore machines and who is talking about this with pride?  All talk is out of necessity.  And what about the next step?  Who has 500,000 or 5,000,000 on the drawing board or in their data centers?  Looking around, it seems very few admit to more than 100,000 and even fewer have more than 500,000.

Verification may be in crisis, as many will say, but it you hold verification technology constant, it is not in crisis, is on a  collision coarse with disaster.  Addressing this crisis has been the theme of many of Mentor Graphics CEO Wally Rhines’ keynotes at DVCon.  His 2011 keynote was taken to heart by many who attended.  The need to improve by a several orders of magnitude the “Velocity of Verification” has been followed by several examples over the year.

One example was shared several months after DVCon when Mentor Graphics and TSMC announced we had partnered to validate advanced functional verification technology.  While not all test results at TSMC or our common customer, AppliedMicro, were revealed, one of the slower tests demonstrated the value of iTBA to shorten time-to-coverage by over 100x.  Even days after that announcement we disclosed Mentor’s Veloce emulation platform offered 400x OVM/UVM driven verification improvement.

100x  and 400x seem like a large numbers, but it appears even bigger when you put it into the context of the time it was measured.  With current constrained random techniques, a project that takes 6 weeks of simulator run time to reach 100% closure can reach it in about 10 hours with Questa inFact or about 2.5 hours with Veloce.  Instead of using complex scripts to peek in on a simulation run over the course of a month and a half, a verification team could actually leave work for the day, return the next morning and have a full, complete and exhaustive verification run.  And when even faster turnaround time is needed, emulation returns results during the work day.

SoC Verification: A Balance of simulation, iTBA & emulation

Wally’s DVCon 2011 keynote referenced 8 customer results coming from Mentor’s Questa inFact tool.  Many more have discovered what this can do for them as well.  And with each success, come the requests from more to see what it can do for them.

But changing the “Velocity of  SoC Verification” has not rested on one technique alone.  Stop by the Mentor Graphics DVCon booth and we can share with you the advances we have made to address system-level verification since last year.

Crossing The Chasm

Which brings me to the point of the “Tornado Watch.”  As I pondered the iTBA tipping point, about “how little things can make big differences” as can be found in Malcolm Gladwell’s book, my car must have been channeling Geoffrey Moore of  “Crossing The Chasm” fame instead.  For that reason it must have issued the Tornado Watch.  Could it be that iTBA is set to cross the chasm from early adopters to the early majority?

And thankfully, I don’t think my car is programmed to issue tipping point warnings, nor do I want to see if it can.

In the end, it will be with the benefit of hindsight that let’s us know if we are crossing the chasm into the tornado or not now or soon.  But for Mentor’s part, full and advanced support of iTBA technology with Questa inFact is ready now, and we are set to cross the chasm into the tornado.   My colleague, Mark Olen, blogs about iTBA here.   If you have not had a chance yet to read his blog on iTBA delivering 10x to 100x faster functional verification, it is worth the time to do so.  You can look for him to give frequent updates on iTBA and comment on the positive impact is has on SoC design and verification teams in the months ahead.

I look forward to seeing you at DVCon.

, , , , , , , , ,

17 February, 2012

It is time to talk about what happens next with UVM

uvm 2The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference organizers had to rearrange the room layout to accommodate a greater than expected number of registrant.  It is clear how important the topic of verification is and UVM in particular has become.

It seems to me that DVCon is the right place to discuss what comes next with UVM.  I have three thoughts about UVM that I think merit discussion.

1. UVM needs a period of stability

While the experts at the Accellera Verification IP Technical Subcommittee (VIP-TSC) standardization table (all good people) continue to hone UVM and debate a few more features they need, they have been unable to make significant progress on those features since last DVCon.  The one major item promised beyond OVM, an update to phasing, remains an open topic.  Mentor has suggested in committee that we allow another year to pass and suspend committee action on this.  Maybe the natural market forces would allow several options to surface, be user-tested and then merit consideration by the VIP-TSC.

This is in keeping with Karen Bartleson’s 9th Commandment for Effective Standards: “Start with Donations; Not From Scratch.”  This is what is happening now with Phasing.  The design by committee process is moving slowly.  It is not the slow part that concerns me, however.

Completing the “last” thing has many in the verification community waiting until it is done before they migrate and adopt UVM.  The best thing the committee could do to encourage use is to give the users certainty that UVM will not change in the next 12 months.  At the same time, the committee could commit to take input from users at the end of those 12 months as a guide to what it does next.

2. UVM needs a simple path to first use

Accellera has an approved and published standard, an open-source implementation and embedded UVM User’s Guide.  This is a lot to digest.  And while one may expect the User’s Guide to help, it calls the reader to supplement it with “education, experience and professional judgment.”  It warns that “not all aspects of this guide may be applicable in all circumstances.”

Users should be offered an unambiguous, easy-to-use and understand means to adopt UVM without having to know everything about it before starting to use it.  UVM was not made for just those who have large verification teams and central CAD groups.  Those large teams are the ones who are already using UVM.  The first step to UVM adoption for the rest of the world should not be too high as it currently is.

UVM needs a simple path for fast adoption.

3. UVM needs to bridge the system domain

Accellera System Initiative has come to life from the unification of Accellera and OSCI.  While the vision to bring the two organizations together is without fault, the lack of a publicly visible plan to leverage each others strengths is noted by Gabe Moretti in his recent blog on DVCon when he wrote: “First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.”  His comment was in response to the questions to be asked at DVCon’s Monday lunch about what the new organization should look like.  Gabe certainly thought “the creators of the organization must have some ideas of the focus, mission and goals.”

I certainly do.  In the case of UVM, I think it needs a bridge between the SystemVerilog world in which it was written and the SystemC world of design and modeling.  As teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models has become an imperative.

It is no secret to the Accellera VIP-TSC that Mentor Graphics thinks this is needed.  Our presentation to committee members on a UVM API to facilitate this outlines exactly what we think should be done to address reusable functional models in the system world.  [Accellera requires registration to download the Mentor presentation.  Accellera members can register here.  Guests require VIP-TSC leadership permission and can request it here.]

UVM must grow and bridge the system world.  The Accellera SystemC Verification Working Group (VWG) knows this.  They have a meeting planned at the DATE conference to discuss future evolutions related to SystemC and Verification on 14 March 2012 from 1230-1340 in Conference Room 4 which I plan to attend.  The VWG meeting is open to external participants, not just Accellera members.


I don’t know what your thoughts about what should happen next with UVM are.  Feel free to share them here if you wish or join me at DVCon or DATE and we can discuss it with the whole community.  Maybe there is hope we can make progress on these three areas in the coming year.

, , , , , ,

15 February, 2012

“Ready, Set, Deploy”

Accellera DayThe last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification Methodology (UVM) is ready for design and verification teams to adopt. This theme started with a whitepaper from Accellera I authored with two of my peers, Stan Krolikoski from Cadence Design Systems and Yatin Trivedi from Synopsys. A day long UVM tutorial will be featured during “Accellera Day” at DVCon with the same ready, set, deploy theme. The UVM tutorial is timely as I have seen UVM gain traction as OVM users transition at the end of their projects and those who have yet to adopt a standardized methodology have likewise begun their adoption.

uvm 2The UVM tutorial starts with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. A section on the UVM register package will show how to create and manage stimulus and checking at the register level. Several expert users will show how this fits together in a complex SoC verification environment and relate lessons learned in preparing the transition to UVM, architecting reusable testbenches, debut techniques and use of the TLM 2.0 in real verification environment.

The tutorial will be presented by expert verification methodology architects and engineers as shown below:

Speakers: Tom Fitzpatrick Mentor Graphics Corp.
  Kathleen Meade Cadence Design Systems, Inc.
  Adiel Khan Synopsys, Inc.
  Stephen D’Onofrio Paradigm Works, Inc.
  John Aynsley Doulos
  Mark Strickland Cisco Systems, Inc.
  Vanessa Cooper Verilab, Inc.
  John Fowler Advanced Micro Devices, Inc.
  Peter J. D’Antonio The MITRE Corp.
  Justin Refice Advanced Micro Devices, Inc.

Conference attendees may choose this tutorial or if you wish to attend the tutorial only, DVCon charges a modest fee ($75.00). You can register here for the day long UVM tutorial.

More UVM News

With 33 exhibitors at DVCon and the heavy functional verification content, what other venue could deliver the potential of breaking UVM news? I invite you to stop by the Mentor Graphics booth were we can share with you the latest in support of UVM. You will find us at booth 801.

I look forward to seeing everyone at DVCon!

, , , ,

@dennisbrophy tweets

Follow dennisbrophy

@dave_59 tweets

Follow dave_59

@jhupcey tweets

  • #ARM now hiring formal verification engineers in Austin: exciting tech challenge + Ram is a great guy to work with.…
  • Attention all SF Bay Area formal practitioners: next week Wednesday 7/26 on Mentor's Fremont campus the Verificatio…
  • This is a very hands-on, creative role for a verification expert -- join us!

Follow jhupcey