Latest posts

User2User

Closing the Gap in Software Skills for Verification Engineers

I’m excited to announce next month’s U2U (User-to-User) meeting, followed by a crucial technical training session that no hardware verification…

Accellera announces fee-free availability of IEEE Std. 1801™-2024

Accellera announced the latest revision of the IEEE Standard for Design and Verification of Low-Power Energy-Aware Electronic Systems, also known…

GOMACTech 2025 Preview: Improving Productivity with Parallel Simulation (Poster P.9)

Field Programmable Gate Arrays (FPGAs) continue to be a critical part of system designs, and their complexity grows as new…

GOMACTech 2025 Preview: FPGA Safety and Security Policy Compliance via HDL-to-Bitstream Equivalence Checking (Session 43.5)

Security and safety policies across domains such as embedded security, defense safety, and automotive safety have been updated to require…

Backpacking Yosemite Aug 2024

Got Coverage?

Welcome to 2025. What happened?! “Coverage” in August in Yosemite backpacking has a different meaning. In August? Snow? Lots of…

DVCon 2025: A must for hardware design and verification engineers

I’ve attended every DVCon US conference since its inception, over 30 years ago. I’ve also given keynotes at DVCon India….

Siemens at DVCon 2025: Don’t Miss the Luncheon and More!

The latest trends in verification are in—and they’re more than just surprising. They’re alarming. Join Siemens EDA at DVCon 2025 for an exclusive luncheon…

Update from the Standards World: Accellera Approves UVM-MS 1.0 Standard

Accellera Systems Initiative approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard.  This milestone marks a significant advancement in…

Breaking the Bottleneck: A Smarter Approach to Semiconductor Verification

The semiconductor industry is facing a new reality: traditional verification methods can no longer keep pace with the rapid evolution…