December Verification Horizons Issue Out
Just wanted to let you know that the latest issue of Verification Horizons is now out. You can find it here. Aside from learning about the extent (or lack thereof) of my carpentry skills (read the Editor’s Letter to see what I’m talking about), you’ll also see these interesting articles:
Page 6… Evolving Your Organization’s ABV Capabilities
by Harry Foster, Chief Verification Scientist, DVT Mentor Graphics
Page 10… Advanced Static Verification is Indispensible
by Ping Yeung Ph.D., DVT Mentor Graphics
Page 14… Evolving the Coverage-Driven Verification Flow
by Matthew Ballance, Technical Marketing, SLE Division, Mentor Graphics
Page 17… Verification of an Ethernet PHY DUT Using Questa MVC
by Pankaj Goel, Mentor Graphics
Page 22… Breaking Your Own Code; A Design Engineer’s Perspective
on Verification Using Questa and OVM.
by Leeja Mathew, Mahasweta Das, Reshma Shetty; Silicon Interfaces
Page 26… SystemVerilog FrameWorks™ Scoreboard: An Open Source
Implementation Using OVM.
by Dr. Ambar Sarkar, Chief Verification Technologist, Paradigm Works Inc.
Page 31… SEmulation: Use Your Emulation Board as a Hardware Accelerator for ModelSim SE.
by Andreas Schwarztrauber, Gleichmann & Co. Electronics GmbH
Page 35… Coding Concise SystemVerilog Assertions.
by Clifford E. Cummings, Sunburst Design, Inc.
Page 41… Methodology for Board Level Functional Simulation and Hardware/Software Co-Verification Using Seamless.
by John Gryba, Senior Hardware Design Engineer, Alcatel-Lucent
Go check it out and let us know what you think.
- IEEE-SA EDA & IP Interoperability Symposium
- Back to School: How to Educate Yourself and Your Colleagues About Formal and CDC Verification
- Mentor Announces Joint Portable Stimulus Contribution with Cadence, Breker
- Ready for a Verification Extravaganza in the Land of Verification Engineers?
- Conclusion: The 2014 Wilson Research Group Functional Verification Study
- How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 2 of 2
- Part 12: The 2014 Wilson Research Group Functional Verification Study
- Beating Design Complexity with VirtuaLAB
- Part 11: The 2014 Wilson Research Group Functional Verification Study
- How Formal Techniques Can Keep Hackers from Driving You into a Ditch, Part 1 of 2