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PCB Design Perfection Starts in the CAD Library – Part 3

Molded Body Components

The next most popular component family on a PCB design layout is the Molded Body Tantalum Capacitor (CAPM). The CAPM components have an “L-Bend” component lead form. Most Molded Body Tantalum Capacitors are metric by default including their standard EIA names –

  • 3216 – 3.2 mm X 1.6 mm
  • 6032 – 6.0 mm X 3.2 mm
  • 7243 – 7.2 mm X 4.3 mm
  • 7343 – 7.3 mm X 4.3 mm

The common component families that use the Molded Body package are –

  • Non-polarized Capacitors
  • Polarized Capacitors
  • Diodes
  • Resistors
  • Inductors
  • Fuses
  • LED’s

See Figure 15 for the 6032 component and land pattern dimensions. I broke 1 rule to create this land pattern. Instead of a 1.0 mm Land Placement Round-off I used a 2.0 mm Land Placement Round-off to snap the land centers on a 0.5 mm grid from the center of the land pattern. When the land pattern is placed on a 0.5 mm grid, the land centers fall on a 0.5 mm grid. This improves the via fanout seen in Figure 17.



Figure 16 illustrates the silkscreen and placement courtyard rules and sizes. The illustration shows the component leads on top of the land for graphic representation.



Figure 17 illustrates the via fanout for a 6032 Tantalum Capacitor. If you are going to use the same size via to maintain trace/space compatibility with the rest of the PCB layout I recommend at least two vias. The placement of these vias is critical in accomplish reduced impedance and increased capacitance. It’s important that the vias be placed as close as possible to the capacitor terminal leads. In Figure 17, the 2 vias coming out the side are 0.15 mm away from the terminal lead. The vias coming out the ends on the land pattern are 0.75 mm away from the terminal leads. That’s 5 times farther away than the vias coming out the sides however some EE engineers will request all 4 vias. Since all the traces and vias are snapped to a 0.5 mm grid, this makes copy/paste much easier to manually fanout all of the 6032 Molded Body Capacitors. The dot grid display is 1 mm and the land pattern is placed on a 0.5 mm grid. All the vias in this illustration fall on a 1 mm snap grid.



See Figure 18 for the 7343 Molded Body Tantalum Capacitor I recommend a larger via size with a 1 mm land size, 0.55 mm hole size and 1.3 mm plane anti-pad. This via can carry more current and you only need two (but the EE will ask for a 3rd one). The illustration in Figure 16 snaps all the vias to a 1 mm grid system. These vias are twice the size of the previous vias but all the same trace/space rules apply. The display grid is 1 mm.

Because the land pattern, traces and the vias are on a 1 mm snap grid, this improves the copy/paste feature for manual fanout of all of the 7343 Molded Body components in your PCB layout.




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Posted October 1st, 2010, by

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5 comments on this post | ↓ Add Your Own

Commented on October 21, 2010 at 12:06 am
By anil chavan

Does multiple and larger vias affect soldering?

Commented on October 21, 2010 at 8:12 am
By Tom Hausherr

The GND & PWR vias have a direct plane connection (no thermal pattern in the via hole). The Thermal Relief in this fanout is the trace between the Land and the via. So you can have as many vias as you want but the total sum of the trace widths + via hole diameters connecting the Land and vias should not exceed 60% of the land diameter. This is noted in the IPC-2221 and 2222 documents that the total “spoke widths” should not exceed 60% of a hole diameter for a through-hole lead to prevent a cold solder joint. So be careful that you do not use multiple vias with wide trace widths. My recommendation is 2 vias on bulk tantalum capacitors. I show 3 vias in the picture to illustrate the preferred via locations and my preference is the 2 vias that come out of the sides of the land pattern because they are closer to the component leads. I do not recommend the vias that come out of the ends of the land pattern because they are further away from the component leads. The closer the via is to the component lead, the greater the capacitance and reduced inductance. This via location tip only applies to bypass decoupling capacitors and discrete parts that are attached to the planes. I also prefer trace widths that are the same width as the via diameter. A 1.0 mm via diameter would have a 1 mm trace width. The picture shows a 1 mm via with a 0.5 mm trace width.

Commented on January 19, 2011 at 10:10 am
By Penn Linder

For a square land, what would you consider the “diameter” for calculating the 60% maximum spoke width?

Do the two vias on the sides come out enough to leave a solder web between the via and the pad? If there were no solder mask between the via and the pad, would solder migration be a concern?

Commented on January 19, 2011 at 11:00 am
By Tom Hausherr

There are no rules for calculating spoke width for SMD Lands. The 60% rule is in relation to the “Hole Diameter”.

All vias, on the same layer as the components, should be “tented” with solder mask. If there are only components on the Top Layer then only the top Layer vias need to be Tented. If there are components on both sides then both sides should have tented vias.

The vias coming out the “side” (rather than top and bottom) of a Chip Capacitor is to get the via as close to the component lead as possible to increase capacitance and decrease impedance. Ultimately, via-in-pad under the component lead will result in the best performance for High Speed and increase component packing density. With “Bottom Only” component leads (like all the Grid Array” LGA, BGA, CGA) and fine pitch will drive via-in-pad to become more popular. The fact is that if you put via-in-pad on one part, you might as well do it on all parts because the fabrication cost does not change. i.e.: once you start to use via-in-pad the fabrication cost automatically goes up, but it does not increase with the volume of via-in-pads (unless you exceed several thousand holes). Each manufacturer is different.

Commented on February 22, 2012 at 8:31 am
By Sea

Excellent step by step post sir. I still fail many times to use the dgsien library as I should. Need a large flashing neon sign next to the monitor to remind me use it.

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