TSMC’s DFM Announcement
If you are a TSMC customer, no doubt you have heard that TSMC has announced that for 45nm (and presumably beyond), LPC and VCMP are mandatory for block/chip. What does this mean? It means that TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
So, what’s really behind this? TSMC isn’t generally known for making things easy for EDA vendors. Why make a new step mandatory like DRC is? Is it because they’re having real yield issues at 45nm, and they want the customers to find and fix issues themselves? Possibly. Is it because the DFM tools are finally mature enough to be a required part of the flow? Well, maybe they are, but that’s probably not the reason.
I think it has to do with money. As they say, “Follow the money.” Having low-yielding parts in the fab doesn’t do anybody any good. Most TSMC customers buy wafers at a pre-negotiated price. If the part yields poorly, the customer will likely have to buy more wafers to make up the volume, and will try to renegotiate the price. How is it bad for TSMC if they buy more wafers? Because that makes TSMC’s production starts more unpredictable. A small company with one product could go out of business if good die are costing them too much as a result of low yield. Orders from medium-sized companies could fluctuate wildly. That would really make things unpredictable for TSMC. Low yield would also hurt TSMC’s reputation. They like being #1 in the foundry business. They like being thought of as the best. Having lots of customers complaining about price and yield puts that at risk. Not only that, but to resolve low yields, TSMC would have to devote more resources to these problem chips, which would cost them real money. Even worse, some large customers actually buy good die. Low yield for those customers would directly impact TSMC’s bottom line, as TSMC would have to make up the difference. Follow the money. Having happy customers who sell more product, make more money, and come back for more high-yielding wafers probably makes the most sense for TSMC. The trend seems to be to make the customers more responsible for DFM. Expect other foundries to follow suit.
So why can’t the foundry just write better rules to make sure that all designs yield well? Hmmmm….
- Why are 450mm wafers and EUV lithography related?
- TSMC 28nm yield (SemiWiki)
- DAC 2011 is upon us!
- You can’t give stuff away fast enough
- Critical Area Analysis and Memory Redundancy
- Economy must be improving
- TSMC loses some production time due to earthquake
- DAC: Veni, vidi, steti
- What do you mean by mandatory?
- So, why not just write better rules?