TSMC’s DFM Announcement

If you are a TSMC customer, no doubt you have heard that TSMC has announced that for 45nm (and presumably beyond), LPC and VCMP are mandatory for block/chip. What does this mean? It means that TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.

So, what’s really behind this? TSMC isn’t generally known for making things easy for EDA vendors. Why make a new step mandatory like DRC is? Is it because they’re having real yield issues at 45nm, and they want the customers to find and fix issues themselves? Possibly. Is it because the DFM tools are finally mature enough to be a required part of the flow? Well, maybe they are, but that’s probably not the reason.

I think it has to do with money. As they say, “Follow the money.” Having low-yielding parts in the fab doesn’t do anybody any good. Most TSMC customers buy wafers at a pre-negotiated price. If the part yields poorly, the customer will likely have to buy more wafers to make up the volume, and will try to renegotiate the price. How is it bad for TSMC if they buy more wafers? Because that makes TSMC’s production starts more unpredictable. A small company with one product could go out of business if good die are costing them too much as a result of low yield. Orders from medium-sized companies could fluctuate wildly. That would really make things unpredictable for TSMC. Low yield would also hurt TSMC’s reputation. They like being #1 in the foundry business. They like being thought of as the best. Having lots of customers complaining about price and yield puts that at risk. Not only that, but to resolve low yields, TSMC would have to devote more resources to these problem chips, which would cost them real money. Even worse, some large customers actually buy good die. Low yield for those customers would directly impact TSMC’s bottom line, as TSMC would have to make up the difference. Follow the money. Having happy customers who sell more product, make more money, and come back for more high-yielding wafers probably makes the most sense for TSMC. The trend seems to be to make the customers more responsible for DFM. Expect other foundries to follow suit.

So why can’t the foundry just write better rules to make sure that all designs yield well? Hmmmm….

— Simon

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Posted May 21st, 2009, by

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7 comments on this post | ↓ Add Your Own

Commented on May 27, 2009 at 1:27 pm
By Early Adopter

From first-hand experience, I would say that “mandatory” has some sizable wiggle room. To go along with your show-me-the-money hypothesis, I’d say that things get a lot less mandatory the bigger you are. Hard on the little guys as usual.

Commented on May 27, 2009 at 1:47 pm
By Simon Favre

I agree. I tend to think the big guys already have a DFM plan in play, but perhaps this surprised them a little. Smaller companies may have to scramble. They may have no choice but to pay TSMC for the service, because that’s the easiest way to amortize the cost on a per-project basis when they only have one chip to do. Larger companies may see it differently. On the one hand, design managers tend to have to be dragged kicking and screaming into having yet another sign-off tool in their critical path to tape-out. On the other hand, product engineers and CAD managers may see this as justification for engaging with DFM to benefit the long-term success of their products. If you take a long-term view, it’s probably a good thing, but hard on some in the short term. I wonder what the small design houses and IP vendors think?

Commented on May 28, 2009 at 12:34 am
By Small Design House

…small design houses will avoid 45nm unless they are forced to use 45nm for very clear technical reasons. The monetary gain with smaller chips is getting less and less obvious. Something gotta break sooner or later…

Commented on May 29, 2009 at 10:12 am
By littleguy

Any idea of the cost charged by TSMC for this DFM analysis service (rough number?)

Commented on May 29, 2009 at 11:11 am
By Simon Favre

I certainly can’t speak for TSMC design services. Besides, I’m an engineer. They don’t let me give answers with dollar signs attached. :=) But seriously, it depends. If you are designing at 45nm, but you only tape something out once or twice a year, maybe the service option is OK. There’s still a turnaround issue, tho. If you’re level of activity is higher, and you’re taping out at 45nm regularly, say 5 or 10 times a year, then you’re way better off acquiring the tools and doing it yourself. This is a normal build or buy proposition. You either build the infrastructure to do it in house, or you farm it out, depending on what makes the most business sense. Just make sure Management looks at all the variables, including the turnaround time of sending it out.

Even if you’re not at 45nm yet, but you know you will be before long, it might be a good plan to get into the DFM issues sooner even if you’re at 65nm. If you’re at 90nm or larger nodes, you have some time to think about it. Even though DFM is not mandatory at 65nm, companies that have already deployed DFM in their flow have found significant opportunities to improve their bottom line as a result.

— Simon

Commented on June 1, 2009 at 2:10 pm
By Silicon Veteran

Thanks Simon, for the insight. All semi companies (big and small) are just going to have “bite the bullet” to compete. DFM is the cost of admission. TSMC is the leader in sub 100nm masks and need the industry to adopt the methods to make the technology successful and accessible.

Commented on July 8, 2009 at 2:34 pm
By What do you mean by mandatory? « Simon’s DFM Corner

[…] seminar (06/25/09) for mutual customers to go over the new DFM requirements at 45/40 nm. (In my first post, I mused about the implications of making some DFM analysis steps mandatory.) When the […]

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