PCB Matters

Thoughts on PCB from our product experts at Mentor Graphics PCB

6 March, 2013

In an article published last September on the Huffington Post there was a claim that the United States is facing a serious STEM (Science, Technology, Engineering, and Mathematics) talent crises. The author pointed to a study by the US Department of Labor claiming that the STEM workforce accounts for 50% of economic growth while only 5% of the working population are employed in STEM fields. The article further pointed out that the STEM workforce is increasingly moving toward retirement with an insufficient pipeline of graduates to take up positions needed to drive an innovation-oriented economy. The Manpower group publishes an annual survey looking at the most difficult positions to fill and Engineering comes to near the top (number 2) in their 2012 survey.

Listening to colleagues who have children entering  college, I hear frequently that engineering enrollment is surprisingly low. I guess we can all point to a variety of factors as to why this phenomena exists. Are we not emphasizing science and math in our schools? Or, are we not inspired like earlier generations? (think of JFK’s investments in NASA and the drive to have a lunar landing within a decade). Have interfaces become too easy (think Apple and Google) that we take technology for granted and therefore aren’t driven to “tinker”? Do we have too many degree choices? I would guess the answer is a combination of reasons. But certainly, if there is an engineering talent crises in terms of pipeline, then this poses serious implications for the electronics industry.

We tend to talk about the implications of increasing design complexity and business pressures (like time-to-market) as a major factor in informing our organizational initiatives related to PCB development (and product development in general). But what about this additional vector, where we might actually be coping with a workforce that is more burdened due to a shrinking workforce?  Add the fact that we are also seeing a decline in the PCB designer population (see an article published in PCD&F last April) and we might have a “perfect storm” brewing.

If, in fact, we are seeing a possible demographic shift in our industry, then that will have implications on design strategies, how organizations drive innovation, and how business targets will be met. Obviously every challenge presents opportunities and some of the solutions will come from political and business leaders but also solutions will have to come from technology solution providers, like Mentor Graphics.

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19 October, 2012

In case you didn’t get the opportunity to go to PCB West 2012 in September, my favorite moment was the fabrication capability update from StreamLine circuits.  Overall, the crowd was already noticeably more upbeat and energetic than the last couple years.  But in a room of over a hundred nerds wearing jeans and button-down shirts, there were outbreaks of murmuring excitement when the latest board cross-sections were shown overhead.

We paused on the picture of a board with 1 mil trace thickness and 1 mil separation while plenty of questions came up about the whole fabrication process.  What caught my attention was that the new limiting factor is hole to different-net-copper, not traces or drill annular rings.  Starting with the assumption that you are using the latest equipment, and you run all types of boards through it to keep it busy, laser drilling and automated optical alignment become features you get without paying extra.  High-density-interconnect designed boards may now quote for less.  Using a couple of outer layers as build-up layers with blind and buried vias means a couple less plane layers in the whole stack-up, which saves money.  Yeah! I get to finally use HDI without looking extravagant.  The thinnest 4 layer board cross-section shown was 5.4 mils thick.  It is OK if you are as unabashedly tech-nerd as I and you just said “Wow.”

It was a great time and I recommend PCB West especially for the design sessions.  Hope to see you there next year.

HDI done in high vole

24 August, 2012

Welcome! I am Gary Lameris Technical Marketing Engineer for Mentor Graphics. I’ve worked with DxDesigner since 1988 and have watched it grow from the independent Unix/Dos tool called PowerView and Viewdraw to a powerful multi-user schematic drafting program tightly integrated into the Expedition Enterprise and PADS layout tools today.

Four years ago I moved to Colorado to join Mentor Graphics and the DxDesigner team as the product was transitioned from an obsolete file based drawing package to a revolutionary multi-user database tool unique in the industry for its vision and scope. From the day I interviewed and saw the prototype database software my excitement has not waned for this revolutionary approach to improving a design team’s performance in creating a design that is right the first time!

Today at Mentor Graphics we released DxDesigner 7.9.4 embedded in the Enterprise Expedition flow. Internally, the Marketing team has been excited with this release for months, and the feedback from our beta testers has been overwhelmingly positive! With this release you will notice many user enhancements including a new drawing canvas, new window management, increased use of color and text styles, better alignment algorithms and graphical rule checks. These new features will improve your productivity, simplify you’re your experience with this product and best of all create better looking and more accurate schematics! Best of all, these enhancements are only the start on our plans.

Gary Lameris
Mentor Graphics, Technical Marketing Engineer
Twitter @glameris – www.twitter.com/glameris

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17 February, 2012

The IPC Embedded Mailing list (EmbeddedNet@IPC.org) has been silent –some may claim stone dead for a very long time.

My article and subsequent blog posts claiming that there never was an Embedded Passive boom apparently provoked some and an intense discussion broke out on the mailing list where EP material vendors, IPC, EIA, EIC standardization committee members, PCB designers, board shops….argued that  the boom actually happened.

From where I stand, there was no boom –not the way we expected it anyway but perhaps there was at least a puff…

It all comes down to the “boom criteria” –and who decides those….
Should we go by what percentage of designs use EP?
Or maybe how many sq-ft of boards use EP compared to not use EP?
Maybe just the fact that a lot of EP materials are being shipped is enough to claim a boom?
…and is it fair to compare embedded capacitance planes and embedded resistors at the same time?

Clearly, EP’s mean different things to different people and success depends on how you define it and I would be the first to admit that in certain segments such as Medical, Automotive, Mil/Aero and SIP packaging, EP’s are pretty much mainstream technology today.  
Read more in my article in PCB Magazine. http://www.iconnect007.com/emag/pub/PCB-Nov2011/?page=66

Now, as I wrote in an earlier post, some of the business drivers for EP’s has lost their value. So, does it end here?

No way!

The  market drivers asking for cheaper, smaller, more speed are still there  -obviously!
…and if EP’s by themselves don’t meet those drivers you can take the embedding even further:  

Let’s embed everything!

Lately, cost effective and reliable processes that let you embed bare dies, SMD-components and EP’s in to a very thin laminate/build up substrates has become available.

Take a look at the presentations from the European HERMES project and the US EMAP-II project readily available on the web:
HERMES:  http://www.hermes-ect.net/
EMAP-II:  http://www.prc.gatech.edu/devm/research/consortia/emapII.shtml

or take a look at AT&S ECP process at http://ecp.ats.net/

In a few coming posts, I will talk more about this technology and why I think this technology will take off big time  even though traditional EP’s hasn’t  …and of course, discuss the design challenges involved. -Stay tuned!

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7 February, 2012

New technology is cool but… with most new processes there are risks to be managed. 
Usually new technologies promises/offers higher design performance, lower product costs and or faster design turn around but, failing to manage the risks can cause all the benefits to go down the drain. Embedded Passives are no exception –on the contrary, there are many pitfalls that can result in bad boards –expensive such, being delivered back to you from the board shop.

Now, risks are always part of life. –You can walk far to avoid them but that’s rarely the most efficient path.
Walt Disney once said:
I dream, I test my dreams against my beliefs, I dare to take risks, and I execute my vision to make those dreams come true.
Complete focus on the vision/goal and daring to take the risks that must be taken brought Mickey to the world. –Surely that must work in EDA too?

How do you prevent costly design disasters? You can design with EP’s on any layout tool. –just put the appropriate shapes on user layers – but I wouldn’t exactly call that “mitigating the risks.”  Still, many are designing with EP’s this way.
In Expedition PCB, you have a series of capabilities that guide you through the entire process from material and process planning to establishing if a design is suitable for embedding and which parts are best embedded and even generating the parametric components and place them on the PCB inner layers –all in a correct by design environment.

The image shows the EP planner tool that gives you a graphic representation of component values, number of components and suitable EP materials to help you establish which materials would cover which components and also calculate –before you even start the layout, the total size of these parts and their power rating.
Its not possible by just looking at a design to figure out if it is a suitable EP candidate or which parts to embed or even which materials that will yield a successful embedding. This little tool let you tradeoff between all these parameters. On top of this we have all the analysis tools for SI and PI to help you keep your designs within specs.

It’s all about enabling you to make use of new technologies that help you maintain -or gain,  a competitive edge –and at the same time mitigate the risks involved.  -There are always risks but properly managed you can walk the straight path.

More on Embedded Passives: Read my article in PCB Magazine: http://www.iconnect007.com/emag/pub/PCB-Nov2011/?page=66

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30 January, 2012

Do you remember the hype on EP’s (Embedded Passives) just a few years ago?

In the PCBD&F magazine, late in 2006, Kathy Nargi-Toth wrote in an Editorial to PCD&F referring to an industry survey:
The statistic that blew me away was the change in anticipated implementation of embedded passives.
The projections are that 24.6% of the PCBs, up 222% over current figures, will incorporate embedded components.  Are we on the brink of widespread acceptance? …”

While quite a few companies do use EP’s I’m sure we can agree that the boom indicated by the survey never happened!

Why is that?  This technology was very promising with all the right market drivers.

What happened was that development caught up with a few of the market drivers:


An embedded resistor is small but not that small. While companies developed technology demonstrator designs with EP’s, the component manufacturers kept reducing the size of the surface mounted components dramatically –and delivered parts with better tolerance than is achievable with EP’s without laser trimming. So, the size argument is gone.

Freeing outer layer board space:

While this one is still valid, smaller components makes it less critical. Interestingly, as the SMD parts are halved in size in every generation (sort of) the board surface they require doesn’t shrink at the same rate as we need some space for assembly machinery and the solder pads need to have certain sizes.

Still, if you really need to gain outer layer space, you can actually embed smaller SMD components in the PCB laminate.


OK, so here is one driver that still applies –big time! As signal speeds go up, it becomes critical to manage board and passive component parasitics. EP’s have extremely small parasitic effects as they can be placed right at the pin they support –for example in high speed termination of a multi gigabit SERDES channel.

Also, when used as an embedded capacitance plane to eliminate or reduce the number of decoupling capacitors you are typically able to reach a much better power distribution network performance than when using discrete decoupling.

So, while several of the market drivers are gone, this is not true for all markets  where  drivers remains valid and drives use of EP’s  in specific products.

For more information read my article in PCB Magazine: http://www.iconnect007.com/emag/pub/PCB-Nov2011/?page=66

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14 October, 2010

In this series of blogs, I’m going to focus on concurrent engineering and cover the following topics:

· What is concurrent engineering & why does it matter?

· Concurrent engineering in practice

· Collaborative concurrent engineering

So, let’s get started with the first question: what is it and why does it matter? Concurrent engineering involves the introduction of parallelism into the engineering process with the purpose of shortening the elapsed time to complete that process.

The parallelism could be applied to steps of the process or it could be applied to a step within the process. A simple example – I’m thinking of getting a set of snow tires for my car which will mean changing all of the wheels. If I do it myself, I will have to get the jack out, and in a serial process, raise each corner of the car, take off the wheel, put on the new wheel, lower the car and remove the jack. I’ll do this four times and I don’t know about you, but it would probably take me an hour. How could I accelerate this process?

I could press-gang my 2 teenage sons and unlucky wife and assuming I had four axle stands and four wrenches, I would still serially jack up each corner and insert the axle stand, but now the four of us could replace the wheels in parallel, then serially remove the axle stands. Here we are applying parallelism to the 4 individual steps of changing the wheels. With this approach, I reckon I could get the elapsed time down to 30 minutes. Notice, I didn’t get the time down to 15 minutes even while applying 4 people to the problem – the reason being that there is still some serial work going on here.

How could I get close to my 15 minute nirvana? By introducing some new technology – something that will jack up the car faster or that will jack up the whole car at once. In this way, we are able to leverage technology so that jacking the car is considered one step (effectively performing those 4 individual jacking steps in parallel). Some folks already figured this out – just take a look at this pit stop during a formula 1 race. 60 minutes down to 7 seconds – not bad!

I’ll delve into how concurrent engineering can be applied to PCB design in my next blog, and how technology can enable parallelism in ways that otherwise aren’t possible.

We have all experienced projects that were behind schedule. Perhaps you work in an industry where earlier to market means increased revenue and market share. Concurrent engineering provides “shortening of elapsed time” for the design process and this answers the second part of our question. In real life, the quicker we can complete a design the more competitive we will be.

I’ll also acknowledge that concurrent engineering does not necessarily mean fewer resources applied to the project. It does however support the efficient use of those resources. Here’s an actual example of this idea in action…

Fujitsu Technology Solutions makes computers and servers, so you can see why time to market would be so critical. In order to meet their schedules and time to market goals, Fujitsu was running night shifts so that designs could be worked on with a longer working day. Of course, there’s some inefficiency in the hand off of a design from one engineer to another, and there is the additional expense of paying night shift rates. Through the use of concurrent engineering, Fujitsu was able to eliminate the expensive night shifts and to apply those engineering resources during the normal day shift.

Why didn’t Fujitsu make this change sooner? Well, I’ll explain that in a later blog but suffice to say for now that concurrent engineering is not just about methodology but also about enabling design technology.

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15 June, 2010

In one of my first blog posts I wrote about PCB Designers being the “unsung heroes of innovation.” After spending a week in Israel and visiting PCB Fabricators and Assemblers, I am even more convinced of the complexity of the PCB Development process. The cycle of complexity is accelerating – we see this amongst our customers in our annual Technology Leadership Awards and we see this day in and day out in terms of the projects we are engaged in.

In my most recent post I talked about WHY PCB MATTERS – and referred to a study from Aberdeen regarding research they conducted. This research supports our assumption that PCB is a highly essential part of the overall product development process. One of the key research points from that study is that PCB’s make up to 31% of the overall costs of a product.

My observations from my visits this week make it easy to see why. Not only are technologies becoming more complex but also processes are increasing in complexity. Yet there is still lots of islands of activity that are not integrated. Mentor is trying to address both the technology complexity as well as the process complexity in multiple ways – such as through product development and through acquisitions, like we recently completed with Valor.

Getting back to the study, we figured our efforts should not stop there. We wanted to give the wider PCB community a chance to assess your practices against the wider samples/benchmarks from the Aberdeen study. So we partnered with Aberdeen in establishing a on-line assessment tool to give you a core understanding of  how your organizations stack up against the wider use-case samples. This assessment is not about Mentor solutions or about specific technologies, it’s about overall PCB development practices.

Take a look at our landing page – there we have a webinar by Michelle Boucher, a consultant from Aberdeen offering an overview of the study. You can also download the study itself. Lastly, you can take the online assessment and leverage the findings for your own organization as a point of discussion for possible areas of improvement.

The major intent of these efforts is mostly to raise the level of conversation around PCB. I think we too often get lost in the technology discussions and not enough in terms of extracting the business value of what we are doing.

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12 May, 2010

I called this blog area “PCB Matters” for a reason.

PCBs are like the Rodney Dangerfield’s of product development – they don’t get the respect they deserve. I think this is because there really is not a such thing as a singular PCB design task – but really a series of tasks with specialists where each speaks a unique language that’s hard to crossover. So what happens is that each specialist (RF designer, High Speed Engineer, Layout Designer, Process Engineering, etc.) all kind of stay in their own domains. So, it’s no surprise that PCBs do not get the kind of respect they deserve. It’s hard to decrypt what is happening at the PCB development level if you don’t come from the PCB world.

It’s a paradox. Because PCB’s are the bridge between the mechanical and electrical world. Fine-tuning the PCB development process can have a significant impact on a company’s bottom line. In an Aberdeen Study, PCBs are found to make up to 31% of the overall cost of a product. This presents significant opportunities for optimizing the product development process.

Proof that we don’t “speak the same language” is in this study. On page 11 of this study a question was asked and the answers were delineated by whether a manager or staff was answering. So, for example 84% of managers answered that “design for cost” is a key initiative whereas 64% of staff answered cost as being a core driver. On the other hand, 89% of staff identified “design for signal integrity” as being critical with 77% of management concurring.

So, although technology is critical (and Mentor has been investing accordingly – most recently with finalizing the acquisition of Valor), it is also a management issue. Putting the right tools in place is part of this challenge, driving the usage of those tools for success in enabling key business goals is the other part.

So, PCB development does matter and it should.

Stay tuned – we will walk through more on this topic over the coming weeks.

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13 November, 2009

My colleague, David Wiens, recently posted a blog about survey results that we collected regarding PCB design. One of the questions asked was around the most common platforms for collaboration. Eighty percent (80%) of the respondents claimed that email was their common platform for communication followed by conferencing as the next most commonly used vehicle for collaboration.

This got me thinking, our most common platforms for collaboration that we are using have been around for forty (40) years (for email) and 133 years for conferencing (telephone). If collaboration is so critical in business success, why are our collaboration platforms of choice  the ones that are least efficient? (In a Google Wave video there is a claim that email was invented the same year of the lava lamp, the last time I had a lava lamp was in my college dorm room twenty years ago – it went with my velvet posters and black light).

In the next question of the survey we asked about barriers to effective collaboration. The first response was that “ambiguous communications” was the major barrier to effective collaboration. This is a “no-duh” moment; the reason why there is so much ambiguity is because we are using highly inefficient means to collaborate!

There has to be (and there is) a better way. Over the past month and through December we are highlighting a series of webinars around PCB Layout and Routing. Our most recent webinar was around enabling concurrent team collaboration in layout and routing.

In today’s hyper-competitive and global business environment it no longer makes sense to have “push-pull” collaboration. This is mostly the paradigm of email and conferencing. We need to drive more concurrency throughout our processes. We need to enable “native” collaboration where engineers and designers can collaborate within the context of their own environments or where ECAD and MCAD teams can do the same. We need to be able to have real bridges between design and manufacturing and to be able to understand the implication and constraints of each others’ processes.

All of this is possible today – it just means getting rid of the lava lamp!

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