VHDL-AMS and Switch Hysteresis
Visiting with customers, particularly in a first or second visit when we’re introducing the benefits and features of SystemVision, is always quite interesting and usually enlightening. Many of these first discussions end with the customer asking the inevitable question: “Can you take one of our existing circuits and simulate it in SystemVision?” If we’re visiting with electronics designers, this usually means entering a SPICE-level circuit in SystemVision then running the design through its paces. But with the many versions of SPICE available, from the full-featured commercial packages to the freebie home-grown versions, we frequently face “model not available” problems. So what do we do? Fortunately, and as I’ve mentioned in earlier blog posts, SystemVision supports the IEEE standard VHDL-AMS modeling language.
Using VHDL-AMS it’s possible to model a variety of device behaviors. As an example, earlier this week I worked on a customer circuit trying to figure out how to add a bit of hysteresis to the operation of a SPICE-level voltage controlled switch model. The SystemVision model library has a voltage controlled switch model, but it doesn’t include hysteresis. Rather than invent a new switch from scratch, I simply took the source code for this switch and added a new architecture.
There are, of course, a variety of ways to model hysteresis, ranging from basic functionality to quite complex. For the project at hand, I only needed basic functionality. Here is the new architecture I added to the existing switch model (note that text preceded by double-dashes “- -“ are comments):
architecture hysteresis of vc_switch is
-- Define the switch resistance and initialize it to Roff which means
-- the switch is normally off.
quantity r_switch : RESISTANCE := Roff;
-- Define the input and output voltages
quantity v_in across in_p to in_n;
quantity v_out across i_out through out_p to out_n;
-- Check to see if v_in exceeds the threshold voltage.
-- If so, set the switch resistance to the ON value.
if v_in'above(Vt + Vh) use
r_switch == Ron;
-- Check to see if v_in drops below the threshold voltage.
-- If so, set the switch resistance to the OFF value.
elsif not v_in'above(Vt - Vh) use
r_switch == Roff;
-- If v_in is between the upper and lower hysteresis values,
-- switch resistance remains unchanged.
r_switch == r_switch;
-- Force the analog solver to take extra sample points at
-- threshold crossings.
break on v_in'above(Vt + Vh), v_in'above(Vt - Vh);
-- Use Ohm’s law to calculate the switch’s output voltage.
v_out == i_out*r_switch
end architecture hysteresis;
To make the switch model as flexible as possible, Ron, Roff, Vt, and Vh are VHDL-AMS generics defined in the model entity (not shown here). A generic is simply a parameter the model user can change to characterize the model’s behavior. Ron and Roff are the on and off resistances for the switch, respectively. Vt is the input voltage threshold level at which switching occurs, and Vh defines the range of switch hysteresis. Increasing Vh reduces the switch’s contact bounce. Here is a brief description of how the switch works:
If the input voltage (v_in) is greater than the sum of Vt and Vh (v_in > Vt + Vh), the switch resistance is set to Ron which is typically very small, effectively turning the switch on.
If v_in is less than Vt minus Vh (v_in < Vt – Vh), the switch resistance is set to Roff which is typically very large, effectively turning the switch off.
If v_in is within Vh of Vt, whether on the high or low side (Vt – Vh <= v_in <= Vt + Vh), the input voltage is in the transition region so the switch resistance remains unchanged.
And that’s all there is to modeling basic voltage controlled switch hysteresis using VHDL-AMS. With the architecture defined, it’s a simple matter to create the model entity to support the architecture. As with any simulation model, the key is understanding how the device functions. The rest is simply describing the function using VHDL-AMS syntax.
What would you add to make the switch hysteresis more realistic?