Posts Tagged ‘junction-to-case thermal resistance’

25 November, 2010

I guess, many people who had to find the metric  known as “theta-JC”  have asked themselves the question great many times: how to measure junction-to-case thermal resistance quickly and accurately

So did my colleagues at MicReD back in 2004/2005 when they had to do contract measurement of over 80 power transistor packages. The usual answer is: read the relevant standard – such as MIL-883 or SEMI G43-87. Well, this answer did not help them. The thermal resistance of the packages they had to measure was in the order of magnitude of 0.5 K/W. In this range the uncertainty of the measurement results caused by inherent problems of the above old, steady-state standards was in the same order of magnitude – resulting in errors of 80-90%. What were the major issues?

The MIL standard for example requires the measurement be carried out on a cold-plate. Usually some kind of a thermal interface material (TIM) is applied between the case surface of the package and the cold-plate. The problem of this is, that the applied TIM’s thermal resistance also contributes to the RthJC value measured this way. And this contribution depends on many different factors (the thermal conductivity of the TIM itself, its thickness, viscosity, pressure)  which are very hard to standardize. These factors have never been treated in any thermal testing standard yet. Not having been standardized would not have been an issue if these uncertainties had not affected the accuracy and the repeatability of the results. But they did – to a great extent.

The other major problem with the above classical RthJCmeasurement standards is that they require the case temperature being measured by a thermocouple placed to the hottest point of the case surface. But where is this hottest point? Can thermal testing managers expect their technicians who perform the actual measurements to locate these spots e.g. by means of an IR camera? Of course not. So, the rule of thumb is to try to hit the middle of the case surface. Well, the problem again is that a little misplacement of the thermocouple causes big measurement errors and results in poor repeatability of the measured data. And another aspect is that one should not “try to hit”. A “trail-and-error” procedure is not good at all – even if it has been standardized for decades. If the goal is to provide data sheet values for a semiconductor vendor’s parts then the measured thermal metrics have to be reliable – that’s the interest of the end-users of the components. Having reliable and precise values for data sheets is also the primary interest of the component vendors. For example in case of power semiconductors a lower junction-to-case thermal resistance is among the unique selling points – creating a battlefield between the package designers and the marketing team. Of course I am speaking about honest companies – where a product is always accompanied by a real data sheet rather than by a data cheat.

So, we had to prove by our own measurements that the power packages we were contracted to measure really had the smallest thermal resistance. Overestimating the junction-to-case value destroys the unique selling point for the company. And it may happen if to much of grease is applied and its thermal resistance appears in our measured values. Underestimating the value is also a problem: if too small RthJCvalues are published by the vendors they end-users might overheat the devices which will burn out. Again, it is a reliability issue and perhaps results in many cases being filed at different courts. I have used the word “estimation” twice – I simply could not find any other word for a situtaion where repeatability of the measurements is poor, the measurement error is high since you have to “hit” the hot spot. So, my colleages were trapped.


Two junction cooling transients measured for two different qualities of the thermal interface between the package CASE and the heat-sink.

The way out from the trap was a genius trick: using a transient measurement method and structure functions in a smart way. The idea is very simple: apply the physical setup as suggested by the MIL 883 standard but measure the transient of the junction temperature only after the dissipation of the semiconductor device is cut off abruptly. Record this transient very accurately. Then change the quality of the junction-to-heatsink heat-flow path at the case surface of the package. Originally my colleagues inserted a sheet of thermal insulator layer – either a thin piece of Mylar or just a ceramics plate. With this second physical arrangement they did a second transient measurement. Then the differential structure functions have been derived from both measured junction temperature transients. The heat-flow path structure was changed at the CASE, so any change between the two structure functions should exactly indicate where the CASE of the package is in terms of thermal resistance. So, the thermal resistance value where the two structure functions start deviating is the junction-to-case thermal resistance. Really simple, isn’t it. This method – which since then is called the transient dual interface method – was first published at SEMI-THERM in San Jose in 2005. And this paper (later published in IEEE Tr. on Components and Pacckaging Technologiesr)  was distinguished by the best paper award of this conference. (Find the original paper in this list).


The structure functions differ from the point where the physical structure was changed. This indicates the CASE surface and the reading from the horizontal axis provides the RthJC value.

Well, this is all history. The present NOW is, that 5 years after the method was invented, it got standardized by JEDEC. Actually, Dirk Schweitzer, one of Infineon’s acknowledged thermal engineers made a great job in assessing the method. He performed analysis of lot of different cases: different kinds of package types with different die attach solutions were studied and got published by Dirk. And at the end of the day, a new standard was created. The JEDEC JC15 committee made also a great job: before the ballot a round-robin test was organized among companies who delegated members to the committee to confirm the applicability of the proposed standard. And since Tuesday, 23 November 2010 we have the new JEDEC JESD51-14 standard. Find below JEDEC’s original announcement about this: 



This document specifies a test method (referred to herein as “Transient Dual Interface Measurement”) to determine the conductive thermal resistance “Junction-to-Case” RθJCJC) of semiconductor devices with a heat flow through a single path, i.e., semiconductor devices with a high conductive heat flow path from the die surface that is heated to a package case surface that can be cooled by contacting it to an external heat sink.

Ask me for example if you are interested how to implement this standard with Mentor Graphics’  T3Ster equipment and the T3Ster-Master data analysis software. Believe me, it’s a great fun!

Best regards: Andras

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