All Aboard! EDA Companies Adopt New UVM from Accellera’s VIP/TSC to verify IC Designs (I love Acronyms)
The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs.
Accellera’s Verification IP (VIP) Technical Subcommittee (TSC) developed the standard, which is now available for download from the organization’s Web site at www.accellera.org. Also offered for download are: the Class Reference Manual, an open-source SystemVerilog base class library implementation, and a User Guide.
“The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability and tool, and VIP interoperability,” according to an Accellera spokesperson.
EDA technology companies, including Mentor Graphics Corp., support UVM; Mentor Graphics is an early supporter, in fact. Also of note, Accellera based the new UVM standard on Open Verification Methodology (OVM), which in 2007 was jointly developed by Mentor Graphics and Cadence Design Systems. The same day Accellera approved UVM 1.0, Mentor Graphics announced comprehensive support for UVM across a broad range of its products, including: the Questa advanced functional verification platform, Questa MVC Verification IP library, Veloce emulation platform, and Certe Testbench Studio tool.
“We see firsthand what a huge impact a comprehensive methodology can have to bring the verification effort under control, and to facilitate the horizontal and vertical reuse that users need to successfully verify SOCs,” explains John Lenyo, general manager, Design Verification Technology division, Mentor Graphics. “The release of UVM 1.0 is the culmination of countless man hours of discussion, debate, and idea sharing. Congratulations to everyone involved.”
Indeed, congratulations on the new standard. The electronics industry is buzzing about UVM, and this geek is anxious to witness its impact on the mil/aero market.
Posted February 22nd, 2011, by J VanDomelen
Accellera, design, design automation, EDA, electronic design automation, IC, integrated circuit, intellectual property, IP, John Lenyo, mentor, Mentor Graphics, Mentor.com, mil-aero, milaero, Open Verification Methodology, OVM, TSC, Universal Verification Methodology, UVM, Verification IP (VIP) Technical Subcommittee (TSC), VIP
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