Archive for Patrick Carrier

15 February, 2017

I frequently get asked, “what is the maximum frequency that you can simulate in HyperLynx?”  And I usually say that it depends on what kind of models you are using.  Different components of HyperLynx have different degrees of accuracy, but the combination of our built-in trace models and the Full-Wave Solver allow for accuracy up to the 50GHz range for your PCB structures, while also allowing for the most efficient analysis time.  As I blogged last week, getting accurate models to that range typically requires a very intimate understanding of your board materials, from basic understanding of dielectric constant and loss tangent, to understanding surface roughness and the frequency variance of the material parameters.  You can read more about correlation in my recent article in PCDandF magazine.  And another important consideration is how much accuracy do you need… for perfect correlation on 50Gbs links, you will need to spend more time making sure you have to most accurate information on materials and are using advanced models when necessary.  But if you are only running at a few Gbs, you could likely get away with using the basic material parameters, ignoring surface roughness, and not using 3D models for things like vias and DC blocking caps.  Whatever your needs, HyperLynx is always committed to providing the necessary accuracy as easily as possible.

10 February, 2017

The advent of high-speed serial links added many challenges to the process of designing PCBs.  In some ways, it made things easier by eliminating the complicated length-matching required for parallel busses like DDR(1,2,3,4).  But mostly, it added challenges.  One of the most notable challenges is the inability to measure the bus in a lab.  The most obvious reason for this is that due to the fast edge rates of these busses, measuring at the pin is essentially the middle of the bus, so you don’t get a clean “endpoint” waveform.  Even if it were possible, you would still need to measure on the “other side” of the receiver equalization to see what the receiver is seeing.  In order to deal with these measurement limitations, many SERDES specs advocate the use of test fixtures.  These test fixtures typically have a standard connector on them to allow them to plug into a customer board, with some trace routing to SMA connectors to allow a high-bandwidth connection to an oscilloscope.  The oscilloscope then mimics the receiver equalization to generate an eye diagram.  This is where simulation presents an advantage, by allowing you to look anywhere in the circuit, including inside the receiver after the equalization.  Another advantage of simulation is the ability to generate worst-case conditions directly, without having to wait the long periods of time it might take to capture them in the lab.

To hear more about simulation and measurement, check out my recent article in PCDandF magazine.

9 February, 2017

Last week I attended DesignCon, and as usual correlation between simulation and measurement was a hot topic, especially for the newer “bleeding edge” bus speeds.  In fact, I recently wrote an article on the topic that can be found here.  As we start approaching 50Gb/s speeds, proper materials characterization is crucial to achieving good correlation.  In other words, putting the right material properties into your simulation becomes essential to getting an accurate answer.  Even at slower speeds, basic material properties are essential to getting accurate results, and can often be difficult to obtain.  Fortunately, material suppliers and board manufacturers are more aware of these issues than they were before, so you can rely a little bit more on their expertise.  But, it is still your responsibility to get that information from the material supplier, and to push them to make sure the info they are supplying is correct.  Even something as basic as the dielectric constant of the dielectric materials, which will vary based on thickness, and will also vary closer to the traces (which I have written about in previous blogs), is crucial to getting accurate timing numbers and impedances.  As frequencies get higher, more advanced factors like properly characterizing the surface roughness of the traces and using a wideband dielectric model become increasingly important.

29 September, 2016

Performing an accurate high-frequency analysis of a power distribution network routed with traces instead of planes poses some interesting challenges.  Most notably, the analysis engine has to be flexible enough to model complicated coupling between power and ground.  The typical assumptions made by a planar solver are no longer valid, and more sophisticated modeling must be used.  In HyperLynx, we have addressed this challenge by integrating our Full-Wave Solver technology into decoupling analysis.  In the new Advanced Decoupling Wizard, you can analyze any PDN structure.  See it in action in this video.  This includes analyzing trace-routed PDNs, PDNs with series components like ferrites, inductors, or other kinds of filters, or any other kind of PDN you might have on your PCB.  While the existing Decoupling Wizard is unmatched in performance and capacity for analyzing a “traditional” PDN, the Advanced Decoupling Wizard has the flexibility and power to analyze any PDN structure.

6 September, 2016

By far, DC Drop issues are the simplest problems you can run into when designing a power distribution network or PDN.  They are also well understood, too: not enough metal, and you have voltage drop issues.  Analysis of these issues can be complex, with constantly changing path widths and multi-layer current paths, but that’s why we have simulators to do the work for us.  Setting up these problems to be analyzed is relatively easy – you just need to define voltage sources and current sinks.  And solving the issues are fairly easy as well – you just need to add more metal.  More metal may mean additional stitching vias and/or layers to carry the necessary current, or just widening a plane shape.  This is where the expertise of a layout designer is well-utilized, as they understand how to fit things into the busy layout to meet design constraints.  It therefore makes sense to move this aspect of PDN design directly into the layout, which makes the PCB design process much more efficient.  Take a look at this video to see how easy it is to analyze and correct these issues directly in layout.

19 August, 2016

A question I get all too often on power integrity results is whether or not a current density issue is going to cause a problem.  The answer to that question is how much heat is going to result from that current density, and to know that you really need to do a PI/Thermal co-simulation.  I have blogged in the past about PI/Thermal co-simulation, and its importance in characterizing these issues.  With the fast built-in thermal solver in HyperLynx PI, it is really easy to do a co-simulation and get accurate results.  Modeling can be as simple or as complicated as you want, but extensive setup is not necessary to get accurate co-simulation results.  Stop guessing at whether or not you have a PI problem that is going to cause thermal issues, and vice versa…  Check out the product demo here to see how easy it is to include temperature effects in your PI simulations.  And while you’re at it, there are a lot of other great product demos on PCB design as well.

26 April, 2016

At today’s speeds, everything matters in PCB design and analysis tools that enable efficient modeling are key. From full-wave 3D electromagnetic solvers to electrically aware PCB checking tools, I recommend a solution that offers comprehensive analysis of any type of bus.

PCB Analysis Solution

DDR3 and DDR4 designs, for instance, are becoming very common.  They employ a number of interface-specific mechanisms for maintaining performance, such as write-leveling and data bus inversion or DBI. Validating these interfaces requires consideration of on-chip timing, slew-rate derating to accurately characterize the on-board timing, and even taking into account the effects of the power distribution network on timing and signal quality.

High-speed serial or SERDES interfaces are pushing the limits of PCB performance.  In order to properly characterize these signals at higher frequencies, advanced 3D solvers must be used to model pieces of the interconnect like vias, connectors, and chip breakouts. Combining those models with S-parameter models and trace models properly is essential to accurately characterizing the channel.  And, new methods have emerged to simulate the channel and predict its performance down to very low BER (bit error rate) levels.

At this year’s PCB Forums, presenters will demonstrate all of the great technology in HyperLynx and how it applies to your PCB designs. Whether you’re an advanced designer or newer and still learning, and regardless of what solutions you currently utilize, PCB Forums has sessions for you. Find a location near you and reserve your seat today!

In the meantime, here are a couple of product demos of the SERDES simulation capabilities in HyperLynx:

Also, there are many more demos, webinars, and whitepapers available at

6 August, 2015

This is the final post in a three-part series discussing PCB design EMI Reduction. View the first and second.

Early in my career, I was working with a talented design group on a pretty complicated system. They did something that many other design groups did not: up-front power plane planning. They mapped out where all their signals would be routed, and made sure that the adjacent planes were either ground or the voltage that powered those nets. They also made sure that the traces did not cross any plane splits.

The resulting design was very quiet from an EMI standpoint. So quiet, in fact, that they took the case off during EMI testing to make sure the system was working! Even with the case off, the system was passing the FCC Class A limits for radiated emissions. This is a great example of how proper return path planning can result in superior EMC performance.

One of the optional checks in the Vertical Reference Plane Change DRC, a standard rule in HyperLynx DRC, makes sure signals reference the “correct” voltages on the PCB. This is one of the many valuable return path checks that come standard as part of HyperLynx DRC. Other return path issues, such as the “invisible” return path breaks at the ICs, can be minimized through solid PDN design with a tool like HyperLynx PI.

EMC Performance: Passing Class A with the Case Off

If you are interested in learning more, check out my recent article on Options for Reducing EMI in a PCB Design.

28 July, 2015

This is the second in a three-part series discussing PCB design EMI reduction.

In my previous blog post, I discussed different methods of containing radiated emissions. However, containment is a really poor solution to the problem. A better solution is to suppress emissions by fixing the problem areas on your board.

Increasing bypass impedance from larger stitching via spacings shown in HyperLynx PI; results of Vertical Reference Plane Change DRC from HyperLynx DRC.

Increasing bypass impedance from larger stitching via spacings shown in HyperLynx PI; results of Vertical Reference Plane Change DRC from HyperLynx DRC.

HyperLynx DRC can find a number of structures that can cause unwanted emissions from a PCB, most of which involve poor or missing return paths. I have blogged many times in the past about the importance of return path. Breaks in return path can come from something obvious like a trace crossing a plane split, or something a little less obvious like a signal via, or even a signal going through a connector.

Care must be taken to make sure that the signal return path stays continuous throughout its path along the board, which may be accomplished with something as simple as intelligent layer selection, or as complicated as adding stitching vias and capacitors. I discuss this in greater detail in “Options for Reducing EMI on a PCB Design,” my recent article on Printed Circuit Design & Fab.

If you aren’t yet sold on the importance of return path for high-speed signaling, try disconnecting the shield on your cable TV cable, and you will probably start feeling a little suppressed…

20 July, 2015

This is the first in a three-part series discussing PCB design EMI reduction.

How can you tell if a fence is goat-proof? Throw a bucket full of water at it, and if any makes it through, the goat can get through the fence. That is one of the many pieces of “folksy” wisdom I have gotten over the years from my father-in-law, and one of the many benefits that comes along with marrying a girl from Texas.

But, all kidding aside, trying to contain EMI can actually be a lot like trying to keep a goat inside a fence. It is one of the topics I discuss in “Options for Reducing EMI on a PCB Design,” my recent article on Printed Circuit Design & Fab.

The most obvious method of containing radiated emissions is to put your PCB inside some kind of metal box. If you need holes for ventilation, those holes need to be small enough to contain your highest frequency of concern. If you need to be able to open the box, the openings need to have EMI gaskets so that the box still acts like a Faraday cage to contain your emissions.

If you don’t want to go through that hassle, you might try containing EMI at the PCB level, by turning your PCB into a Faraday cage. This can be done by routing a thick trace around the periphery of the board on each layer (or at least the outer layers), and stitching them together periodically with vias.  Such a structure can be verified by using the “Edge Shield” DRC, one of the standard rules in HyperLynx.

Contain the PCB Design EMI Beast

Depiction of Faraday cage on a board; side view of resulting apertures; results from running Edge Shield DRC in HyperLynx DRC

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