Archive for March, 2012

31 March, 2012

Running at 6GHz is actually kind of scary regardless, but especially so with your eyes closed.  And I mean that more figuratively than literally.  Obviously, if your eye diagrams are closed on your serial links in your design there is cause for fear, but the fear of the unknown can be even greater, especially if you are running at multi-GHz speeds.  That is where a complement of pre-layout and post-layout signal integrity simulation can help.
Take a look at this article discussing the differences:

Pre-layout simulations are a great way to see if a design is even feasible.  For instance, if you are trying to run a 6Gbps link like Serial ATA or SAS through several boards and a long backplane, it might not make it unless you make the appropriate choice of connector, board stackup, and trace geometries.  Pre-layout simulation is a great way of gaining an understanding of the limitations of a certain bus architecture, and understanding the margins of your system.  This opens your eyes to what your design is actually doing.  It also leads to a better understanding of what might be a potential problem once the system is built.  In fact, post-layout simulation is even more useful in that regard, as it gives the most accurate view of what is going on at the receiver.  Post-layout simulation is often more useful than actual measurement.  Multi-GHz busses cannot be measured while they are running; they usually need to be measured into some sort of test fixture.  So, having a post-layout simulation handy to see what is going on in the actual design, including the effects of equalization at the receiver, is invaluable.

, , , , , ,

29 March, 2012

It’s never too late to fix a design problem.  Well, maybe if the product is shipping, that might be classified as “too late”.  But during the design phase, whether you’ve laid out your board or not, it’s a good time to make sure there are no design issues.  When it comes to signal integrity, that means performing pre-layout or post-layout simulations.  I think most experts agree that pre-layout simulations are the best time to do signal integrity.  There those, however, that feel pre-layout simulations are a lot of time wasted on “what might be”, but the counter-argument is that if you don’t simulate, how do you know what constraints to apply to your board layout as it is being layed out.  I say as long as you do EITHER before the product ships, you’ve done well.  But, when it comes to getting products out in the fastest and most efficient manner, a mixture of both pre-layout and post-layout simulation will best suit your needs.

What’s the difference?  Well, other than the obvious fact that post-route simulations are done after layout, I would classify the main difference as the fact that pre-layout simulation is aimed more at exploring a solution space and creating design constraints, while post-layout is aimed at verifying that those constraints were met.  For a more in-depth discussion on the differences, take a look at this article in Electronic Design magazine:

, , , ,

7 March, 2012

Parallel busses are a pain to implement.  They really are.  Sure, they are slower than blazing-fast SERDES busses, but they introduce a lot more problems.  SERDES busses introduce a new set of problems because they are so fast, but they are also differential and serial, which eliminates a bunch of problems.  Parallel busses are single-ended, so they tend to draw a lot more power.  So that means you have to worry about designing a good power distribution network (PDN), and worry about things like simultaneous switching noise.  Any layer transitions require ample stitching vias (or stitching capacitors) as well, so the vias and PDN are inter-related.  Not to mention all the complicated timing relationships that need to be maintained…

The original DDR was probably the toughest parallel bus to implement successfully.  DDR2 got faster, but also implemented a number of changes to make implementation easier – changes like using slew-rate derating to get a better picture of your timing margin, and allowing for 2T timing on the heavily-loaded address bus.  And DDR3 added the new fly-by address routing and write-leveling.  Really, these changes were necessary to operate at faster speeds, but also helped make things easier.  Easier, that is, if you understand how to include all of them in your analysis of the bus.

If you are interested in finding out more about the challenges facing DDR3/4 and SERDES busses, take a look at this article in New Electronics magazine:

, , , , , ,

6 March, 2012

Interconnect loss modeling?  Check. 
Signal conditioning modeling?  Check. 
Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain?  Oooh…. that’s a tough one.  Check!
Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis?  Wow!  Check.
3D via modeling?  Check!
HyperLynx 8.2 is fully equipped to handle every SERDES problem you can throw at it.  Really, any signal integrity problem you can throw at it.  Power integrity too.

In general, SERDES designs are a lot easier to implement than parallel busses.  You have a smaller number of problems to worry about, but the problems that are there are considerable.  They are basically problems of fast edges and low margins.  The fast edges require careful attention to detail in all aspects of the layout, and bring about the need to analyze pieces of the interconnect that could be ignored with slower edges, most notably vias.  And the low margins necessitate a greater understanding of when the bus will actually fail.  So in order to be successful in the analysis of these busses, care must be taken to include everything that is needed to understand the limits.

Read more about it in my recent article in New Electronics magazine:

, , , , , , , ,

5 March, 2012

“A man’s got to know his limitations” … true, and so does a digital bus.  Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses.  Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity.  And now, in sharp contrast, we’ve progressed to the point where we try to validate busses down to bit error rate (BER) levels of 10^-15.  And things are moving so fast now that you can’t rely on measurement to know your margins, or your limits.  Even parallel busses like DDR3 require simulation in order to appropriately understand the margins of the bus.  Probing at the pin on such busses yields little more than very ugly waveforms, so simulation allows a unique perspective into the limits of the bus. 

For SERDES busses, this is especially true.  With receiver equalization becoming very common, it is very important to know what the signal looks like inside the IC.  And, in order to ensure the bus will work to the required performance standards, you have to run simulations that predict performance for trillions of bits, and include effects of deterministic and random jitter.

You can read about this in greater detail in my recent article in New Electronics magazine on page 25:

, , , , ,

@MentorPCB tweets

Follow MentorPCB