Among the many threats to design schedules and design quality is achieving physical verification signoff on time and with minimal ECO iterations. At advanced nodes (16/14/10/7nm), with the introduction of FinFETs and Multi-patterning, designs now have to meet very complex rules for DRC, multi-patterning (MP), and DFM (Figure 1). The number of physical verification errors found during signoff is increasing significantly, which requires multiple, sometimes non-convergent, signoff iterations. Each pass involves time-consuming transfers of huge data files between the signoff analysis and the implementation tools. Multi-pattern conflicts, unlike DRC violations are global in nature and could impact several objects that span significant distances. Fixing multi-patterning problems in a local scope might contribute to global cycles and it might be too late to leave multi-cycle fixing to the last step of routing flow.
Designers used to be able to complete physical design before starting physical verification signoff analysis, but that approach no longer works due to the inherent complexities of advanced-node designs. The optimal way to solve these growing manufacturing closure problems is to address them starting in physical design, well before sign-off verification. This moves manufacturing closure actions early enough in the design process to allow them to be effective, to avoid late stage surprises and to avoid non-convergent iterations.
Mentor’s Calibre InRoute is and interactive design and manufacturing closure platform that enables all the Calibre sign-off capabilities from within the place and route environment. It is built on Mentor Place and Route System (Nitro-SoC & Olympus-SoC) and Calibre, the industry standard for manufacturing sign-off. Calibre InRoute. Some of the features of Calibre InRoute include:
- DRC, DFM, and multi-patterning analysis and fixing during design with direct access to signoff engines ensuring that the manufacturability issues are resolved without introducing new ones or degrading design performance
- Automatically fixes and incrementally verifies violations at either the block or full-chip level
- Uses routing technology with native coloring, verification and smart conflict resolution engines to handle both local and global multi patterning violations
- Concurrently optimizes the layout for all timing, power, signal integrity (SI), and manufacturing issues;
Calibre InRoute is based on the open router architecture that allows the place and route tools (Nitro-SoC and Olympus-SoC) to natively invoke the Calibre sign-off engines in the inner loop of the router without any file transfers. It has API-level access to the Calibre engines and performs true signoff analysis and then uses the router to automatically fix any violations without introducing new ones or degrading design performance. All violations found with Calibre InRoute are persistent in the place and route database, and can be viewed and edited through the error browser. Calibre InRoute includes the full suite of Calibre capabilities.
Shifting physical signoff into place and route minimizes the growing gap between design and signoff environments to improve design schedules and design quality and speed time-to-market. With Calibre InRoute, manufacturing closure that takes weeks or months can be reduced to days.
White paper: https://auth.mentor.com/products/ic_nanometer_design/resources/overview/advanced-manufacturing-closure-with-calibre-inroute-and-mentor-place-and-route-aa1e13ad-eec6-4665-b622-e582b6897fa9