Xpedition Enterprise Blog

Learn about the industry's most innovative PCB design flow, providing integration from system design definition to manufacturing execution.

We'll keep you updated on the latest design trends, and other interesting tech tidbits in the industry.

28 January, 2015

This is the fourth post in a series showcasing the winners of the 2014 Technology Leadership Awards. View the previous ones here.

First place winner in the Consumer Electronics & Handheld category: Qualcomm, United States

Qualcomm Technologies Logo

Design: a Quad-core APQ (application processor Qualcomm) targeting the tablet/netbook market segments

Design team: Larry Paul, Sanat Kapoor, Stephen Baker, Danlin Xiang, Michael Tex

Design challenges:

  • Quad-core Krait, A320 3DGfx, Dual Channel PCDDR3/3L + LPDDR2 PoP option, integrated GPS SS w/Gen8A-Lite Nav core, 1080p HDMI Video, Media Processor, SATA Gen1, and PCIe 2.0
  • To maintain cost constraints, a through-hole 8-Layer stackup with no HDI layers needed to be used
  • Trace width dimensions of under 3th
  • Multidiscipline collaboration was utilized:
  • PCB Layout, Package & APQ were designed together with a co-design process and collaborated across the PCB, package and IC design teams
  • The power and signal integrity group helped with simulations and design feedback; multiple rounds of power simulations and memory simulations were needed to optimize the package and PCB routing
  • Design for reuse – the second memory circuit was designed to be copied and replicated; memory circuit can be single or dual ranked to support four memory banks
  • Eight DDR comps mounted four on each side; sharing thru via fanouts
  • 97 percent of the design was high-speed nets, with close to 9,000 connections

Qualcomm Technologies Technology Leadership Awards Winning Design

Design tools and team comments:

  • Xpedition® Enterprise and Package Integrator
  • Package Integrator is used at Qualcomm to help optimize pin definition on the APQ.
  • “Mentor’s Package Integrator tool allowed us to manage multiple rounds of signal assignment evaluation across teams without loss of data. The design was initially worked out in a co-design study through PCB Layout. Near completion the circuit placement and routing was copied to a customer reference design to re-use and quickly route 80% of the traces. This allowed us to build a product quickly and fabricate a working design with no design spins.”

Judge’s comments:

  • The intense activity around the RAM is very impressive.
  • Good team effort across multiple disciplines. This is a tight design considering that is utilizes standard technology instead of HDI.

About the Technology Leadership Awards

Started in 1988, this program is the longest running competition of its kind in the electronic design automation (EDA) industry. It recognizes engineers and designers who use innovative methods and design tools to address today’s complex PCB systems design challenges and produce industry-leading products. See the full list of 2014 winners here.

26 January, 2015

This is the third post in a series showcasing the winners of the 2014 Technology Leadership Awards. View the previous ones here.

Runner up in the Computers, Blade & Servers, and Memory Systems category: Sanmina, India.

Sanmina Corporation Logo

Design: a DDR3 240 pin RDIMM

Design team:

  • Damodhar Chakravarthy Mallisetty, Tom Thomas, and Birla Manoharan

Design challenges:

  • DDR3 240pin UVLP RDIMM 1333MT/S ECC 17.75mm 2R x4 10 layer Viking Stacked BGA
  • Using fly by topology and length matching within the time limit was a big challenge
  • Embedded resistors were used in layer three and no vias could be placed around the embedded resistors
  • No traces were allowed over the slot in this design
  • Placing components within the tight clearances was a great challenge

Sanmina Corporation Winning Design 2014 Technology Leadership Awards

Design tools and team comments:

  • Xpedition® Enterprise allowed for via keepouts for embedded resistors and fast routing
  • HyperLynx® was used to verify the signal integrity for the tuned address signals and keep them within the limits

Judge’s comments

  • Long thin boards can present serious design challenges and this design makes very good use of board real estate.

About the Technology Leadership Awards

Started in 1988, this program is the longest running competition of its kind in the electronic design automation (EDA) industry. It recognizes engineers and designers who use innovative methods and design tools to address today’s complex PCB systems design challenges and produce industry-leading products. See the full list of 2014 winners here.

19 January, 2015

Shortly after I graduated with my Associates degree in technical drafting, I entered the world of computer aided design. I trained in CAD technology on one of the very first computer design systems – CEADS CAD, and we young bucks could not wait to jump right into drawing designs on the computer screen.

Our teacher, a tall Texan with a big stern voice, told us that we might come across many CAD systems but that no matter what they could accomplish, they could not accomplish it without a quality library. These libraries would be the building blocks of our designs.

Since my CAD training stressed the importance of a good library to achieve quality designs, I have always trained the designers that report to me on the importance of a correct-by-construction PCB component library. Over the years, I have built thousands of the components used in designs, and trained many a librarian in the processes that make up a quality library.

Xpedition Starter Libraries

Just before I came to Mentor Graphics, I was given the task to create a component library and information database that would be used by over 400 design engineers in my company. It was a huge undertaking including over one hundred thousand records of component information that would be used to design and fabricate the designs of tomorrow.

First and foremost, the library had to be flawless in quality as to not create board errors, or errors in fabrication – the library currently in use was perilous to use. The new library had to be hands-off for the engineers. In other words, they needed to be able to request parts and walk away expecting to get exactly what they needed, correct the first time. Yes, a very daunting task!

So, with the help of my one librarian, and some old friends at Optimum Design Associates, we took on the task. Although it took over a year to complete the library (you see we were using it while we were building it), we completed it with fantastic results.

I am proud to say that to this day no Xpedition design using the library has ever failed due to a bad library component. This was always my goal as a designer.

We could not have done it without the library team, and my buddies at ODA, specifically Justin Parise. Their attention to library details and the knowledge of the needs of the PCB Design engineers is second to none. A quality library was what they promised, and it is what I received.

And NOW, with the release of Xpedition VX.1, you can have these same results.

With the latest release, users can download a FREE complete starter library created by my friends at Optimum Design Associates. You will get the same quality components that I received when working with them. Of course, you will not get hundreds of thousands of components, but you will get a great baseline library and component information database so your design team can hit the ground running.

Optimum Design Associates Logo

Download your very own building blocks to PCB design today!

Not an Xpedition user? PADS® users may download starter libraries here.

12 January, 2015

This is the second post in a series showcasing the winners of the 2014 Technology Leadership Awards. View the first here.

First place winner in the Computers, Blade & Servers, and Memory Systems category: Seagate Technology, United States.

Technology Leadership Awards_Seagate

Design: The team used all of the “tricks in the book” to achieve placement and routing within the speed/timing parameters on their mid-range enterprise solid-state drive.

Design team:

  • Andre’ Dutko, Keith MacLean

Design challenges:

  • This was a heavily constrained design with a high percentage of high-speed nets; over 64,000 constraints in the design and lots of restrictions due to PCIE, DDR3 and Flash. Tight length matching to balance byte lanes; isolation of multi-GHz signals; layer count and thickness restrictions.
  • Adjacent layer coupling and reference plane impact on SI required extensive collaboration between layout designer and project engineer.
  • Power distribution for 37 voltages with current ranging from 0.5 – 5.0 amps.
  • Buried vias were avoided as a cost consideration.

2014 Technology Leadership Award Winner Seagate_Design

Design tools and team comments:

  • Xpedition® Enterprise flow and Hyperlynx®
  • The 556 pin BGA/SOC was the most complex component. Beyond the multiple power supplies required, it is driving two DDR3 chips and 16 (back-to-back) NANDs. All of which had separate byte lanes containing unique Data, Command and Control and/or Address.
  • High volume manufacturing requirements with multiple variants also added to cost considerations.

Judges’ comments:

  • This design has very high lead density due to innovative side-side placement and routing of the memory.
  • This is a tight design considering that is utilizes standard technology instead of HDI. I like the way they utilized the various tools within the flow to achieve design requirements.

About the Technology Leadership Awards

Started in 1988, this program is the longest running competition of its kind in the electronic design automation (EDA) industry. It recognizes engineers and designers who use innovative methods and design tools to address today’s complex PCB systems design challenges and produce industry-leading products. See the full list of 2014 winners here.

9 January, 2015

As you may already know, the Xpedition VX.1 release is now available to customers. I encourage you to take some time to evaluate it because if there is one thing to mention about this release, it is that you will be able to increase your productivity significantly. It can be downloaded at SupportNet.

We have added some new interactive routing styles that complement the existing ones quite well. The differences between these styles are found in the amount of automation applied to the action, and the type of user control. Looking at Editor Control/Plow, the methods are listed:

PCB Routing Solutions Editor Control Plow methods

You can set a style for routing with the Mouse Up (clicking when needed) and for the Mouse Down (dragging as you route). I recommend trying the default style using Real Trace for a couple weeks to really get a good feel for its value.

Real Trace Plow

This is the new functionality. Real Trace is what can be called a “One-Click” interactive router. All you need to do once you are in Plow mode is to click on a route object and start routing. The trace is added as you move your cursor – no need to click again. It even finishes the route automatically when it gets close to the end of the netline. Watch this video to see in detail.

Delayed Option – This option allows you to delay the application of push & shove until the trace being added is in an open space. Why? We have found that by waiting to apply the push & shove, the quality of the traces being pushed is much better because we consider a longer length of trace and smooth it and those little unnecessary jogs are eliminated.

Dynamic Option – With this style, push & shove is applied dynamically as the trace is being added. You might be thinking, after I described the value of the Delayed option – why would we come back and enable you to have the push & shove done dynamically? Sometimes it is desirable to immediately see how a trace will fit through a tight area. The good news is that all you have to do is hold down the left mouse button and push & shove will be applied as long as you are dragging. Rumors that the push & shove is more effective if you press harder on the mouse button are not true; however, I do understand that sometimes this method may be useful to release some pent-up emotions during stressful days.

The Hockey Stick style works as it has in previous releases; however, the Local Gloss has been improved significantly to provide higher quality routing. For those who want to click-click-click-click to create every segment, the Segment style for ultimate control is still available.

Other New Items

Active Clearances – This feature dynamically displays a shadow around objects that shows you the design rule clearances to the trace being plowed. This is especially useful when Plow fails and it is not easy to understand why.

PCB Routing Active Clearances 1PCB Routing Active Clearances 2

Fixed & Locked Patterns – You can now set your own patterns for fixed and locked objects in the Display Control / Graphic tab.

PCB Routing Fixed and Locked Patterns

Route Object Appearance – Another feature that may be useful is the ability to set a specific pattern on general Traces, Pads and Plane Data. This is also on the Display Control / Graphic tab.

PCB Routing Route Object Appearance

Conclusion

As time goes on, we continue to make both big and small enhancements to our design tools. Many of the enhancements are driven by customer requests and we often go out-of-the-box with things like the Sketch Router.

What do you think would be a good improvement in our interactive routing tools? Maybe it has already been done in the Xpedition VX.1 Layout product and all I need to do is show you where it is.

7 January, 2015

This is the first in a series showcasing the winners of the 2014 Technology Leadership Awards.

The votes are in for the 2014 TLAs! Congratulations to the 2014 Technology Leadership Award winners! Started in 1988, this program is the longest running competition of its kind in the electronic design automation (EDA) industry. The competition recognizes engineers and designers who use innovative methods and design tools to address today’s complex PCB systems design challenges and produce industry-leading products.

Overall 2014 Winner: Alcatel-Lucent, Italy

Alcaltel-Lucent Logo

Design:  An evolution in core packet processing technology, Alcatel-Lucent’s 1X100GE packet module includes 100Gb/s of total processing power and signals operating at 6/12/28GHz.

Design team: Fabrizio Crippa, Giovanni Villa, Sergio Pirovano, Massimo Pollastri, Stefano Cornini, Luigi Aldeghi, Fabio Villa, Paolo Scotti, Massimiliano Severi, Ivan Malaspina, Fabio Frigerio, and Donato Maggi

Design challenges:

  • Design for: signal/power integrity, reliability, manufacturability, cost, and variants
  • 6,000+ components, 22,000+ connections, 20,000+ vias, 24 layers
  • 70% nets high-speed: used Constraint Manager for more than 200 buses with length controls on ~5,000 nets and more than 10,000 connections; all routed by hand and verified
  • Cost constraints for high-volume product drove the overall design process and influenced many of the decisions; limited use of HDI due to cost constraints resulted in greater placement and routing effort
  • Placement restrictions: height constraints based on racking system forced all tall comps to one side; couldn’t be over internal high-frequency signals; also had to consider DFM issues associated with rework and testing (100% test point coverage)
  • Multi-discipline concurrent design: the board design involved several disciplines including signal and power integrity, mechanical, thermal, layout, and DFM/DFT. To achieve the aggressive schedule, each of these components was implemented in parallel with the design team sharing data at appropriate stages. The design team used the flexibility of their Xpedition® tool chain to collaborate in real time during schematic entry, layout, and manufacturing validation.
  • “But the biggest challenge was to make sure that this project works the first time, and this has been met!”

2014 TLA Overall Winner Alcatel-Lucent's Design

Design tools:

  • Xpedition Enterprise flow
  • Many power supplies with currents higher than 30Amps and tight drop voltage tolerances required detailed study and simulation with HyperLynx® PI. Power integrity analysis performed by HyperLynx in early and final design stage allowed PI expert to verify if the two distinct facets of PCB power integrity (DC and AC) respect the design specification, suggesting updates where needed as part of the cost reduction strategy.
  • Thermal analysis used to determine the exact size of heat sinks to ensure operation within the required temperature range. FloTHERM was used to simulate the thermal profile of each sensitive component, at PCB and complete systems level, especially during the preliminary phase of the design process to keep each device in the operating temperature range improving the PCB′s thermal reliability with the goal to reduce possible PCB re-spins due to thermal issues.
  • Signal integrity (HyperLynx SI) was used in the first stage of the project to characterize the critical HF signals. Each significant frequency type was simulated and recorded. When multiple drivers could be selected for a specific device, the full range of driver to receiver simulations were performed so that the overall design performance could be determined. These results were used to define the constraints for the board but the long term goal is to provide a database of response characteristics so that they can be used by engineers on future design work.
  • Xtreme design technology was utilized so that more PCB designers could work at the same time on the single database without work divisions or merge operations, keeping the constraints intact.
  • DFM verification by Valor NPI during the design process made it possible quickly send feedback to the PCB designer for updates or improvements before releasing the final database. This helped improve manufacturability and product quality.

Comments from the Judges:

  • “One serious board design!”
  • “They did a great job at describing the issues they face in the design. This is a high volume board that had to not only resolve the high level of signal speeds, current, and high pin count BGA’s, but address field repair and total cost reduction the first time out.“

16 December, 2014

Typically my blogs speak of PCB layout technology and the company I work for, but this one is a bit different.

During this season of reflection and celebration, I’d like to take some time to honor the special friends that have passed during the year. We place these friends and our fondest thoughts “into memory,” in hopes to keep their legacies alive. I’d also like to recognize another great PCB designer who is retiring.

As some of us near, or have reached the age where we think of new things to do with our time, it’s nice to look back on this industry which has provided financial well-being, some very good memories, and many opportunities to work with fantastic, like-minded individuals.

In Memory Of

Dieter BergmanThis year we lost a pillar in our industry – Dieter Bergman (82). His career spanned 56 years and he has been hailed as a “true pioneer in the industry,” as well as “the heart and soul of the IPC Designers Council.” I met him once during my career, at the PCB West Conference, and I was able to witness first-hand the many “Dieterisms” he became so famous for.

Dieter became the driving force for technical standards through the IPC Designers Council, and produced many workshops on PCB design and fabrication. Dieter is survived by his wife, two sons, and a daughter. He will be greatly missed.

Art Morimitsu

On a more personal note to me, I recently heard that Art Morimitsu passed away. Art was a PCB designer at Pal Pilot in Irvine, California. He was a great PCB designer and friend, and I first met Art in my PCB design class in technical school. He was also my college roommate. Art was the first Japanese Cowboy I ever met, as he hailed from Boulder, Colorado.

A soft-spoken gentleman that never complained, he became one of the many PCB design friends I have made in this industry. We lost him too soon and he will be missed. Here is a great shot of Art doing what he loved most when he was not designing printed circuit boards.

Retirement Best Wishes

On a happier note, we are losing another great PCB designer from our ranks after 46 years of dedicated service. Larry Baggs, shown here second from the right, has been around a long time and has been a friend and colleague to many. He has decided to hang up his PCB design hat and spend his days travelling and enjoying life. I have had the pleasure to work with Larry and his dedication to PCB design and library creation has benefited several companies throughout his career. Please join me in wishing Larry a great retirement!

Larry Baggs and Group

These are only a few, and I am sure there are more that many of you would like to recognize. Please do so in the comments section, as I would love to hear the memories and stories that make our jobs so much fun – yes, I said fun!

There is also a link listing some of the colleagues we lost in the past year at the Printed Circuit Design and Fab website.

Happy Holidays, and my wishes for a very Happy New Year.

4 December, 2014

As I sit here still recovering from the Thanksgiving feast of turkey and all of the trimmings, I am reminded that this is the time of year we give thanks and gifts to our friends and loved ones. Christmas is just around the corner, and the holiday season is in full swing.

Speaking of giving thanks…I’d like to thank you for following along with me here on the blog! I also have an exciting announcement - the new Xpedition® VX.1 release is here!

Xpedition Enterprise

This release was created with thoughtful consideration of the challenges faced by our users. Over the past six years, thousands of engineering man hours have gone into creating a release packed full of innovation and new capabilities that benefit current users and new users alike. This is the most significant release in Mentor’s history.

We developed Xpedition VX.1 to address the challenges of companies like yours: modern enterprise development organizations that are coping with increasing design complexity as they expand into multi-board systems and manufacturing prep with integrated new product introduction.

Built on a hub-and-spoke architecture, Xpedition VX.1 enables unprecedented collaboration throughout the development ecosystem for multiple-discipline engineers and supply-chain partners, while maintaining design data integrity.

Packed full of new features including an intelligent user interface, group planning and placement, sketch routing technology, and integrated 3D PCB layout, this new version has been a hit with beta testers worldwide.

Now that it is available to everyone, we are looking forward to hearing what you think of it!

To find out more about this exciting new release, take a look at the Xpedition Webinar series. Downloads of Xpedition VX.1 (32 bit and 64 bit versions) are available now at http://supportnet.mentor.com/.

From myself and everyone at Mentor – we wish you a very safe and happy holidays, and a very happy New Year!

18 November, 2014

In my last post I mentioned my recent conversation about autorouting with several PCB designers at the IPC Council meeting in Irvine, California. Take a look at the previous post, Auto Assisted Routing: “I ain’t got time for that!” You will see that there are mixed feelings about autorouting, and many think we needed something better.

The IPC meeting that I’m referring to happened to be all about routing technology that is currently available and there was more than one vendor in attendance to present their wares. I got to go first, and I proposed a question.

I showed them a design with two FPGAs and 120 twisted netlines connected between them and asked, “How fast could you route these netlines?” The answers around the room ranged from 30 minutes to an hour. I selected the netlines, started the Sketch Router with a click, and said, “What if you could route them in one minute?” As the routes completed, I knew I had their undivided attention.

Before Routing:

FPGA Challenge: Before Routing
After Routing:
FPGA Challenge: After Routing

As a PCB designer, I consider myself an artist as I create beautiful artwork for the products of the future. For the younger PCB designers in the room, I explained that what we output to manufacturing in the past was actually called “artwork.”

As the show continued, I used my cursor like a painter uses a brush to select and route netlines and groups of netlines. First, I showed a DDR3 circuit that I routed in less than four minutes. Then, a PCIe circuit with differential pairs that I easily routed in about two minutes – including the matched length tuning. I moved around the design with the ease of routing with an autorouter while maintaining complete user control. The routing method utilized my intent and direction, but the algorithms gave me the speed and quality of a manually routed design. If I made a mistake, a quick undo allowed me to reroute entire groups of netlines in seconds. Take a look at the links below to see some of the circuitry I routed.

I wowed the room to a point of silence, and then I posed a second question:

“For those of you who said you do not use autorouting, would you use this autoroute method on your designs?” The unanimous response was “YES!”

So, you provide designers with an autorouting method that is easy to use, and uses the designer intent, they will use it.

Sketch Router is a new paradigm in auto assisted routing. I believe it to be the next big step for designers to provide fast, high quality designs – all with the look and feel of a completely hand-routed design.

One more thing about the IPC meeting…

Many thanks to those who came to me after the meeting and made statements like these: “The other guys should have been embarrassed to show their tools; they did not route a single trace, while you routed a huge portion of your design in under 20 minutes!”

It’s great to hear my colleagues say that they truly believe this is a game changer in the PCB Design industry. I agree! What do you think?

Videos:

Sketch Routing Demo

Routing and Tuning DDR3 in Under Three Minutes

27 October, 2014

When tuning a set of nets in Xpedition Layout, there are methods to do it automatically or manually – or both. The previous post in this routing series explored the use of Auto Tune and the Target Lengths dialog. In this post, we will look at the manual tuning features and the options available for using them in a productive manner. The intent here is to reveal the new capabilities in the context of the existing ones.

Discovering What Needs to be Tuned

Normally designers will focus on resolving routing timing challenges circuit by circuit, interface by interface. Discovering what needs to be tuned is just a reflection of knowing the circuit and proceeding to adjust the lengths to follow the rules. However sometimes – especially at the end of the design process, it is good to review all the nets to be tuned and determine if they fulfill the rules. There are a number of enhancements for doing this in Xpedition Layout, and each one has its own value.

Net Explorer:

This dialog automatically organizes the nets that have rules assigned in CES into groups. The Tuned Nets group lists all the nets that have delay rules that can be resolved by tuning. The Matched Length group lists each matched length set as defined in CES, and organizes them by the user defined ID. This is a quick way to see which nets have tuning requirements. Using other features like Cross-probing and Marking allows you to easily find and isolate them in the graphics window. When a net or group of nets are marked, you have options in Display Control to display just the netlines for those nets.

img1

Target Lengths:

In my previous post, this dialog was described in some detail. In the context of manual tuning, the best thing is that you can see which nets still need to be tuned in a given cluster; and the fact that it is updated dynamically as you modify lengths in the graphics.

img2

Tuning Meter:

Using the Tuning Meter is the best way to get instant feedback on length adjustments. The Target Lengths dialog is dynamic; however, it is not as instant as the Tuning Meter which is updated with even the smallest movement of the cursor. As you drag on a segment or the pattern box, the tuning meter will tell you exactly where you are within the range defined by the tolerance. It works when making Phase Matching adjustments as well.

img3

Hazards:

The Hazards dialog provides a way to find any remaining nets that need to be tuned. This is especially useful when at the end of the design when you want to find any last remaining tuning that is needed.

  • Differential Pair Length and Phase Matching – The Hazards dialog is the only way to find the nets that still need length or phase matching to fulfill the CES rules. Once you find a hazard for diff pair length tolerance or phase matching, you can select the Resolve button which will add a sawtooth or uncoupled pattern to automatically adjust the length to remove the hazard.

DifferentialPairLengthTolerance

img4

Adding Manual Tuning Patterns

There are a number of different ways to add tuning patterns and it is important to control what the initial pattern looks like when doing so. Selecting one of the toolbar icons is a very quick way to add a pattern.

Tuning Dialog:

When a tuning pattern is added, it follows the rules setup in the Tuning dialog. You can modify it after it is added, but the initial pattern style is controlled by this dialog.

TuningPatterns

Manual Tune Icon:

manualtuneicon

When you select a trace, this icon becomes sensitive and when pressed, it will add a tuning pattern that obeys the rules setup in the Tuning dialog and it will obey the Push and Shove settings in the Editor Control dialog. If you don’t want the new tuning pattern to disturb existing routing, turn Trace Shove off. When the tuning pattern is added, it also obeys the other Push & Shove settings, including Via Shove, Via Jump and Pad Jump.

  • With Trace Shove Off:

TraceShoveOff

  • With Trace Shove On:

TraceShoveOn

Interactive Tune:

InteractiveTune

If you select the Interactive Tune icon, the dialog will open. In previous releases, this feature was part of the Smart Utilities but now it is included in the standard Tune Routes functions. The general methodology is to define the tuning parameters and when you click “Tune” you can then select a trace to add that tuning pattern.

InteractiveTuneDetail

Sawtooth:

Sawtooth

Adding a sawtooth pattern is a new capability in Xpedition Layout. It is used for diff pair balancing to fulfill either the Differential Pair Tolerance (length matching) or the Differential Pair Phase Tolerance (phase matching) rules set in CES.

DiffPairTolerance

The Differential Pair Tolerance rule defines the allowable length or delay difference for the total length of the differential pair routing.

The Differential Pair Phase Tolerance is expressed by two values: First, the maximum tolerance, and second the maximum distance for that tolerance to be applied. For example, you can say that a tolerance of .24mm is allowed over a distance of 12mm. That means that as you traverse the route from source to load, for each 12mm of distance, the diff pair compliments must have lengths within the .25mm tolerance.

In the Tuning dialog, you define the parameters for the sawtooth pattern.

SawtoothPattern

Editing Patterns

Once a pattern is added, you can edit it as a pattern when the box around it is visible as shown here.

EditingPatterns

At this point you can either stretch the pattern (using the handles) or move it by dragging your cursor on the box outline. This kind of editing will obey all the settings for Gloss as well as Push & Shove in from the Editor Control dialog. If you don’t want other traces affected by your editing, turn off “Trace shove” in the Push & Shove section.

EditRouteControls

There are two modifiers available when editing tuning patterns. These options are shown in the text field when editing a tuning pattern.

AltDrag

Editing Individual Segments:

You can also edit the individual parts of the tuning pattern, but first you must flatten the pattern. It can be flattened either by using the RMB menu or by holding down the Ctrl key when dragging on a trace segment.

Changing to Arcs:

If you have a pattern that was originally added with chamfers and you want to change it to a pattern with arcs, you need to change the Tuning dialog to turn on arcs, delete the original pattern and then re-add it.  Another method would be to use the Modify Corners dialog, but that will flatten the pattern first.

Deleting a Tuning Pattern:

Select one of the handles and drag it as shown in the image below until the pattern disappears.

DeletingTuningPattern

Conclusion

What methods do you like for adjusting the length of the traces? Did I leave anything out? I believe what is important is to discover the methods that get your desired results as quickly as possible. We continue to enhance our tuning capabilities and would like to hear your feedback.

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