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Get Ready for SystemVerilog 2012
The latest revision of the IEEE 1800-2012 SystemVerilog Language Reference Manual (LRM) is about to hit the press; though I doubt people will be printing the 1300+ pages on their own from the soon to be readily available online version. Here’s a little background into what’s in all those pages.
The first SystemVerilog LRM came from Accellera in 2002 as a set of extensions to the IEEE 1364-2001 LRM. This first LRM was called version 3.0 because it was considered the third generation of Verilog. Accellera released a few more versions and turned version 3.1a over to the IEEE in 2004. The IEEE released the 1800-2005 SystemVerilog LRM as a set of extensions to the 1364-2005 Verilog LRM, which became the last revision of the 1364 LRM. Four years later, the IEEE combined the SystemVerilog extensions with the Verilog LRM producing a single 1800-2009 SystemVerilog LRM.
Now, a short three years later, the SystemVerilog IEEE 1800-2012 LRM is ready having addressed 225 issues. The majority of these issues are clarifications and corrections to the existing LRM. However, a few enhancements ranging from the simple 
removal of the restriction on non-blocking assignments to class members to the major addition of multiple class interface inheritance made their way into the new LRM. A number of those enhancements will undoubtedly be presented at the upcoming Design & Verification Conference.
I’d like to demonstrate two enhancements that should be of value to most verification engineers. They address two of the more commonly asked SystemVerilog questions I receive: How do I generate an array of unique values? and How to I create covergroup bins to get toggle or one-hot functional coverage?
Generating unique array of random values
Many verification scenarios require creating sets of random instructions or addresses with no repeating values, usually represented as elements in a dynamic array. Earlier versions of SystemVerilog required you to use either nested foreach loops to constrain all combinations of array elements so that they would not be equal to each other. Or else repeatedly randomize one element at a time, and then constraining the next element to not be in the list of already generated values.
The new unique constraint lets you use one statement to constrain a set of variables or array elements to have unique values. When randomized, this class generates a set of ten unique values from 0 to 15.
You can also add other non-random variables to the set of unique values which has the effect of excluding the values of those variables from the set of unique values. When randomized, this class generates a set of ten unique values excluding the values 0, 7 and 15.
Complex coverpoint bin expressions
The previous SystemVerilog syntax for specifying functional coverage bins was very limiting. Unless you could explicitly state the individual bin values or range of bin values in your coverpoint definition, or could figure out a way to instantiate multiple copies of your covergroup passing in a different bin value as an argument, you were out of luck. This also made defining coverage crosses extremely difficult.
The new SystemVerilog bin syntax lets you specify a bin expression that is evaluated over the range of possible values of the coverpoint expression. The bin expression acts like a constraint, and the set of coverpoint values where the bin expression is true become the set of bins. The coverpoint below generates as set of bin values between 0 and 127 that are divisible by 3. The range is 0 to 127 because sbyte is a 7 bit variable.
Probably the most powerful feature is the coverpoint bin set that simply allows you to define an array of values that you want as bins. This is useful for specifying one-hot encodings, toggle coverage of a register, or any complex algorithm that can generate the set of bin values you want. The code below builds a list of onehot values in the encodings array, and then constructs the protocol_cg covergroup using the array as a set of bin values.
Available in the latest version of Questa
By the way, every feature discussed in this post is available in the latest version of Questa, 10.2.
Tags: Constrained Random Test, functional coverage, SystemVerilog, Verification
VHDL Update Comes to Verification Academy!
VHDL-2008 Explained Via 7 Course Modules
For some time now a dedicated group of engineers have defined and standardized an important update to the VHDL standard. Also know as IEEE Std. 1076™-2008, this update to VHDL took an interesting path to get to where it is today. The VHDL standards team started the standards development work in the IEEE but sought additional input and standards project funding from industry. Accellera provided a good venue in which to get industry input and feedback for an update to the VHDL standard along with funding. Once industry input was taken into account, the proposed update to VHDL, approved by Accellera, was returned to the IEEE for official standards ratification and ongoing maintenance. Jim Lewis, the IEEE VHDL Working Group Chair, points out this is the greatest update to VHDL since VHDL 93. And I agree. Jim is also the subject matter expert for the VHDL-2008 course modules on Verification Academy mentioned in this blog.
Verification Academy Modules
In less than an hour and half – over 7 course modules – Jim will layout out the additions and changes to VHDL-2008 to simplify the language and extend it to address more of your pressing design and verification challenges with the addition of reusable data structures, simplified RTL coding and the inclusion of fixed and floating point math packages.
As part of my role in international standardization as co-convenor of the IEC TC 93 WG2 (now known as IEC TC 91 WG 13) and in keeping with the IEEE/IEC dual-logo agreement, I helped complete the dual logo process for this version of VHDL in 2011. VHDL-2008 is also now known as IEC 61691-1-1-2011 – Behavioural languages – Part 1-1: VHDL Language Reference Manual. I think we can all agree that that name is a bit much that we can simply call it VHDL-2008.
With this round of standardization complete, the VHDL-2008 course modules arrive just as complete support for VHDL-2008 emerges here at Mentor Graphics in our ModelSim and Questa products.
I encourage and invite VHDL users to get acquainted with VHDL-2008 via the seven course modules on Verification Academy. Verification Academy “Full Access” membership is required. And it is easy to sign up (certain restrictions apply). For a quick look at what the courses offer, the introduction page found here will show you more details about the following modules.
| “VHDL-2008 Why It Matters” Modules | |
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Additional Reference Material
There is additional reference material you may wish to have to get the most out of VHDL-2008. Here is my short list:
- IEEE Std. 1076-2008 Language Reference Manual (Click here)
- VHDL-2008: Just the New Stuff (Click here)
- The Designer’s Guide to VHDL, Third Edition (Click here)
Tags: iec, IEEE 1076, Verification Acdemy, vhdl
IEEE Approves Revised SystemVerilog Standard
IEEE Std. 1800™-2012 Officially Ratified
The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard. The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.
What’s New?
The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification. DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard. The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics). You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.
For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance. As Stu and Tom said in their presentation, “This is BIG!” If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.
Major work was done to augment the current notion of constraints in SystemVerilog. In past versions of the standard they were known as hard constraints. What this meant was all the conditions of the constraints had to be met otherwise there would be an error. There was no built-in method to relax the need to satisfy the constraints. Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high. To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard. If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard. Stu and Tom said that “This is also a big enhancement!”
Availability
IEEE 1800™-2012 has only now been approved. The standard itself is not ready to be published yet. Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013. I will share publication information as it becomes available. And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.
While the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now. For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more. You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well. You can find more information about it on Amazon.com here.
The Story Continues…
There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead. The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.
Stay tuned! For now, I encourage you to get informed!
Tags: 1800, Assertions, Ben Cohen, DASC, dvcon, Hard Constraints, IEEE SASB, IEEE-SA, Muttiple Inheritance, RevCom, Soft Constraints, Standards, Stu Sutherland, SystemVerilog, Tom Fitzpatrick, UVM
Coverage Cookbook Debuts
Verification Academy Adds Major New Technical Resource
The Verification Academy adds another major methodology cookbook to focus on effective coverage adoption. The Coverage Cookbook describes the different types of coverage that are available to track your verification process progress, how to create a functional coverage model from a specification, and provides examples to implement functional coverage for different types of designs.
Verification Academy “full access” members have access to the free Coverage Cookbook and the UVM/OVM Cookbooks as well. Are you a registered full access member? If not, register now to become a full access member. (Restrictions apply.)
Coverage is not a new topic. It was one of major additions to the SystemVerilog (IEEE Std. 1800™-2009) standard. But the SystemVerilog functional coverage extensions were left to the verification engineer to use in such as way to return meaningful measurements of how much of the design specification was being tested. The Universal Verification Methodology (UVM) offers greater structure for coverage over SystemVerilog, but it too, is still only a piece of the puzzle.
As verification teams have come to generate greater amounts of information from use of SystemVerilog, UVM and other verification tools, the data from the verification runs needs to be easily used to drive coverage closure. Within the Mentor Graphics Questa verification platform, this resulted in the development of the Unified Coverage Database (UCDB) and associated verification management and planning features.
Since verification teams use a variety of tools and technology from many sources, it was an imperative that verification information could be easily shared and combined to help drive faster coverage closure across the industry. This is why Mentor Graphics donated its UCDB API to Accellera where it became the Unified Coverage Interoperability Standard (UCIS).
It would be great to think that we are done; but we’re not. Tools and data are just two dimensions of the three dimensions to any IC design project. A comprehensive approach to verification management that handles all of this adds the third dimension. The Mentor Graphics Questa Verification Management features handle all this.
Now the question is how to best adopt and use all the capabilities at hand from the standards to the verification technology at your finger tips.
The Verification Academy Coverage Cookbook is one of the important tools you now have to help pull all the information into a single place where you can learn the theory and put that theory into practice. The Coverage Cookbook is much like the OVM/UVM Cookbooks in that it is web friendly, while supporting the ability for you to generate a PDF file of the whole document in case you want to have a printed copy or have it available for offline reference.
The Theory section covers:
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The Practice section shows three examples you can use today:
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The Coverage Cookbook is a live document. You can expect continued extensions and contributions to enhance it. As Harry Foster, Mentor Graphics’ Chief Scientist Verification put it, “Methodology is the bridge between tools and technologies, which creates a productive, predictable, and repeatable solution.” We should expect that our collective use of this technology will help hone the methodology which is the heart of the Coverage Cookbook. And with this use, we should expect the Coverage Cookbook to evolve as we achieve greater verification productivity.
Let us know what you think about the Coverage Cookbook and what we might be able to do to improve it. In the meantime, Happy Coverage Closing!
Tags: accellera, Coverage, Coverage Closure, Coverage Cookbook, functional coverage, Harry Foster, IEEE 1800, OVM, SystemVerilog, UCDB, UCIS, UVM, Verification Academy
IoT: Internet of Things
Ready for 100 billion “things” connected by the Internet?
The IEEE Standards Association (SA) Corporate Advisory Group (CAG) has been working to bring industry input into the standards development organization on the emerging Internet of Things (IoT) trend that will connect billions of devices with each other.
As you can imagine, the impact this will have to the service structure down to the development of connected devices will have impact on tools used to create, verify and test them from the EDA industry to the protocols that will need to be in place to facilitate this.
This past summer the oneM2M was launched to bring some groups together who were dedicated to product technical specification for the M2M Service Layer. The impact on the IEEE, that is responsible for ongoing Internet standardization, is likewise large and not totally known.
I was reminded of the IoT impact this week by ARM’s EVP, Simon Segars. His ARM Techcon keynote presentation this week. noted the IoT is a merging of our digital and physical worlds. He also said predictions are the data from smartphones is “exploding at a 100% growth rate a year for the next 4-5 years.” To make the point even more stunning, Simon shared that Facebook expects 1-2 billion pictures will be taken and uploaded to their website around Halloween 2012. The good news for those who did not have the time to make it to Santa Clara, CA USA for ARM Techcon, his presentation has been made available for viewing on YouTube. You can find it here.
The IoT conversation continues around the globe.
IEEE IoT Workshop: You are invited!
IEEE has restored service to their Internet connection at www.ieee.org. However, connection from IEEE staff locations is tentative due to the widespread devastation of Hurricane Sandy in the New Jersey USA area where they live and work. There may be delays in getting official invitations out on the IoT workshop. The IEEE workshop on Internet of Things has been put together in conjunction with several of the CAG member companies, with direct leadership from our STMicroelectonics representative and input from representatives from Broadcom, GE Medical, Ericsson, Qualcomm and others. The IEEE SA staff and IoT Workshop leadership have asked those who are connected to share workshop information. I am doing that here.
You are invited to attend and participate in the workshop. Details on the event are:
Event Description:
The event will feature a combination of keynote speeches, product showcase and panel sessions with the goal to:
- identify collaboration opportunities and standardization gaps related to IoT
- help industry foster the growth of IoT markets;
- leverage IEEE’s value and platform for IoT industry-wide consensus development,; and
- help industry with the creation of a vibrant IoT ecosystem.
Date: 13 November 2012
Location: Milan, Italy
Fee: Free
Keynotes include:
- Service Provider’s View of the IoT World (SP)
- End to End Systems Security (ST)
- IEEE-SA – Perfect Platform for the New Millennia of Consensus Development
Panel Topics include:
- GW as an Enabler of the New Services in the IoT World
- Monetizing Services in the IoT World
- Security in the IoT World
- Standard, what we have and what is missing, convergence in the technology world, collaboration opportunities.
Website: http://standards.ieee.org/events/iot/index.html
| WEATHER ALERT! 31 October 2012 4:25 p.m. PDT Access to ieee.org has been restored. That was quick! You can now access IoT Workshop details from IEEE directly. 31 October 2012 3:00 p.m. PDT Due to the impact of Hurricane Sandy, power to IEEE servers has been lost and backup power sources have been depleted. Access to the IEEE website for more information, registration and additional details is not available at this moment. The workshop will be held.If the servers return to the Internet, I will update this notice.And if their absence appears to be something that will last longer than another day or so, I will update this blog with alternate contact information for those who would like more detailed information on how to register and where to go to attend the event. |
Tags: ARM, ARM Techcon, IEEE, Internet of Things, IoT, oneM2M, Standards
Check out the October, 2012 Verification Horizons
Hi Everyone,
Just wanted to let you know that the latest and greatest edition of Verification Horizons is now available. The articles in this issue all discuss how you can apply new techniques and technology to achieve greater verification productivity. And for you football (I mean “American football” as opposed to “soccer”) fans out there, be sure and check out the Editor’s Note.
If you’re not already receiving Verification Horizons, you can sign up here.
Improving simulation results with formal-based technology
When it comes to formal methods, many engineers are skeptics. Perhaps this is due to value propositions that have been pitched over the years that have over-promised yet under-delivered in terms of results. Or perhaps it is due to the advanced skills that have traditionally been required to achieve predictable and reliable results. After all, historically this was the case—dating back to the mid-nineties when formal techniques were only adopted by companies that could afford a dedicated team of formal experts with PhDs.
So, what’s changed today? The emergence of functional verification solutions targeted at specific problem domains, which blend simulation with formal-based techniques in a seamless way to improve results. In other words, the application of formal-based technology is not just for experts anymore! In fact, everyone can reap the benefits of formal analysis today with very little effort.
One example of this blending of simulation with formal-based techniques is in the area of accelerating the process of code coverage closure with the new Questa CoverCheck solution. Closing code coverage typically involves many engineering weeks of effort to manually review code coverage holes to determine if they are unreachable and can be safely ignored—or figuring out exactly how to handcraft special tests to cover them during simulation. Questa CoverCheck makes it easy for non-expert users to leverage formal-based technology to complete this process by automatically identifying the set of unreachable coverage items in a design, and then guiding the user to create tests for the reachable items that have not been covered yet. This process, illustrated in the figure below, is push-button, low-effort, and requires no expertise with formal techniques. In addition, no assertions are required nor expertise in assertion languages. It is a beautiful example of how formal-based technology is blended with simulation to form a solution that improves both productivity and quality of results.
Another example of how formal-based technology is being used today to complement simulation is with AutoCheck, which is part of the Questa Formal solution. For example, there is a class of bugs that cannot be found using RTL simulation due to a simulation effect known as X-state optimism. These bugs might be found during gate-level simulation, but this occurs very late in the design flow when it is costlier to fix. By using AutoCheck, engineers are able to identify and correct X-state issues early in the design flow, before simulation occurs. In addition to X-state issues, AutoCheck uses formal-based technology to verify a wide range of common RTL errors that are difficult or impossible to find during RTL simulation. It is another example of a push-button, low-effort solution where assertion-language and formal expertise is not required. What’s new in the latest Questa Formal release is significant improvements in engine performance and capacity, along with multicore support.
Questa CDC is one more example of how formal-based technology is being used today to complement simulation. Today, we see about 94% of all designs have multiple asynchronous clock domains. Verifying that a signal originating from one clock domain will safely be registered in a different asynchronous clock domain is not possible using traditional RTL simulation since state element setup and hold times are not modeled, which means that metastability issues will not be verified. Again, these bugs might be found later in the flow during gate-level simulation where it is costlier to fix. Static timing analysis, although effective at finding timing issues within a single or synchronous clock domains is unable to identify issues across asyncrhonous clock domains. This is an area with formal-based technology, such as Questa CDC, can help. What’s new in the latest Questa CDC release is support for unlimited design sizes through hierarchical CDC analysis along with a 5X improvement in performance.
To learn what’s new with Questa Formal-Based Technology, see our recent press release. Or check out the Questa Cover Check, Questa CDC and Questa Formal links.
Tags: formal verification, functional verification, Simulation
Introducing “Verification Academy 2.0”
A new style takes center stage
It was Fashion Week in Portland, Oregon in early October. And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was. What struck me was the blend of fashion with high tech this year. Intel took the opportunity to roll out its fashion inspired campaign (dressing room mirror sized tablets) and Mitsubishi used it to launch its new electric vehicle (named MiEV in case you did not know). Certainly it was more than just your run-of-the-mill runway show. But that was not the only thing “getting some style” here in the Portland area.
The Verification Academy team at Mentor Graphics has been working hard as well to restyle the Verification Academy website, modernize it and make content easily accessible. It made its debut in late September, a few weeks before the Portland Fashion Show. While these two things are a coincidence, the focus on a refreshed style should not to be totally unexpected.
Some of the changes just had to be made given the success of the Verification Academy. When it started a few years back, Harry Foster (the face in the picture of the Verification Academy website above) knew the adoption of advanced technology was hampered by unequal and slow distribution of knowledge. Part of the Verification Academy’s thrust was to bring information about advanced verification topics to the whole world in a format that could be easily used. The content comes from respected verification subject matter experts and the first “runaway success” was the Open Verification Methodology (OVM) training by John Aynsley from Doulos for the “basic” module and Tom Fitzpatrick from Mentor Graphics for the “advanced” module. The Universal Verification Methodology (UVM) course, likewise, has also joined the ranks of the highly watched. Updates to the Academy improve the services to deliver video.
We have moved to the most current web video protocols that allow modern browsers and mobile devices to easily access course content. You can watch courses on the “smaller” smartphone screens to the largest of TV displays with SD and HD video to support your viewing preferences. Since content is delivered in native web technologies, users do not have to depend on Flash or other plugins.
We have also migrated the Academy to the leading open source content management system and adopted the use SSL throughout the Verification Academy to make it more secure.
When we first started the Verification Academy, we did not know how large the community would grow nor could we predict the demands the community would place on the resources to support it. Today, there are almost 12.5K users making it the largest single site to support the verification professional. The changes we have made to the internals of the site show a speed improvement of over 400% by exploiting a commercial content delivery network to handle large media.
And for many members, where English is a second language, the video captions, when offered, are in plain text. Registered users can click on the picture to the right to see the UVM Introduction and enable closed caption to see how the text appears right below the video. (Or, from reading the text below video in the picture to the right, you can see John is introducing himself at the moment of this screen capture.)
We have also made big improvements to searches. The searching facility now scans across all content at once, from the forums, to the UVM/OVM Cookbook and presents the information to you in an improved way to allow you to filter the results to focus on just that you want to know.
Want to experience the new Verification Academy 2.0 style? Click here to go to the Verification Academy to see these changes and discover these and other changes yourself. Share your comments with me on what you think. Have we made it better for you? And if not, what more can we do to improve your experience even more?
Tags: OVM, UVM, UVM Cookbook, Verification, Verification Academy
OVM Gets Connected
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
OVM Thrives
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
Download
The UVM Connect 2.2 kit supports multilingual use of OVM and can be found at the Verification Academy and the Accellera UVM World contributions download site.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Tags: 1666, 1800, accellera, IEEE, Multilanguage OVM, Multilanguage UVM, OVM, Standards, systemc, SystemVerilog, UVM, UVM Connect
OpenStand & EDA Standardization
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards”
The EDA industry has seen changes to the international standards paradigm the past few decades. When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version. In addition to anchoring the standard at the IEEE, collaboration with the IEC for international standardization and recognition with the one-country, one-vote process set the stage for international approval of VHDL.
In the early days of Verilog, I encouraged similar support for that IEEE standard. But its support was not immediate and to some may have failed to track the pace of support by industry. Indeed, with Accellera developing SystemVerilog, later to become an IEEE standard and IEC standard, what was missing was the close link between a global industrial community and the international setting in which the standard was developed and deployed.
In the case of SystemVerilog, global markets drove the international deployment of the standard without respect to its formal status. Indeed, on what was called the “birthday” of SystemVerilog in Japan, the day it was approved as an official IEEE standard, the Japanese National Committee on standards hosted an open celebration that I was invited to attend. There was no waiting on their part the formal status. The interdependencies of global design, global commerce and global partnerships have driven all of us to adapt the standards development process for EDA.
On the eve of OpenStand’s launch, it is good to see the IEEE, Internet Society, W3C, IAB and IETF come together to put in writing what is the emerging practice for EDA.
You can learn more about the supporters of OpenStand, their guiding principles and how you can give your input, comments and feedback by visiting their website at http://open-stand.org. And if you agree, you can even “stand” with them; with me; with us.
But in short, OpenStand promotes a standards development model that demands:
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Tags: accellera, IAB, iec, IEEE, Internet Society, ITEF, OpenStand, Standards, SystemVerilog, vhdl, W3C
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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