Verification Horizons BLOG

Part 1: The 2012 Wilson Research Group Functional Verification Study

Design Trends In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs. This blog begins the process of revealing the 2012 Wilson [...]

What’s the deal with those wire’s and reg’s in Verilog

A unique concept most beginners have trouble grasping about the Verilog, and now the SystemVerilog, Hardware Description Language (HDL) is the difference between wire’s (networks) and reg‘s (variables). This concept is something that every experienced RTL designer should be familiar with, but there are now many verification engineers with no prior Verilog experience trying to [...]

Getting AMP’ed Up on the IEEE Low-Power Standard

Power Aware Verification Course Modules Released I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one [...]

Prologue: The 2012 Wilson Research Group Functional Verification Study

This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study. Study Overview In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in [...]

Even More UVM Debug in Questa 10.2

We’re really excited about the recent Questa 10.2 release, and I’m sure you’ll be just as excited when you check it out. For you UVM-philes out there, we’ve extended our industry-leading UVM Debug features to make your life even easier. I’ll present a quick overview of the new features here, but you’ll really want to [...]

IEEE Approves New Low Power Standard

IEEE 1801™-2013 Enters Pre-Publish Phase The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now. Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013). The IEEE SA’s Review Committee (RevCom) unanimously recommended [...]

Verification Horizons DVCon Issue Now Available

Hi Everyone, Just wanted to let you all know that the new issue of Verification Horizons is now available. You can get the full edition online at the Verification Academy. Please be sure to check it out. There are a few articles in particular that I’d like to call your attention to. Using Formal Analysis [...]

Get your IEEE 1800-2012 SystemVerilog LRM at no charge

Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program. As I posted a few weeks ago, the 1800-2012 is not a major revision of the [...]

IEEE 1800™-2012 SystemVerilog Standard Is Published

Download the standard now – at no charge! The IEEE has published the latest update to the SystemVerilog standard. And courtesy of Accellera, the standard is available for download without charge directly from the IEEE. The latest update to the SystemVerilog standard is now ready for download. It joins other EDA standards, like SystemC in [...]

See You at DVCon 2013!

Learn about new standards, industry surveys and trends This year’s DVCon is set and if you have not yet registered, you can do it now – or just show up! If you want to secure seating at some of the Monday tutorial events, I strongly encourage pre-registration to ensure you can secure a seat. And [...]