Posts Tagged ‘vmm’
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.
To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:
Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Cost: Free; registration restrictions apply
Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Legacy set for replacement?
Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.
This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.
When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.
With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.
While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.
Why bring all this up?
We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.
In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.
In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?
I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.
In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and I think I have them all!
What was clear to me was the IEEE standard was not sufficient to practice or understand the standard. After all, examples were few and far between in the standard. And even if there were examples in the standard, you were reminded that they are not part of the official standard – or in standards-speak – they are nonnormative.
User groups were popular too and continue to be today. VHDL International (now Accellera) had this notion of local VHDL user group chapters. When it came time to drive adoption of the VHDL gate-level library standard (known as VITAL), I attended several user group meetings to share details on how to use the new standard. I even solicited the support of a VHDL notable to put together a seminar series that would help ASIC library makers build their libraries. We took the seminar around the world and met with all the top ASIC suppliers. We even took our product that implemented the standard to the Cloud – while we did not call it the Cloud at the time. We had a model validation service in the early days of the internet that could be used to run training examples to validate ones own understanding or even test models and concepts to see if they would work. Free evaluation software was still a thing of the future then. As one byproduct of that work, we did have one competitor inundate us with the 1000’s of VHDL tests. We did throttle back their access to be fair to the others. But at that time, we left few ideas unexplored on how to drive global use and adoption of that standard.
What I understood was crossing the chasm from standards development to practicing the standard meant we had to build the knowledge, expertise and confidence in the user community to help them accept the standard and adopt it. I also learned that the standards developing organizations were not the best equipped to help practice the standard. The simple reason for this is the SDO is in place to bring together competitors to collaborate on the development of the standard but not foster competition on algorithms to best use the standard. This is perhaps better said by Synopsys’ Karen Bartleson in her “First Commandment for Effective Standards: Cooperate on Standards; Compete on Tools.”
Today’s Challenges with UVM & OVM
We are at that chasm with Open Verification Methodology (OVM) and the Universal Verification Methodology (UVM) today. While some may suggest OVM & UVM sit in a homogenous world where it works the same everywhere, the effective practice of the standards is anything but that. There are competitive options for users to explore and they are not ideas best promoted by a standards group. Mentor’s Mark Olen points out the value of an advanced method to generate stimulus rather than relying on the methods built into OVM & UVM in his recent blog post. Mark shows how a user gains 10x-100x in efficiency all the while doing this from within their OVM or UVM testbench.
Mentor has thought long and hard about how to best get this information to users and how to help them practice OVM and UVM better than they can if they only had access to the lowest common denominator of information. We first did a blind survey to see what methodology the design and verification community was using now and what they were going to use 12 months from now to validate our focus on OVM and UVM. Mentor’s Harry Foster has shared a lot of detailed information on this already. If you have not read his blog postings on this yet, you should start with his prologue that outlines the survey.
The survey clearly showed that UVM was in its ascendency and OVM was going to maintain strong and growing domination into 2012. Other survey results also clearly point out that SystemVerilog is the language of choice. While the survey shows what the user is doing, the standards developers were all collaborating on UVM and giving little time to OVM.
A Little Attention Goes a Long Way
While users were focused on continued use of OVM and planning for major move to UVM in 2012, the community developing standards had all but shifted to UVM, seemingly abandoning OVM. OVM was in need of care and attention given its dominant position in planned and future use.
Mentor stepped into the breach and has brought OVM into a strong, user-centric home that preserves the OVM World openness and augments it with several levels of additional user benefits in the Verification Academy. It also joins OVM and UVM in a single location that would not be appropriate in a standards body. After all, UVM is the standard from Accellera, not OVM. The Verification Academy also opens the cross pollination of ideas between the OVM and UVM users so one group can learn from another. We also brought the SystemVerilog User Group (SVUG) into the forum as well since OVM and UVM are based on the SystemVerilog language.
As we brought all these groups together, we did get many questions about Verification Academy Access Levels. First off, we dropped the OVM World requirement to register to download OVM. UVM and VMM were allowing anonymous downloads, so we made it the same for OVM. Of the 15,000+ OVM World registrants, most registered to download OVM. Just as OVM can now be downloaded without registration, the forums can be accessed in read-only mode without registration as well.
For those who used their OVM World registration to post on the forum, we moved them to “Forum Only Access” members so they could continue their posting privileges. The highest level of membership is “Academy Total Access.” Membership at this level is restricted to those who give a valid business profile. It enables access to training material, courses and lessons to help build SystemVerilog, OVM and UVM skills. It also allows users to gain knowledge about the advance algorithms that can help them get the 10x-100x or more out of OVM and UVM over conventional use. Below is a table of Verification Academy membership levels and privileges:
|Observer||Read-Only Forum Access. Free OVM/UVM kit download. No registration required.|
|Forum Only Access||Post to Forum and contributions area. Registration with any credentials required.|
|Academy Total Access||Total access. All academy areas open for free use. Registration with valid business profile.|
The response to this has been outstanding. While we strongly urge those who wish to develop the UVM standard to visit www.accellera.org and its www.uvmworld.org site to monitor that work, Verification Academy seems to have a much larger community of users with which to interact. And we will keep the Verification Academy current with the most recent versions of OVM and UVM. As of late July 2011 we recorded the following statistics.
|Verification Academy Forum||5,476|
|UVM World Forum||685|
|VMM Central Forum||696|
We look forward to continue to develop the site and add to the richness of its content and continue to improve your experience with it. Your comments on how we can improve it are always welcome.
Language and Library Trends
This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here).
In my previous blog (Part 7 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present design and verification language trends, as identified by the Wilson Research Group study.
You might note for some of the language and library data I present, the percentage sums to more than one hundred percent. The reason for this is that some perticipant’s projects use multiple languages and multiple methodologies.
Let’s begin by examining the languages used for design, as shown in Figure 1. Here, we compare the results for languages used to design FPGAs (in grey) with languages used to design non-FPGAs (in green).
Figure 1. Languages used for design
Not too surprising, we see that VHDL is the most popular language used for the design of FPGAs, while Verilog and SystemVerilog are the most popular languages used for the design of non-FPGAs.
Figure 2 shows the trends in terms of languages used for design, by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected design language adoption trends within the next twelve months (in purple). Note that the design language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 2. Trends in languages used for design
Next, let’s look at the languages used for verification (that is, languages used to create simulation testbenches). Figure 3 compares the results between FPGA designs (in grey) and non-FPGA designs (in green).
Figure 3. Languages used in verification to create simulation testbenches
And again, it’s not too surprising to see that VHDL is the most popular language used to create verification testbenches for FPGAs, while SystemVerilog is the most popular language used to create testbenches for non-FPGAs.
Figure 4 shows the trends in terms of languages used to create simulation testbenches by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected language adoption trends within the next twelve months (in purple). Note that verification language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 4. Trends in languages used in verification to create simulation testbenches
Now, let’s look at methodology and class library adoption. Figure 5 shows the future trends in terms of methodology and class library adoption by comparing the 2010 Wilson Research Group study (in green) with the projected adoption trends within the next twelve months (in purple). Previous studies did not include data on methodology and class library adoption, so we are unable to show previous trends.
Figure 5. Methodology and class library future trends
The study indicates that the only methodology adoption projected to grow in the next twelve months are OVM and UVM.
Assertion Languages and Libraries
Finally, let’s examine assertion language and library adoption, as shown in Figure 6. Here, we compare the results for FPGA designs (in grey) and non-FPGA designs (in green).
Figure 6. Assertion language and library adoption
SystemVerilog Assertions (SVA) is the most popular assertion language used for both FPGA and non-FPGA designs.
Figure 7 shows the trends in terms assertion language and library adoption by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected adoption trends within the next twelve months (in purple). Note that the adoption of most of the assertion languages is declining, with the exception of SVA whose adoption is increasing.
Figure 7. Trends in assertion language and library adoption
In my next blog (click here), I plan to focus on the adoption of various verification technologies and techniques used in the industry, as identified by the 2010 Wilson Research Group study.
Tags: 1076, 1364, 1666, 1800, accellera, Add new tag, Assertion-Based Verification, functional verification, IEEE 1800, OVM, Standards, SystemVerilog, UVM, Verification Methodology, verilog, vhdl, vmm
The full statement can be read at EDA Cafe, click here.
The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology (OVM) can work together. This preserves the investments made to date by users of those two methodologies.
The joint statement also says the Accellera Universal Verification Methodology (UVM) is based on OVM 2.1.1 and firmly rooted in SystemVerilog. While we know today UVM is OVM 2.1.1 with a few small changes or additions, it is made clear that Accellera has just begun. What happens next is the topic of the Accellera breakfast meeting. (Have you registered yet for it?)
The joint statement asked these questions:
- If we fast forward by a year, what would UVM base class release X look like?
- What features should it have to solve the problems faced a year from now? 3 years from now?
- Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs?
- What specifically are we doing to improve our ability to find bugs in the design and then fix them?
What questions do you have? If you want to share them here, please do. If you cannot attend the breakfast in person, I’ll bring your questions along to ask and report back after DAC on what happened at the Accellera breakfast.
As I mentioned in a previous blog, the Accellera OVM/VMM Interoperability kit code that is a companion to the Verification Intellectual Property Recommended Practices (1MB PDF) was nearing readiness. As of today, it is now ready for download and use. With qualification tests run on verification platforms from the Big-3 EDA companies, no objection was voiced at a recent Accellera VIP-TSC meeting against it being released for general industry use and adoption.
Congratulations to the Accellera VIP-TSC for hitting this huge milestone!
This kit contains an OVM/VMM interoperability library that meets and exceeds the requirements recently approved by the Accellera VIP-TSC. It includes a growing collection of adapters and utilities that enable easy and flexible reuse of existing IP in both OVM and VMM environments. Both library’s use-models are fully preserved, and no modifications to existing IP are needed.
Team OVM has created a version of the VMM 1.1b kit that needs to be downloaded from OVM World to work with the Accellera interoperability kit. In addition to modifications needed to get VMM 1.1 in compliance with standard SystemVerilog and to workaround differences in simulator implementations, the VMM 1.1b kit also incorporates changes to enable interoperability with OVM.
To setup your environment requires making sure you have installed and are pointing to qualified versions of simulators, libraries, and utilities. The release notes and overview documentation contained in the kit offer full details on how to use the kit. Basic information is shown below.
The Accellera VIP-TSC welcomes suggestions for improvements to the Verification Intellectual Property Recommended Practices and Interoperability Kit. They should be sent to the VIP email reflector: firstname.lastname@example.org.
Users Can Start Migration to OVM Today
Accellera’s Verification Intellectual Property (VIP) Technical Committee (TC) co-chair issued a public status report that highlights the group’s progress on its first phase of work, the OVM/VMM Interoperability Guide and companion software interoperability kit, and its second phase of work, a common base class library (CBCL) with OVM as its basis.
As the market accelerated its adoption of OVM in 2009, a smooth exit for VMM developers and users became increasingly apparent.
To address the exit and facilitate a smooth transition, Mentor Graphics drove the first phase of the committee’s work to protect users’ prior investments in VMM-based VIP so they can be reused in OVM testbenches. The companion open-source interoperability kit works in Questa now and should shortly pass all tests in other industry verification tools as well as highlighted in the VIP-TC status report.
As the Big-3 EDA companies embraced the Accellera VIP-TC phase one project, the worst kept secret was OVM was, by necessity, running in all their verification tools.
Now that Accellera has selected OVM, all the reasons for VMM developers and users to plan and make the transition to OVM today are clear. Team OVM has made sure there is no need to wait to start your transition with a large resource base on OVMWorld.org to help.
- OVM Download – here
- OVM Documentation Resources – here
- OVM Recorded Webinar – here
- VMM that works with the Accellera Interoperability Kit – here
- Accellera Interoperability Kit – here
As Accellera holds meetings to discuss additional common base class library features, Mentor understands users have a need to get down to the business of verification today. The OVM Team has all the necessary elements on OVMWorld.org to make your transition smooth. You can start your transition today with confidence.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
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- December 2010 (2)
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- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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