Posts Tagged ‘VIP’
User Adoption of OVM Featured; Views on UVM Discussed
The Mentor Graphics user group meeting, User-2-User, in Santa Clara is all set. U2U will be held on 26 April 2011 at the Santa Clara Marriott and one of the tracks will feature functional verification after keynote presentations by Mentor’s CEO, Wally Rhines and Xilinx’s CTO, Ivo Bolsens.
Registration for the event is open and is fee-free. U2U includes a complimentary lunch, evening reception and raffle along with the technical program.
The functional verification track opens with a presentation by Mentor’s Steve Chappell on how Mentor is “transforming verification” followed by three user presentations. The three user presentations share a common theme that highlight how they have leveraged the Open Verification Methodology (OVM) to improve their verification productivity. A couple presentations will also offer their views of the Accellera Universal Verification Methodology (UVM).
For users interested in the most current information on adoption and use of OVM and UVM, connecting with other users is probably the best source of unbiased information available. Here are three presentations that can help you understand how three users get the most out OVM and UVM when coupled with Mentor technology.
Using OVM with Transaction and Emulation Based Simulation Acceleration
Galen Blake | Verification Lead | Altera
Using OVM (or UVM) with transaction and emulation based simulation acceleration platforms. The OVM library is not quite as well suited to transaction and emulator based simulation acceleration. This presentation examines the problems and approaches to address them.
Case Study “Proving OVM on a Real Design” – Testimonial by AppliedMicro
Shing Sheung Tse | Senior Verification Manager | AppliedMicro
This case study will present how APM overcame their verification challenges with Mentor’s advanced verification methodology and the decision to choose OVM. APM will also present their view on UVM.
Verifying Bus Bridges with Questa Verification IP
Sudararajan Haran | Verification Lead | Microsemi
Microsemi moved to OVM-based verification environments and decided to use industry standard VIPs as much as possible. This presentation will highlight Microsemi’s experiences using Mentor’s AHB and AXI VIP’s to drive the verification of our AHB_AXI and AXI_AHB bridges to a quicker completion.
The full statement can be read at EDA Cafe, click here.
The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology (OVM) can work together. This preserves the investments made to date by users of those two methodologies.
The joint statement also says the Accellera Universal Verification Methodology (UVM) is based on OVM 2.1.1 and firmly rooted in SystemVerilog. While we know today UVM is OVM 2.1.1 with a few small changes or additions, it is made clear that Accellera has just begun. What happens next is the topic of the Accellera breakfast meeting. (Have you registered yet for it?)
The joint statement asked these questions:
- If we fast forward by a year, what would UVM base class release X look like?
- What features should it have to solve the problems faced a year from now? 3 years from now?
- Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs?
- What specifically are we doing to improve our ability to find bugs in the design and then fix them?
What questions do you have? If you want to share them here, please do. If you cannot attend the breakfast in person, I’ll bring your questions along to ask and report back after DAC on what happened at the Accellera breakfast.
Download OVM Configuration and Virtual Interface Extensions from OVMWorld.org
Creating configurable testbench elements is critical for reuse. If you write some OVM code in one particular testbench and never intend to use it in any other testbench, then there is no need to make it configurable. As soon as you wish to take code and turn it into reusable IP which can be used in a variety of applications, not all of which are immediately known, then you need to think about how to make the code configurable. Making code configurable means that you need to think about the breadth of applications where it will be used and the degrees of freedom you want to make available to the user of this IP.
The author of any verification IP needs to think about how to make that VIP sufficiently flexible to be used in a variety of different scenarios. In order to achieve this, OVM components need to have a number of settings associated with which can be varied by the testbench integrator. These settings may include things such as error injection rates, protocol modes supported or not supported, whether an agent is active or passive, to name but a few.
Future OVM Directions
If you download the OVM Configuration and Virtual Interface Extensions, you will find information on future directions for OVM in the documentation directory. In particular, detaching the configuration scoping mechanism from the OVM component hierarchy is an active area of investigation which might enhance the existing configuration mechanisms in important ways. This would allow one to naturally use the scoping mechanism with “behavioral VIP,” such as sequences, in addition to the current “structural scoping” mechanism that works with OVM components.
Additionally, the current configuration database is limited to storing strings, integers, and objects derived from ovm _ object. Another area of active investigation is enabling the database to store values of any type to solve the efficiency problems when storing and retrieving integral types.
It is also possible to improve and expand the existing wildcarding mechanisms to deal with the full regular expression syntax.
We invite you to join us in the this endeavor and share your thoughts here or on OVM World. To get started, you can download the OVM Configuration and Virtual Interface extensions to learn more.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)