Posts Tagged ‘vhdl’
This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study.
In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 study, no other industry studies were conducted, which left a void in identifying industry trends.
To address this void, Mentor Graphics commissioned Far West Research to conduct an industry study on functional verification in the fall of 2007. Then in the fall of 2010, Mentor commissioned Wilson Research Group to conduct another functional verification study. Both of these studies were conducted as blind studies to avoid influencing the results. This means that the survey participants did not know that the study was commissioned by Mentor Graphics. In addition, to support trend analysis on the data, both studies followed the same format and questions (when possible) as the original 2002 and 2004 Collett studies.
In the fall of 2012, Mentor Graphics commissioned Wilson Research Group again to conduct a new functional verification study. This study was also a blind study and follows the same format as the Collett, Far West Research, and previous Wilson Research Group studies. The 2012 Wilson Research Group study is one of the largest functional verification studies ever conducted. The overall confidence level of the study was calculated to be 95% with a margin of error of 4.05%.
Unlike the previous Collett and Far West Research studies that were conducted only in North America, both the 2010 and 2012 Wilson Research Group studies were worldwide studies. The regions targeted were:
- North America:Canada,United States
- Asia (minusIndia):China,Korea,Japan,Taiwan
The survey results are compiled both globally and regionally for analysis.
Another difference between the Wilson Research Group and previous industry studies is that both of the Wilson Research Group studies also included FPGA projects. Hence for the first time, we are able to present some emerging trends in the FPGA functional verification space.
Figure 1 shows the percentage makeup of survey participants by their job description. The red bars represents the FPGA participants while the green bars represent the non-FPGA (i.e., IC/ASIC) participants.
Figure 1: Survey participants job title description
Figure 2 shows the percentage makeup of survey participants by company type. Again, the red bars represents the FPGA participants while the green bars represents the non-FPGA (i.e., IC/ASIC) participants.
Figure 2: Survey participants company description
In a future set of blogs, over the course of the next few months, I plan to present the highlights from the 2012 Wilson Research Group study along with my analysis, comments, and obviously, opinions. A few interesting observations emerged from the study, which include:
- FPGA projects are beginning to adopt advanced verification techniques due to increased design complexity.
- The effort spent on verification is increasing.
- The industry is converging on common processes driven by maturing industry standards.
My next blog presents current design trends that were identified by the survey. This will be followed by a set of blogs focused on the functional verification results.
Also, to learn more about the 2012 Wilson Reserach Group study, view my pre-recorded Functional Verification Study web-seminar, which is located out on the Verification Academy website.
Quick links to the 2012 Wilson Research Group Study results (so far…)
- Part 1 – Design Trends
Tags: accellera, Assertion-Based Verification, formal verification, functional coverage, functional verification, IEEE, Simulation, Standards, SystemVerilog, UVM, Verification Academy, Verification Methodology, verilog, vhdl
VHDL-2008 Explained Via 7 Course Modules
For some time now a dedicated group of engineers have defined and standardized an important update to the VHDL standard. Also know as IEEE Std. 1076™-2008, this update to VHDL took an interesting path to get to where it is today. The VHDL standards team started the standards development work in the IEEE but sought additional input and standards project funding from industry. Accellera provided a good venue in which to get industry input and feedback for an update to the VHDL standard along with funding. Once industry input was taken into account, the proposed update to VHDL, approved by Accellera, was returned to the IEEE for official standards ratification and ongoing maintenance. Jim Lewis, the IEEE VHDL Working Group Chair, points out this is the greatest update to VHDL since VHDL 93. And I agree. Jim is also the subject matter expert for the VHDL-2008 course modules on Verification Academy mentioned in this blog.
Verification Academy Modules
In less than an hour and half – over 7 course modules – Jim will layout out the additions and changes to VHDL-2008 to simplify the language and extend it to address more of your pressing design and verification challenges with the addition of reusable data structures, simplified RTL coding and the inclusion of fixed and floating point math packages.
As part of my role in international standardization as co-convenor of the IEC TC 93 WG2 (now known as IEC TC 91 WG 13) and in keeping with the IEEE/IEC dual-logo agreement, I helped complete the dual logo process for this version of VHDL in 2011. VHDL-2008 is also now known as IEC 61691-1-1-2011 – Behavioural languages – Part 1-1: VHDL Language Reference Manual. I think we can all agree that that name is a bit much that we can simply call it VHDL-2008.
With this round of standardization complete, the VHDL-2008 course modules arrive just as complete support for VHDL-2008 emerges here at Mentor Graphics in our ModelSim and Questa products.
I encourage and invite VHDL users to get acquainted with VHDL-2008 via the seven course modules on Verification Academy. Verification Academy “Full Access” membership is required. And it is easy to sign up (certain restrictions apply). For a quick look at what the courses offer, the introduction page found here will show you more details about the following modules.
|“VHDL-2008 Why It Matters” Modules|
Additional Reference Material
There is additional reference material you may wish to have to get the most out of VHDL-2008. Here is my short list:
- IEEE Std. 1076-2008 Language Reference Manual (Click here)
- VHDL-2008: Just the New Stuff (Click here)
- The Designer’s Guide to VHDL, Third Edition (Click here)
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards”
The EDA industry has seen changes to the international standards paradigm the past few decades. When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version. In addition to anchoring the standard at the IEEE, collaboration with the IEC for international standardization and recognition with the one-country, one-vote process set the stage for international approval of VHDL.
In the early days of Verilog, I encouraged similar support for that IEEE standard. But its support was not immediate and to some may have failed to track the pace of support by industry. Indeed, with Accellera developing SystemVerilog, later to become an IEEE standard and IEC standard, what was missing was the close link between a global industrial community and the international setting in which the standard was developed and deployed.
In the case of SystemVerilog, global markets drove the international deployment of the standard without respect to its formal status. Indeed, on what was called the “birthday” of SystemVerilog in Japan, the day it was approved as an official IEEE standard, the Japanese National Committee on standards hosted an open celebration that I was invited to attend. There was no waiting on their part the formal status. The interdependencies of global design, global commerce and global partnerships have driven all of us to adapt the standards development process for EDA.
You can learn more about the supporters of OpenStand, their guiding principles and how you can give your input, comments and feedback by visiting their website at http://open-stand.org. And if you agree, you can even “stand” with them; with me; with us.
But in short, OpenStand promotes a standards development model that demands:
The DASC Participates in IEEE Standards Association Gala Event
The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA on 4 December 2011. Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples.
The DASC recognized Larry Saunders as its “Ron Waxman Design Automation Standards Committee Meritorious Service Award” recipient. Larry was recognized “for pioneering the standardization of VHDL that fundamentally changed the electronic system design process.”
As someone who has worked with Larry on and off over the years to promote the use of VHDL, I know firsthand he is very deserving of this recognition and it was a pleasure to be present as he, one of the renowned VHDL fathers, was given this award. Yatin Trivedi, vice-chair of the DASC and director of standards at Synopsys gave a glowing tribute to Larry, not just from his DASC leadership role, but as a colleague, friend and mentor.
In addition to the “Ron Waxman” award, the IEEE-SA Working Group Chair Awards were also officially recognized. From the DASC, two of the working groups completed standards development and published their work and a few members of each of those groups were given Working Group Chair awards.
1076.1.1™-2010 IEEE Standard for VHDL Analog and Mixed-Signal Extensions – Packages for Multiple Energy Domain Support
Tom Alderton, Peter J. Ashendon, Ernst Christen, David W. Smith
1647™-2011 IEEE Standard for the Functional Verification Language e
Mike Bartley, Darren Galpin, Amy Witherow
Yatin’s citation for the Ron Waxman Award, Ron’s additional background on Larry’s contributions and Larry’s acceptance video can be seen below. The microphone was a bit away from the speakers and it was recorded at some distance from the speakers so the sound may be a bit hard to hear unless you use headphones. But for those who were not there and might like to see it, it is offered for you.
In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and I think I have them all!
What was clear to me was the IEEE standard was not sufficient to practice or understand the standard. After all, examples were few and far between in the standard. And even if there were examples in the standard, you were reminded that they are not part of the official standard – or in standards-speak – they are nonnormative.
User groups were popular too and continue to be today. VHDL International (now Accellera) had this notion of local VHDL user group chapters. When it came time to drive adoption of the VHDL gate-level library standard (known as VITAL), I attended several user group meetings to share details on how to use the new standard. I even solicited the support of a VHDL notable to put together a seminar series that would help ASIC library makers build their libraries. We took the seminar around the world and met with all the top ASIC suppliers. We even took our product that implemented the standard to the Cloud – while we did not call it the Cloud at the time. We had a model validation service in the early days of the internet that could be used to run training examples to validate ones own understanding or even test models and concepts to see if they would work. Free evaluation software was still a thing of the future then. As one byproduct of that work, we did have one competitor inundate us with the 1000’s of VHDL tests. We did throttle back their access to be fair to the others. But at that time, we left few ideas unexplored on how to drive global use and adoption of that standard.
What I understood was crossing the chasm from standards development to practicing the standard meant we had to build the knowledge, expertise and confidence in the user community to help them accept the standard and adopt it. I also learned that the standards developing organizations were not the best equipped to help practice the standard. The simple reason for this is the SDO is in place to bring together competitors to collaborate on the development of the standard but not foster competition on algorithms to best use the standard. This is perhaps better said by Synopsys’ Karen Bartleson in her “First Commandment for Effective Standards: Cooperate on Standards; Compete on Tools.”
Today’s Challenges with UVM & OVM
We are at that chasm with Open Verification Methodology (OVM) and the Universal Verification Methodology (UVM) today. While some may suggest OVM & UVM sit in a homogenous world where it works the same everywhere, the effective practice of the standards is anything but that. There are competitive options for users to explore and they are not ideas best promoted by a standards group. Mentor’s Mark Olen points out the value of an advanced method to generate stimulus rather than relying on the methods built into OVM & UVM in his recent blog post. Mark shows how a user gains 10x-100x in efficiency all the while doing this from within their OVM or UVM testbench.
Mentor has thought long and hard about how to best get this information to users and how to help them practice OVM and UVM better than they can if they only had access to the lowest common denominator of information. We first did a blind survey to see what methodology the design and verification community was using now and what they were going to use 12 months from now to validate our focus on OVM and UVM. Mentor’s Harry Foster has shared a lot of detailed information on this already. If you have not read his blog postings on this yet, you should start with his prologue that outlines the survey.
The survey clearly showed that UVM was in its ascendency and OVM was going to maintain strong and growing domination into 2012. Other survey results also clearly point out that SystemVerilog is the language of choice. While the survey shows what the user is doing, the standards developers were all collaborating on UVM and giving little time to OVM.
A Little Attention Goes a Long Way
While users were focused on continued use of OVM and planning for major move to UVM in 2012, the community developing standards had all but shifted to UVM, seemingly abandoning OVM. OVM was in need of care and attention given its dominant position in planned and future use.
Mentor stepped into the breach and has brought OVM into a strong, user-centric home that preserves the OVM World openness and augments it with several levels of additional user benefits in the Verification Academy. It also joins OVM and UVM in a single location that would not be appropriate in a standards body. After all, UVM is the standard from Accellera, not OVM. The Verification Academy also opens the cross pollination of ideas between the OVM and UVM users so one group can learn from another. We also brought the SystemVerilog User Group (SVUG) into the forum as well since OVM and UVM are based on the SystemVerilog language.
As we brought all these groups together, we did get many questions about Verification Academy Access Levels. First off, we dropped the OVM World requirement to register to download OVM. UVM and VMM were allowing anonymous downloads, so we made it the same for OVM. Of the 15,000+ OVM World registrants, most registered to download OVM. Just as OVM can now be downloaded without registration, the forums can be accessed in read-only mode without registration as well.
For those who used their OVM World registration to post on the forum, we moved them to “Forum Only Access” members so they could continue their posting privileges. The highest level of membership is “Academy Total Access.” Membership at this level is restricted to those who give a valid business profile. It enables access to training material, courses and lessons to help build SystemVerilog, OVM and UVM skills. It also allows users to gain knowledge about the advance algorithms that can help them get the 10x-100x or more out of OVM and UVM over conventional use. Below is a table of Verification Academy membership levels and privileges:
|Observer||Read-Only Forum Access. Free OVM/UVM kit download. No registration required.|
|Forum Only Access||Post to Forum and contributions area. Registration with any credentials required.|
|Academy Total Access||Total access. All academy areas open for free use. Registration with valid business profile.|
The response to this has been outstanding. While we strongly urge those who wish to develop the UVM standard to visit www.accellera.org and its www.uvmworld.org site to monitor that work, Verification Academy seems to have a much larger community of users with which to interact. And we will keep the Verification Academy current with the most recent versions of OVM and UVM. As of late July 2011 we recorded the following statistics.
|Verification Academy Forum||5,476|
|UVM World Forum||685|
|VMM Central Forum||696|
We look forward to continue to develop the site and add to the richness of its content and continue to improve your experience with it. Your comments on how we can improve it are always welcome.
How do your favorites rank?
Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But if you have purchased any IEEE standards, you will know this information is not available from the IEEE Store or the IEEE XPlore platform.
On May 4th, the IEEE Standards Association announced its collaboration with Techstreet to create the New IEEE Standards Store. Until now, anyone who wanted to order a single standard had to use a more complex system that even made it hard to share a permanent link to one’s favorite standard with another. Just look at the Accellera homepage for an example of where to get the SystemVerilog (IEEE Std. 1800™) standard. At the writing of this blog, it simply points to www.ieee.org. [I will share the fact the IEEE’s new site now has fixed links that can now be used to help others find the most current SystemVerilog standard with the Accellera.]
But back to what is the most popular IEEE EDA standards… Any guesses?
Before I delve into those details, let me say the ranking is just by ordinal. The New IEEE Standards Store shares no information on the actual number of standards purchased. So the difference between #1 and #10 could be just 10 copies. It probably isn’t, but it could be. But talking about #10, why is it even on the list? The IP-XACT standard (IEEE Std. 1685™) is available for free under the IEEE Get Program. Under this program you can download a PDF of the IEEE standard for free. If you want a printed version, you can print your own copy from the free one you download. Back in December 2010, Accellera reported that since the IEEE started to offer IP-XACT for free, there had been 1200 downloads. It also looks like many people did not want the hassle to print and simply ordered the print version directly from the IEEE. The other IEEE EDA standard offered free is SystemC© And this is probably the reason it is in 32nd place. It is very popular in terms of the number of free downloads.
And yes, if you search for the those two standards on the New IEEE Standards Store, you will find you can order print copies there and if you read the small print below, you will see there is a link to take you to the free online versions.
Harry Foster has issued several research reports on the popularity of one language or format the past several months. In his last blog, he discussed which of the design and verification languages are ranked high and those, well, not so high. And I guess I feel best to share the correlation between his findings and these more “anecdotal” results from the New IEEE Standards Store. I have been party to many at the top standards (Verilog/SystemVerilog) and party to the “least highest” (yes, I can’t say the least liked) VITAL 2000. For vindication, I will note that VITAL-95 comes in at #18. In whole, it appears to me that the New IEEE Standards Store ordinal rankings of EDA standards matches the scientific data from the research Harry has reported.
Below is the full ranking of IEEE EDA standards. Where are your favorites?
|1||IEEE 1364-2001||Verilog Hardware Description Language|
|2||IEEE 1800-2009||SystemVerilog–Unified Hardware Design, Specification, and Verification Language|
|3||IEEE 1076-2002||VHDL Language Reference Manual|
|4||IEEE 1076-1993||VHDL Language Reference Manual|
|5||IEEE 1499-1998||Interface for Hardware Description Models of Electronic Components|
|6||IEEE 1364-1995||Hardware Description Language Based on the Verilog® Hardware Description Language|
|7||IEEE 1800-2005||SystemVerilog: Unified Hardware Design, Specification and Verification Language|
|8||IEEE 1076.2-1996||VHDL Mathematical Packages|
|9||IEEE 1076.1-1999||VHDL Analog and Mixed-Signal Extensions|
|10||IEEE 1685-2009||IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows|
|11||IEEE 1850-2005||Property Specification Language (PSL)|
|12||IEEE 1076c-2007||VHDL Language Reference Manual – Procedural Language Application Interface|
|13||IEEE 1164-1993||Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)|
|14||IEEE 1850-2010||Property Specification Language (PSL)|
|15||IEEE 1076.6-2004||VHDL Register Transfer Level (RTL) Synthesis|
|16||IEEE 1801-2009||Design and Verification of Low Power Integrated Circuits|
|17||IEEE 1481-2009||Integrated Circuit (IC) Open Library Architecture (OLA)|
|18||IEEE 1076.4-1995||VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification|
|19||IEEE/IEC 61691-5-2004||IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification|
|20||IEEE 1647-2008||Functional Verification Language e|
|21||IEEE 1076.1.1-2011||VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support|
|22||IEEE/IEC 61691-7-2009||Behavioural languages – Part 7: SystemC Language Reference Manual|
|23||IEEE 1076-1987||VHDL Language Reference Manual|
|24||IEEE 1076.1.1-2004||VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support|
|25||IEEE 1076.3-1997||VHDL Synthesis Packages|
|26||IEEE/IEC 61523-3-2004||IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process|
|27||IEEE 1076/INT-1991||Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual|
|28||IEEE/IEC 62531-2007||IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL)|
|29||IEEE 1076.6-1999||VHDL Register Transfer Level Synthesis|
|30||IEEE 1647-2006||Functional Verification Language “e”|
|31||IEEE/IEC 61691-6-2009||Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions|
|32||IEEE 1666-2005||SystemC® Language Reference Manual|
|33||IEEE/IEC 61691-1-1-2004||IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual|
|34||IEEE 1364-2005||Verilog Hardware Description Language|
|35||IEEE/IEC 61691-4-2004||IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog® Hardware Description Language|
|36||IEEE 1076.4-2000||VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification|
Learn more about the New IEEE Standards Store
There is much more to the New IEEE Standards Store than just the rankings of the standards we use in electronic design automation. As I mentioned, it is easier to share fixed links to IEEE standards. And if you want to track IEEE standards development – and don’t want to have to register your email address with the actual committee developing it just to know when they are done and a standard is ready – you can register to be notified when a new standard is ready. The New IEEE Standards Store will notify you when a new one is ready.
Check out the short, one minute, video below to learn more about the New IEEE Standards Store.
Language and Library Trends
This blog is a continuation of a series of blogs, which present the highlights from the 2010 Wilson Research Group Functional Verification Study (for a background on the study, click here).
In my previous blog (Part 7 click here), I focused on some of the 2010 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present design and verification language trends, as identified by the Wilson Research Group study.
You might note for some of the language and library data I present, the percentage sums to more than one hundred percent. The reason for this is that some perticipant’s projects use multiple languages and multiple methodologies.
Let’s begin by examining the languages used for design, as shown in Figure 1. Here, we compare the results for languages used to design FPGAs (in grey) with languages used to design non-FPGAs (in green).
Figure 1. Languages used for design
Not too surprising, we see that VHDL is the most popular language used for the design of FPGAs, while Verilog and SystemVerilog are the most popular languages used for the design of non-FPGAs.
Figure 2 shows the trends in terms of languages used for design, by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected design language adoption trends within the next twelve months (in purple). Note that the design language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 2. Trends in languages used for design
Next, let’s look at the languages used for verification (that is, languages used to create simulation testbenches). Figure 3 compares the results between FPGA designs (in grey) and non-FPGA designs (in green).
Figure 3. Languages used in verification to create simulation testbenches
And again, it’s not too surprising to see that VHDL is the most popular language used to create verification testbenches for FPGAs, while SystemVerilog is the most popular language used to create testbenches for non-FPGAs.
Figure 4 shows the trends in terms of languages used to create simulation testbenches by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected language adoption trends within the next twelve months (in purple). Note that verification language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing.
Figure 4. Trends in languages used in verification to create simulation testbenches
Now, let’s look at methodology and class library adoption. Figure 5 shows the future trends in terms of methodology and class library adoption by comparing the 2010 Wilson Research Group study (in green) with the projected adoption trends within the next twelve months (in purple). Previous studies did not include data on methodology and class library adoption, so we are unable to show previous trends.
Figure 5. Methodology and class library future trends
The study indicates that the only methodology adoption projected to grow in the next twelve months are OVM and UVM.
Assertion Languages and Libraries
Finally, let’s examine assertion language and library adoption, as shown in Figure 6. Here, we compare the results for FPGA designs (in grey) and non-FPGA designs (in green).
Figure 6. Assertion language and library adoption
SystemVerilog Assertions (SVA) is the most popular assertion language used for both FPGA and non-FPGA designs.
Figure 7 shows the trends in terms assertion language and library adoption by comparing the 2007 Far West Research study (in blue) with the 2010 Wilson Research Group study (in green), as well as the projected adoption trends within the next twelve months (in purple). Note that the adoption of most of the assertion languages is declining, with the exception of SVA whose adoption is increasing.
Figure 7. Trends in assertion language and library adoption
In my next blog (click here), I plan to focus on the adoption of various verification technologies and techniques used in the industry, as identified by the 2010 Wilson Research Group study.
Tags: 1076, 1364, 1666, 1800, accellera, Add new tag, Assertion-Based Verification, functional verification, IEEE 1800, OVM, Standards, SystemVerilog, UVM, Verification Methodology, verilog, vhdl, vmm
Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages
OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.” It is not a word I see or use much. In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825.
It struck me that the title was tending towards the allegoric, if not mostly there, due to it conjuring possible metaphoric, astrological meaning as I began to wonder if planetary positioning was going to be offered on the next slide to bolster SystemVerilog’s ascendancy. I asked myself: Is SystemVerilog’s “ascendancy” a move to a new spiritual level? Has it transcended all other languages to garner greater social importance for design and verification? Is this a greater representation of another trends? Or, perhaps, I was having a flashback to the hippie era. After all, I was hearing in my mind that Hair song with the phrase
When the moon is in the second house
and Jupiter aligned with Mars…
But I was too young in the hippie era of 1967 to have a real flashback. And Wally’s keynote was not some hippie mumbo jumbo. I am also more than certain any of the engineers in the room at DVCon with some physics background could tell us Jupiter aligns with Mars several times a year and the few who might have astrological training (I’ve got to meet them!) could share with us the Moon is in the 7th House for about two hours every day.
Wally’s DVCon 2011 keynote was presented in three parts. The third and last part was on language transitions. When he got to that section he started it by presenting a slide on language transition titled “SystemVerilog in the Ascendancy.”
When some things go up, others go down. It is no surprise that VERA, which seeded the SystemVerilog standard, has reached a low level of predicted use in 2011 of 3%. Joining this decline is the other language of that day that battled with VERA, “e.” “e” use was at 16% in 2007 and 15% in 2010, but users plan a greater than 25% reduction in use from 2010 to 2011. This is a rather dramatic drop in one year, given it has held so steady from 2007 until now.
Wally also discussed the adoption of languages by geography. SystemVerilog has a strong global presence with particular strength in Asia and India. The “e” language shows focused geographic use in Europe/Israel followed by India. VHDL’s use also has focused geographic use with Europe/Israel leading followed by North America. It is interesting to note some languages have broad global appeal while others have only regional adoption.
Wally also touched on the adoption trends in testbench base-class libraries. Accellera’s UVM shows the largest growth from 2010 use to predicted use in 2011. It should grow from 7% to 27% in the next 12 months. While many projects adopted UVM’s progenitor, OVM, there appears to be no let up in use of OVM either over the next 12 months. In fact, there is some small growth predicted from 42% to 47%. Ongoing projects are the most probable reason that the OVM transition to UVM does not appear to start in the next 12 months. One can postulate that once projects end, teams can consider a transition from OVM to UVM. What it means to Mentor, OVM support is going to be critical for customer success for some time.
What is declining? “Other methodologies,” such as in-house or homebrew drop fastest as the last holdouts adopt the Accellera industry standard. All the other methodologies show small declines in the coming year.
The survey results Wally shared confirm the world is tending towards dominant use of IEEE Std. 1800™ (SystemVerilog) and Accellera UVM™. If the world is aligning on these standards, can we predict the standards wars are over? Looks like another Hair musical flashback:
Then peace will guide the planets.
And love will steer the stars
There are more survey results in Wally’s keynote. I will offer additional commentary in subsequent posts. Maybe you see additional information and meaning in those numbers. If so, I invite you to share your views and opinions of them. And no, you don’t need to dim the lights, turn on the black lights, download and listen to Hair’s Aquarius to divine your view.
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday. On Monday the group reported out conclusions of all the committee’s working groups.
Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users. In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I/O Buffer Information Specification. IBIS 4.2 is on the work plan for standardization. The Japanese National Committee’s technical report from JEITA on their Bird’s eye View of Design Language (BVDL) was also submitted as an official submission.
The TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems. From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).
Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards. For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010). The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo. Different countries have different rules and laws to recognize standards. The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.
… To Advance Technology for Humanity
It is a humbling honor to have been elected chair of the IEEE Standards Association’s (SA) Corporate Advisory Group (CAG). While Corporate Membership in the IEEE SA has been an element of the organization from its inception, it has only been in recent years that it has started to bring the voice of global industry into the IEEE’s standards making process. As CAG chair I plan to work with fellow CAG members to continue to encourage industry to extend its role to guide the IEEE SA and deepen its impact to foster consensus standards that meet industry needs.
The EDA industry and users of EDA technology have played a big role to help the corporate program to take shape. Prior to any EDA standards adopting the IEEE corporate process, “consumer” members of the IEEE 1076 (VHDL) team offered specific feedback in a letter writing campaign to EDA company leadership. Consulted on this campaign prior to its start, I was given an opportunity to weight in, in case I was able to offer a solution to avoid the campaign.
While I agreed with the need for greater direct and clear industry involvement, a revenue tax was probably not the answer. I also indicated I was almost certain that such a request to the highest levels in Mentor Graphics would probably find its way right back to me. The letter to Wally, Mentor Graphics’ CEO, did just that. It found its way to me. And the response back promised to reflect on Mentor’s commitment and that of industry to standards.
The VHDL team planted a seed to consider the question of what industry can do to foster better standards development that binds technologist with industry that I took to heart. A good model was underway in Accellera where SystemVerilog was being crafted that had strong support from Mentor Graphics and Synopsys along with vocal planned user adoption by Intel when their representative spoke at an Accellera press conference on the need for the industry to adopt the language.
While the rest is history for Accellera (and SystemVerilog), it was just the beginning for the IEEE SA. In the year ahead, Gabe Moretti, a member of the IEEE SA New Standards Committee at the time, told me (chair of Accellera at the time) of a growing corporate program in the IEEE SA. The corporate process to make SystemVerilog the IEEE 1800 standard was adopted and used. I also encouraged the VHDL team to follow the same path. The VHDL team was even more inventive and did some of their prep work within Accellera. However, when it came time to return to the IEEE SA, they retained their historical way to complete their work in the IEEE.
My preference is to have active industry participation during standardization. I like to know up front what backing the standard has from industry. The faster we can get industry to back and adopt standards, the faster humanity can benefit from the application of standards.
It is the pace part of industry involvement that has me add something to the new IEEE tag-line: “I do it to advance technology for humanity, quickly.”
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
- May 2013 (2)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)