Accellera Handoffs UVM to IEEE
Verification Methodology Beginnings
As the IEEE finalized approval of the initial release of SystemVerilog (IEEE Std. 1800™) in 2005, I floated the idea of the need for a methodology that would be a companion to it. At the time there was little to no industry desire to explore this opportunity in earnest – apart from interest by Mentor Graphics – so we launched our Advanced Verification Methodology (AVM) and set a new direction for an open functional verification methodology. We built implementations of AVM based on SystemVerilog and SystemC (IEEE Std. 1666™). We also pioneered an open-source mechanism based on the Apache 2.0 license which is now the accepted license to foster global and rapid open-source adoption in the EDA industry. And as others joined with us in this journey, AVM grew to become OVM, then UVM. Now UVM is set to become an IEEE standard. The IEEE has assigned it project number 1800.2.
To say we are pleased to see UVM move to the IEEE is an understatement. We congratulate the Accellera UVM team on its accomplishment and look forward to participate in this phase of UVM’s standardization. Since our first public announcement on May 8, 2006 when we introduced the world to AVM and announced support for it from 19 of our Questa Vanguard Partners, to our announced collaboration with Cadence Design Systems on the development of the Open Verification Methodology (OVM) on August 16, 2007 and the eventual announcement January 8, 2010 that Accellera adopts OVM as the basis of its Universal Verification Methodology, we have guided its development and supported a path for the Big-3 EDA to voice positive public support. We are thrilled Accellera has announced its delivery of UVM to the IEEE for ongoing standardization and maintenance.
What comes next? The IEEE P1800.2 (UVM) project has announced a Call for Participation and kickoff meeting to be held August 6, 2015 from 9am – 11am PDT. The first meeting will be held via teleconference. In order to attend, you will need to register for the meeting. Membership in the IEEE project will be “entity-based” with one company, one vote. The call for participation has details on membership requirements in order to observe or actively participate. The 1800.2 project will only focus on the written specification and not the open-source base class library (BCL). The Accellera UVM TSC will continue to update the BCL. Accellera has committed to keep the BCL implementation current with changes proposed and approved by the IEEE 1800.2 working group. This is just like the arrangement Accellera has with the IEEE for SystemC.
Join us at the upcoming meeting and remember to register in order to attend!