Posts Tagged ‘upf’

11 September, 2014

From those just beginning to study electronic systems design to the practicing engineer, this is the time of the year when those taking their first steps to learn VHDL, Verilog/SystemVerilog join the academic “back to school” crowd and those who are using design & verification languages in practice are honing skills at industry events around the world.

A new academic year has started and the Mentor Higher Education Program (HEP) is well set to help students at more than 1200 colleges and universities secure access to the same commercial tools and technology used by industry.  It is a real win-win when students learn using the same tools they will use after graduating.  Early exposure and use means better skilled and productive engineers for employers.

The functional verification team at Mentor Graphics knows that many students would prefer to have a local copy of ModelSim on their personal computer to do their course work and smaller projects as they learn VHDL or Verilog.  To help facilitate that we make the ModelSim PE Student Edition available for download without charge.  More than 10,000 students use ModelSim PE Student Edition around the world now in addition to our commercial grade tools they can access in their university labs.

For the practicing engineer, the Verification Academy offers an online community of more than 25,000 design and verification engineers that exchange ideas on a wide variety issues across the numerous standards and methodologies.  If you are not a member of the Verification Academy, I recommend you join.  You will also find the Verification Academy at DAC for one-on-one discussions and even more recently Verification Academy Live daylong seminars which came to Austin and which will be in Santa Clara – as of the writing of this blog.  There is still time to register for the Santa Clara event and I invite you to attend.

As design and verification is global, Accellera realized that DVCon should explore the needs of the global design and verification engineer population as well.  For 2014, DVCon Europe and DVCon India were born from an already successful running SystemC User Group events.  These user-led conferences will be held so engineers in these areas can more easily come together to share experiences and knowledge to ultimately become more productive.

Students and practicing engineers alike can benefit from fee-free access to some of the popular IEEE EDA standards.   While I don’t think reading them alone is the ultimate way to educate yourself, they make great companions to daily design and verification activities.  Accellera has worked with the IEEE to place several EDA standards in the IEEE Standards Association’s “Get™” program.  Almost 16,000 copies of the SystemC standard (1666) and just about the same number of SystemVerilog standards (1800) have been downloaded as of the end of August 2014.  Have you download your free copies yet?

The chart below shows the distribution of nearly 45,000 downloads which have occurred since 2010.  Stay tuned for breaking news on some updates to the EDA standards in the Get program.  When updated, they will replace the versions available now.  So if you want to have the current versions and the ones to come out shortly, you better download your copies now.  If the electronic version is not sufficient for you, the IEEE continues to sell printed versions.

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From students to practicing engineers, the season of learning has started.  I encourage you to find your right venue or style of learning and connect with others to advance and improve your design and verification productivity.

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20 August, 2014

The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global.  Accellera System Initiative has expanded many of its SystemC user group events to be more inclusive of other Accellera and IEEE standards.  In doing so, the local organizers of these events have moved to adopt the popular DVCon USA style to organize their events to include this large complement of standards.  If you want to attend, participate or contribute to the events, follow the links as shared below.

Mentor Graphics is excited to participate and sponsor these user-led events with a keynote address, technical paper presentations and educational tutorials.  We look forward to see you in September for DVCon India in Bangalore and in October for DVCon Europe in Munich.

DVCon Europe (14-15 October 2014 | Munich, Germany) will target the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The two day event will feature tutorials on the first day and technical paper presentations and poster sessions on the second day.  The DVCon Europe program list the details of the conference.  It is collocated with the annual Forum on Design Languages (FDL), which runs from 14-16 October 2014 in case you want to extend your stay for an extra third day.

At DVCon Europe Mentor Graphics is collaborating with our industry peers and users on a tutorial titled Enabling Energy-Aware System Level Design with UPF-Based System Level Power Models. As power has become one of the major concerns in design equaling those of feature, function and performance, more advances are needed to address system power challenges.  The tutorial will explore the use of IEEE Std. 1801™ (UPF) and how design and verification flows can best use it.

Mentor Graphics will also sponsor a tutorial titled Creating Portable Tests with a Graph-Based Test Specification.  It will cover an overview of a graph-based test description language that raises the level of verification abstraction to address system level challenges. This technology is being used by many successful verification teams around the world today and it is the technology we have committed to help build a new standard upon in Accellera.

DVCon India (25-26 September 2014 | Bangalore, India) is the first year of the transition of the popular Indian SystemC User Group (ISCUG) meeting into an event that expands to cover topics that bring together all the stakeholder involved in design and verification of IP, SoC, ASIC, FPGA and system level solutions.   The event is over two days with common sessions in the morning for keynote addresses.  The attendees will then break into an ESL track and Design & Verification track for focused sessions.

Mentor Graphics will sponsor a tutorial session as well as host the keynote presentation by Mentor Graphics CEO, Dr. Walden C. Rhines.  Dr. Rhines will review recent Wilson Research Group study results on the ongoing convergence of SoC design practices towards a common methodology, independent of specify tools being use. In this keynote, Dr. Rhines identifies the common attributes of SoC methodology that are emerging, and will highlight specific capability enablers for the further optimization of SoC design verification.

Registration for both events is now open and I hope you have time in your calendar to make it there.  Both events will have an exhibition area where you can also catch up on recent updates to our products and discuss what you think should be added next.  The Mentor Graphics team looks forward to meeting you there!

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10 April, 2014

Its always fun to take the wraps off of solutions we have been hard at work developing.  The global team of Mentor Graphics engineers have spent considerable time and energy to bring the next level of SoC design and verification productivity to what seems to be a never ending response to Moore’s Law.  As silicon feature sizes get smaller, design sizes get larger and the verification problem mushrooms.  But you know that.  These changes are the constants that drive the need for continued innovation.  Our next level of innovation for design verification is embodied in the Mentor Enterprise Verification Platform (EVP) which we recently announced.

Gary Smith recently published Keeping Up with the Emulation Market, and lays out the fact that verification platforms are unifying with emulation now a pivotal element, not just for microprocessor design success, but for Multi-Platform Based SoC design success as well.  The need to bring software debug into the loop with early hardware concepts is a verification challenge that must be supported as well.  Pradeep Chakraborty reported on the point made by Anil Gupta of Applied Micro at the UVM 1.2 Day in Bangalore where Anil implored “Think about the block, the subsystem and the top.”  The point made was software is often overlooked or under tested prior to committing to hardware implementation implying that our focus on UVM leaves us to verify no higher than where UVM takes us – and that is not the “top” of the SoC that mandates software be part of the verification plan.

Path to Success

With the Mentor EVP, we do address these issues.  We bring simulation and emulation together in a unified platform.  Software debug on conceptual hardware is supported to address verification at the “top.”  And even as Gary’s report concludes with a wonder about how easy access to emulation will be supported for the masses.  That too is solved in the Mentor EVP using VirtuaLAB that can be hosted in data centers along with the emulator vs. complex, one-off lab setups that lock an emulator to a design and lock out your global team of software developers from collaborating.  The Mentor EVP moves to emulation for the masses in a 24×7 world.

With big designs comes big data and complex debug tasks.  These complex debug tasks are all easily handled by the new Mentor Visualizer Debug Environment that has native UVM and SystemVerilog class-based debug capabilities and low-power UPF debug support to easily pinpoint design errors. All of this works in both interactive and post-simulation modes for simulation and emulation.  To keep the software team productive, and get to SoC signoff sooner, the innovative and new Veloce OS3 global emulation resourcing technology moves software debug think-time offline to Mentor’s Codelink software debug tool.

And there’s more!  But I’ll leave that for you to discover.  When you have time, visit us here, to learn more about the Mentor Enterprise Verification Platform.

Path to Standards

As the move to support Multi-Platform Based SoC evolves, so do the standards that underpin it.  And as I’ve reported on the comments of others in this blog – and the understanding from our experience that UVM can only go so far in Multi-Platform Based SoC verification – we concluded the time is right for the industry to explore the need for new standards.

We announced at DVCon 2014 an offer to take our graph-based test specification into an Accellera committee to help move beyond the limitations today’s standards have.  As our investment in tools, technology and platforms continues, we are keenly aware users want their design and verification data to be as portable as possible.  The Accellera user community members echoed the need to discuss portable stimulus that can take you up and down the design hierarchy from block, to subsystem, to system (“top”) and support the concurrent design of hardware and software.

In support of this, Accellera approved the formation of a Portable Stimulus Specification Proposed Working Group (PWG) to study the validity and need for a portable stimulus specification.  To that end, join me at the kickoff meeting to launch this activity on Wednesday, May 7, 2014 from 10:00am to 4:00pm Pacific time at the offices of Mentor Graphics in Fremont, CA USA.  If you would to attend, or you would  like time on the agenda to discuss technology that would advance the development of a Portable Stimulus Specification or discuss your objectives/requirements for this group, contact me and I will put you in touch with the meeting organizer.  Accellera PWG meetings are open to all and do not require Accellera membership status to attend.

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11 February, 2014

DVCon 2014 LogoOne of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.  And this year’s DVCon is no exception.  The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.  For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers.

UVM LogoI have written in the past about the productivity challenges before us to address the verification crisis and the emergence of machine-to-machine communication and the Internet of Things driving power aware design and verification.  To advance the demands on improved verification and help to address the verification crisis, the next round in the Universal Verification Methodology (UVM) standard is being readied for industry adoption.  UVM 1.2, the emerging update will be covered in some detail in a Monday morning tutorial to help you learn “What’s Now and What’s Next.”  Mentor Graphics’ Tom Fitzpatrick and Accellera Working Group representative will present in this tutorial.

UVM 1.2 is an active development project of Accellera and has not yet been released so there is no official standard available for download and use yet.  I’ll share standardization details as they happen.

At the same time on Monday, those who are concerned with power aware design and verification can attend the tutorial on the Unified Low Power Format (UPF), or as it is officially called IEEE 1801™-2013.  The tutorial will cover the full spectrum of UPF capabilities and methodology from basic to advanced applications.  So if you are new to UPF and want to learn, this is a great tutorial to attend.  And if you are already an expert, the advanced application of UPF as highlighted by those companies who have adopted UPF make this valuable for you as well.  Mentor Graphics’ Erich Marschner and IEEE 1801 Working Group vice-chair will participate in this tutorial.

UPF is an official IEEE standard.  Have you downloaded your copy yet?  Accellera has worked with the IEEE to make no-charge access to the official standard for you.  You can find the UPF standard here.

In the afternoon, there will be a session on case studies in SystemC.  User and vendor presentations will explore use of this standard.  SystemC offers much in the verification space, not just in technology but learning on how to bridge the RTL world with transaction level modeling world.  Mentor Graphics’ John Stickley will review what we have learned and how you can apply it to your most pressing verification needs.

SystemC is an official IEEE standard.  Have you downloaded your copy yet?  Under the Accellera agreement with the IEEE, you can download SystemC standard here.

There is a lot more to DVCon than just the use of current standards and planning adoption of emerging standards.  I encourage you to check out the whole agenda and join me at DVCon 2014 March 3-6.

Mentor Graphics presentations during the conference include:

  • Tuesday Paper Sessions
    • Amit Srivastava – Stepping Into UPF 2.1 World: Easy Solution to Complex
      Power Estimation
    • Kenneth Bakalar – Interpreting UPF For A Mixed-Signal Design Under Test
    • Gordon Allan – Tried and Tested Speedups for Software-Driven SoC Simulatio
  • Tuesday Poster Sessions
    • Rich Edelman – Debugging Communicating Systems: The Blame Game – Blurring
      the Line Between Performance Analysis and Debug
    • Matthew Balance – Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
    • Gaurav K. Verma – Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology
    • Andreas Meyer – So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
    • Rich Edelman – UVM SchmooVM – I Want My C Tests!
    • Thom Ellis – Are  You Really Confident That You Are Getting the Very Best From Your Verification Resources?
    • Jitesh Bansal – Is Your Power Aware Design Really X-Aware
  • Wednesday Paper Sessions
    • Avidan Efody – Wiretap Your SoC: Why Scattering Verification IPs Throughout Your Design Is A Smart Thing To Do
    • Tom Fitzpatrick – Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It

Mentor Graphics will host its traditional lunch at DVCon on Wednesday on the theme of Accelerating Verification.  And we have lively panel participants for the Tuesday and Wednesday panels.  And, as always, the Exhibit, CEO Keynote and Panels are open to all a no charge – you just have to REGISTER!

I look forward to seeing you there!

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15 October, 2013

Low Power Flow Kicks-off Symposium

In the world of electronic design automation, as an idea takes hold and works its way from thought to silicon, numerous tools are used by engineers and the like to help bring a good idea to product fruition.  Standards play a key and important role to help move your user information from high-level concepts into the netlists can be realized in silicon.  The IEEE Standards Association is holding a Symposium on EDA Interoperability to help members of the electronics/semiconductor design and verification community better understand the landscape of EDA and IP standards and the role they play to address interoperability.

Another key component are the programs and business relationships we foster to promote tool connectivity and interoperability among each other.  The Questa users rely on the Questa Vanguard Partnership program so their trusted tool and technology partners have access to our verification technology to allow them to craft the leading edge design and verification flows with technology from numerous sources.  If your users want you to connect with Questa, we invite them to explore the benefits of this program.  Even better, join us at the IEEE SA Symposium on EDA Interoperability where can also discuss this in person – Register Here!

Event Details
Date: 24 October 2013
Time: 9:00 a.m. – 6:00 p.m. PT
Location: Techmart – 5201 Great America Parkway, Santa Clara, CA 95054-1125
Cost: Free!
Program: http://standards.ieee.org/events/edasymposium/program.html

One of the more pressing issues in design and verification today is address the issue of low power.  The IEEE SA Symposium on EDA kicks-off the morning with its first session on “Interoperability Challenges: Power Management in Silicon.”  The session will feature an opening presentation on the state of standardization by the Vice Chair of the IEEE P1801 Working Group (and Mentor Graphics Verification Architect) as well as two presentations from ARM on the use of the IEEE 1801 (UPF) standard.

11:00 a.m. – 12:00 p.m. Session 1: Interoperability Challenges: Power Management in Silicon
IEEE 1801 Low Power Format: Impact and Opportunities
Erich Marschner, Vice Chair of IEEE P1801 Working Group, Verification Architect, Mentor Graphics
Power Intent Constraints: Using IEEE1801 to improve the quality of soft IP
Stuart Riches, Project Manager, ARM
Power Intent Verification: Using IEEE1801 for the verification of ARM Cortex A53 processor
Adnan Khan, Senior Engineer, ARM

The event is sponsored by Mentor Graphics and Synopsys and we have made sure the symposium is free to attend.  You just need to register.  There are other great aspects to the event, not just the ability to have a conversation on the state of standards for low power design and verification in the morning.  In fact, the end of the event will take a look at EDA 2020 and what is needed in the future.  This will be a very interactive session that will open the conversation to all attendees.  I can’t wait to learn what you have to share!  See you at the Techmart on the 24th.

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28 June, 2013

Clocking and Power Trends

In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends.

Independent Asynchronous Clock Domains

Figure 1 shows the percentage of designs developed today by the number of independent asynchronous clock domains. The asynchronous clock domain data for FPGA designs is shown in red, while the data for the non-FPGA designs is shown in green.

 

Figure 1. Number of independent asynchronous clock domains

Figure 2 shows the trends in number of independent asynchronous clock domains for non-FPGA designs. The comparison includes the 2002 Collett study (in dark green), the 2007 Far West Research study (in gray), the 2010 Wilson Research Group study (in blue), and the 2010 Wilson Research Group study (in green).

Figure 2. Trends: Number of independent asynchronous clock domain

It’s interesting to note that, although the number of clock domains is increasing over time, the sweet spot in terms of number of independent asynchronous clock domains seems to remain between 2 and 20, and it hasn’t changed significantly in the past ten years.

Figure 3 provides a different analysis of the data by partitioning the projects by design sizes, and then calculating the mean number of independent asynchronous clock domains by project design. The design size partitions are represented as: less than 5M gates, 5M to 20M gates, and greater than 20M gates.

Figure 3. Mean number of independent clock domains by design size

Power Management

Today, we see that about 67 percent of design projects actively manage power with a wide variety of techniques, ranging from simple clock-gating, to complex hypervisor/OS-controlled power management schemes. We decided for the 2012 Wilson Research Group study that we wanted to take a closer look at power management related to functional verification. Hence, I can share some interesting results with you here. However, since this aspect of functional verification has never been studied in previous surveys, I will not be able to show trends. Our goal is to carry these same questions forward in our future studies so that we can identify trends.

For these, Figure 4 shows the various aspects of their power-managed design that they verify (for those 67 percent of design projects that actively manage power).

Figure 4. Aspects of power-managed design that are verified

In our study, we asked what percentage of simulation was power-aware (that is, verifying some functional aspect of the power-management scheme), and the results are shown in Figure 5. We were surprised to learn that about 10 percent of all designs that actively manage power perform no power-aware simulation to verify the power management scheme.

Figure 5. Percentage of simulation that verified some aspect of power management

In addition, we asked what percent of verification resources were focused on power management verification, and the results are shown in Figure 6. You will note that the curve is very similar to the percentage of total simulations that were power-aware, which you would expect. Again, we see that about 10 percent of the projects that actively manage power provide no verification resources to verify the power-management scheme.

 

Figure 6. Percentage of verification resources focused on power management

Figure 7 shows the different types of simulation-based functional testing approaches that are currently applied to verifying power management. It’s not a surprise that most power-aware simulation is based on directed-testing approaches since often (but not always) power-aware simulations are performed at the SoC integration level where directed testing is common.

 

Figure 7. Percentage of simulation that verified some aspect of power management

Since the power intent cannot be directly described in an RTL model, alternative supporting notations have recently emerged to capture the power intent. In the 2012 study, we wanted to get a sense of where the industry stands in adopting the notation. For projects that actively manage power, Figure 8 shows the various notations that have been adopted to describe the power intent. Some projects are actively using multiple standards (such as different versions of UPF or a combination of CPF and UPF). That’s why the adoption results do not sum to 100 percent.

 

Figure 8. Notation used to describe power intent

In my next blog (click here), I’ll present data on design and verification reuse trends.

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29 May, 2013

Download the standard now – at no charge

The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance and enhancement to the IEEE.  Further – Courtesy of Accellera – the standard is available for download without charge directly from the IEEE.

1801-2013_Page_001The latest update to IEEE 1801 is ready for download.  It joins other EDA standards, like SystemVerilog and SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF.  (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)

The official IEEE announcement on the standard’s publication can be found here.  And the official Accellera announcement that it has partnered with the IEEE-SA to offer the standard to all at no charge can be found here.  This revision of the standard had one of the largest number of IEEE-SA entity members of any corporate standards program.  Participation from the IEEE-SA global community of entity participants ensures the needs of a broad set of companies are captured to support this worldwide standard.

Just In Time For DAC

50th DACDAC 2013 has many events that will allow you to learn more about the new standard and how to use it to your maximum benefit.  And for those who cannot attend DAC, visit the Verification Academy, you will find the Low Power sessions cover the new standard as well. [Registration required; restrictions apply.]

Sunday
Topic: DAC Workshop:  Low-Power Design with the New IEEE 1801-2013 Standard
Date: 2 June 2013
Time: 1:00 p.m. – 5:00 p.m.
Location: Convention Center: Room 18C
Registration: Official DAC Workshop registration required ($). For more information and to register, click here.


Monday
Accellera Breakfast & Town Hall Meeting
Topic: The Standard for Low Power Design and Verification is here!  What’s next?
Date: 3 June 2013
Time: 7:00 a.m. – 8:45 a.m.
Location: Convention Center: Ballroom D
Registration: This is a free Accellera event, but registration is required.  Form more information click here and to register, click here.


Monday
Verification Academy
Topic: “Low Power Monday”
Date: 3 June 2013
Time: 11:00 a.m. – 6:00 p.m.
Location: Tradeshow Floor – Booth 1215
Registration: The DAC Tradeshow floor is open to all DAC registrants. Visit www.dac.com to register.

The Verification Academy is open to all DAC registrants.  There are no restrictions and we invite everyone to visit booth 1215 for Low Power sessions that may be of interest to you on Monday.  To help judge attendance, please feel free to pre-register at here.  I look forward to see you there as you will find me here most of the time Monday-Wednesday.

Time Description Presenter
11:00 a.m. – 12:00 p.m. Low Power Verification Tim Jordon
MicroChip Technlogy
1:00 p.m. – 2:00 p.m What’s New in UPF 2.1? Erich Marschner
IEEE 1801 Vice-chair
Mentor Graphics
2:00 p.m. – 3:00 p.m. UPF-Based Verification for Cypress PSOC Ellie Burns
Mentor Graphics
4:00 p.m. – 5:00 p.m. Optimizing for Power Efficient Design Abhishek Ranjan
Calypto
5:00 p.m. – 6:00 p.m. IEEE 1801 UPF Commands and Methodology John Biggs
ARM
IEEE 1801 Chair

If you are coming to DAC and participating in the DAC Low Power Workshop on Sunday, or in other events, download your person copy of the new IEEE 1800-2013 standard today.  The PDF form allows you to take it with you and read it using your favorite e-reader or i-device.  Let’s me know what you think of the standard.  And – See you at DAC!

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29 April, 2013

Power Aware Verification Course Modules Released

I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to out do the other when it came to puns. So it is understandable why the topic of low power standards takes me back to these fun exchanges.

But low power design and verification is a serious issue that design teams continue to grapple. To take advantage of emerging support of the new low power standard takes time and energy on part of practicing engineers and design teams. More information on what IEEE Std. 1801™-2013 (Unified Power Format) is and how you can use it is needed.

Back in March 2013 I blogged that the revised IEEE low power standard had been approved. I also mentioned there would be a short wait until the standard itself was published. And, indeed, we continue to wait for the final editing of the standard. I shared a link to a short article on the content of the standard, but more information is needed.

PA Verificatio Intro.jpgTo address this need, the Verification Academy has added a course on Power Aware Verification. There are six (6) sessions that will introduce you to power aware verification, UPF and walk you through an example to illustrate the use of the standard in more detail in about 1.5 hours. In order to access the course material you will need to be a “full access” registrant of Verification Academy. There is no fee for this, but restrictions apply.

In addition to watching the video course sessions online, you can also download the presentations and MP4 videos of the course for offline viewing.

The six course sessions are:

We are interested to get your feedback on the Power Aware Verification course and learn what additional sessions you think would help you get AMP’ed up to further the need to conserve energy. Let us know!

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14 March, 2013

IEEE 1801™-2013 Enters Pre-Publish Phase

The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.

If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).

As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication.  So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet.  So I won’t do that.  If you do need something, the superseded version from 2009 is the only one available at this moment.  I will keep you updated as to when it is published and ready for access to the global design community.

imageMentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled Bringing Verification and Validation under One Umbrella The Evolution of UPF: What’s Next?  (Free access; no registration required; 81KB)

Erich gives a good introduction to the new standard, also known as UPF 2.1.  He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.

Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot.  This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification.  If you are interested to join in with the IEEE 1801 team, visit here for more information.

DVCon UPF Tutorial

The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon.  For those who registered for the conference, the tutorial presentation is still available online.  Unfortunately, the material has not yet been made available to the general public.  If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy.  The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.

As for planning you can do now.  The IEEE 1801 team will host a tutorial at DAC on Sunday.  I will share more information with you on that once the DAC registration site goes live.  Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.

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19 February, 2013

Learn about new standards, industry surveys and trends

This year’s DVCon is set and if you have not yet registered, you can do it now – or just show up!  If you want to secure seating at some of the Monday tutorial events, I strongly encourage pre-registration to ensure you can secure a seat.  And if you just want to see the exhibits and chat with suppliers, that’s free.

The IEEE low power format is set to close on its current round standardization shortly and DVCon is a great place to learn all about it from the experts.  Harry Foster will update the DVCon attendees on design and verification trends over lunch on Tuesday and later that afternoon, Mentor CEO, Wally Rhines will offer this year’s DVCon keynote.  His keynotes are always insightful and entertaining.  And if you want to catch me, you can find me with the Mentor staff at the Mentor exhibit booth.  Or just follow @dennisbrophy on Twitter and I will share info on paper presentations and other happenings.  For more details on the events mentioned above, see below.  For more information DVCon in general, visit the website at www.dvcon.org.


Monday | February 25th | 1:30pm – 4:30 | Fir Ballroom
Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™

The past few years, the IEEE P1801™ (Unified Low Power – UPF) Working Group has been busy working on an update to the industry’s standard for low power design, verification and implementation.  Accellera has brought together experts from many EDA tool suppliers and users for this tutorial.  Attendees can expect to gain a detailed understanding of of the IEEE standard (concepts, terminology & features) as well as an understanding of the practical aspects to apply UPF in real world flows.

The following experts will be help you learn about the new standard – and will be available to interact with at the conclusion of the tutorial.

Speakers:
  • John Biggs – ARM, Inc.
  • Sushma Honnavara-Prasad – Broadcom Corp.
  • Dr. Qi Wang – Cadence Design Systems, Inc.
  • Erich Marschner – Mentor Graphics Corp.
  • Jeffrey Lee – Synopsys, Inc.

Learn more, then register.


Tuesday | February 26th | 11:30am – 12:45pm | Pine/Cedar Ballroom
The Changing Landscape in Functional Verification: Industry Trends, Challenges, and Solutions
Presented by Harry Foster

Mentor Graphics invites you to join us for lunch—where we will present, for the first time publicly, highlights from this year’s Wilson Research Group Functional Verification Study. Be the first on your block to learn the latest verification trends, challenges, and solutions.
Learn more, then register.


Tuesday | February 26th | 3:30pm – 4:30pm | Oak/Fir Ballroom
Speaker: Wally Rhines, Chairman and CEO of Mentor Graphics

As a thought provoking, timely, and informative presentation, this keynote session will focus on functional verification trends and the accelerated adoption of advanced functional verification technologies, methodologies and languages.
Learn more, then register.


Booth #901
Tuesday & Wednesday (February 26th & 27th)
3:30pm – 6:30pm

I look forward to meet up with those who attend DVCon.  You can catch me at or around the Mentor booth for the last three hours of the conference.

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