Posts Tagged ‘upf’
Getting AMP’ed Up on the IEEE Low-Power Standard
Power Aware Verification Course Modules Released
I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to out do the other when it came to puns. So it is understandable why the topic of low power standards takes me back to these fun exchanges.
But low power design and verification is a serious issue that design teams continue to grapple. To take advantage of emerging support of the new low power standard takes time and energy on part of practicing engineers and design teams. More information on what IEEE Std. 1801™-2013 (Unified Power Format) is and how you can use it is needed.
Back in March 2013 I blogged that the revised IEEE low power standard had been approved. I also mentioned there would be a short wait until the standard itself was published. And, indeed, we continue to wait for the final editing of the standard. I shared a link to a short article on the content of the standard, but more information is needed.
To address this need, the Verification Academy has added a course on Power Aware Verification. There are six (6) sessions that will introduce you to power aware verification, UPF and walk you through an example to illustrate the use of the standard in more detail in about 1.5 hours. In order to access the course material you will need to be a “full access” registrant of Verification Academy. There is no fee for this, but restrictions apply.
In addition to watching the video course sessions online, you can also download the presentations and MP4 videos of the course for offline viewing.
The six course sessions are:
- Introduction to Power Aware Verification (9 minutes)
- Overview of UPF (13 minutes)
- Getting Started with UPF (23 minutes)
- A Simple UPF Example (17 minutes)
- UPF 2.0 Enhancements (11 minutes)
- Using Supply Set (18 minutes)
We are interested to get your feedback on the Power Aware Verification course and learn what additional sessions you think would help you get AMP’ed up to further the need to conserve energy. Let us know!
Tags: IEEE 1801, Low Power, Power Aware Verification, Standards, upf
IEEE Approves New Low Power Standard
IEEE 1801™-2013 Enters Pre-Publish Phase
The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now. Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013). The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.
If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).
As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication. So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet. So I won’t do that. If you do need something, the superseded version from 2009 is the only one available at this moment. I will keep you updated as to when it is published and ready for access to the global design community.
Mentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled 
The Evolution of UPF: What’s Next? (Free access; no registration required; 81KB)
Erich gives a good introduction to the new standard, also known as UPF 2.1. He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.
Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot. This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification. If you are interested to join in with the IEEE 1801 team, visit here for more information.
DVCon UPF Tutorial
The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon. For those who registered for the conference, the tutorial presentation is still available online. Unfortunately, the material has not yet been made available to the general public. If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy. The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.
As for planning you can do now. The IEEE 1801 team will host a tutorial at DAC on Sunday. I will share more information with you on that once the DAC registration site goes live. Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.
Tags: dvcon, Erich Marschner, IEEE 1801, IEEE-SA, Low Power, RevCom, Standards, upf
See You at DVCon 2013!
Learn about new standards, industry surveys and trends
This year’s DVCon is set and if you have not yet registered, you can do it now – or just show up! If you want to secure seating at some of the Monday tutorial events, I strongly encourage pre-registration to ensure you can secure a seat. And if you just want to see the exhibits and chat with suppliers, that’s free.
The IEEE low power format is set to close on its current round standardization shortly and DVCon is a great place to learn all about it from the experts. Harry Foster will update the DVCon attendees on design and verification trends over lunch on Tuesday and later that afternoon, Mentor CEO, Wally Rhines will offer this year’s DVCon keynote. His keynotes are always insightful and entertaining. And if you want to catch me, you can find me with the Mentor staff at the Mentor exhibit booth. Or just follow @dennisbrophy on Twitter and I will share info on paper presentations and other happenings. For more details on the events mentioned above, see below. For more information DVCon in general, visit the website at www.dvcon.org.
Monday | February 25th | 1:30pm – 4:30 | Fir Ballroom
Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™
The past few years, the IEEE P1801™ (Unified Low Power – UPF) Working Group has been busy working on an update to the industry’s standard for low power design, verification and implementation. Accellera has brought together experts from many EDA tool suppliers and users for this tutorial. Attendees can expect to gain a detailed understanding of of the IEEE standard (concepts, terminology & features) as well as an understanding of the practical aspects to apply UPF in real world flows.
The following experts will be help you learn about the new standard – and will be available to interact with at the conclusion of the tutorial.
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Tuesday | February 26th | 11:30am – 12:45pm | Pine/Cedar Ballroom
The Changing Landscape in Functional Verification: Industry Trends, Challenges, and Solutions
Presented by Harry Foster
Mentor Graphics invites you to join us for lunch—where we will present, for the first time publicly, highlights from this year’s Wilson Research Group Functional Verification Study. Be the first on your block to learn the latest verification trends, challenges, and solutions.
Learn more, then register.
Tuesday | February 26th | 3:30pm – 4:30pm | Oak/Fir Ballroom
Speaker: Wally Rhines, Chairman and CEO of Mentor Graphics
As a thought provoking, timely, and informative presentation, this keynote session will focus on functional verification trends and the accelerated adoption of advanced functional verification technologies, methodologies and languages.
Learn more, then register.
Booth #901
Tuesday & Wednesday (February 26th & 27th)
3:30pm – 6:30pm
I look forward to meet up with those who attend DVCon. You can catch me at or around the Mentor booth for the last three hours of the conference.
Tags: Harry Foster, IEEE 1801, Low Power, Standards, upf, Wally Rhines
Verification Academy: Up Close & Personal
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design. The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well. A whole host of educational modules and seminars can also be found there too.
If you know about the Verification Academy, you know all about the content mentioned above and that there is much more to be found there. For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum. (Flash is required to watch Harry discuss Verification Academy with Luke.)
The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends. Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations. While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations. Verification Academy “Total Access” members now have access to many of the presentations.
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ARM |
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Doulos |
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Thales Alenia Space |
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Test & Verification Solutions |
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Willamette HDL |
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Sunburst Design |
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Mentor Graphics |
Total Access members can also download all the presentations in a .zip file. Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.
Tags: ABV, ACE, ams, ARM, Assertion-Based Verification, Coverage Closure, dac, Doulos, formal, IEEE, iTBA, Low Power, OVM, SystemVerilog, Tech Design Forum, Thales, upf, UVM, UVM Express, Verification Academy, Verification Trends
Off to DAC!
Where might our paths cross?
It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC). If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.
Saturday and Sunday are busy with an Accellera Systems Initiative board meeting. Split across two days, Accellera board members will meet to conduct traditional business and do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year. Intel has graciously granted space in their San Francisco offices, so I won’t be around the Moscone Center during the pre-conference setup phase. (By the way, Thank you Intel!)
After we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception (registration required) at 6:00pm (San Francisco Marriott, Salon 7) and Gary Smith’s “Sunday Night at DAC” at 7:00pm (San Francisco Marriott, Salon 6).
During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings. And just in case you may note that most of my evenings are not scheduled, they are with customer activities.
When the show floor is open, you will find me most of the time at the Verification Academy Booth #1514. I will join Mentor’s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry’s research results, updates on important verification standards from Mentor’s perspective and more. You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth. (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)
Verification Academy DAC Schedule
| Monday, June 4th | Tuesday, June 5th | Wednesday, June 6th |
10:00 – Simulation and Formal Assertion-Based VerificationHarry Foster, Mentor Graphics |
9:30 – Using the UVM Register Layer
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10:00 – Bringing UVM to Life
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11:00 – Bringing UVM to Life
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10:00 – Generating Coverage Models and Achieving Coverage Closure
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11:00 – Resistance is Futile: Learning to love UVM!
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2:00 – Verification of Low Power SoCs with IEEE UPF
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2:00 – Bringing UVM to Life
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2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics
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3:00 - Evolving Trends in Functional Verification
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3:00 - Evolving Trends in Functional Verification
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3:00 – UVM Express
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4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
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4:00 - Evolving Trends in Functional Verification
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5:00 - Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
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5:00 – Meet the Verification Experts Cocktail Reception |
Accellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS). The lunch is free and seating is limited and registration is required.
Hosted Luncheon and Technical Presentation
Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard
Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee
Wednesday, June 6, 12:00-1:30pm
Moscone Center, Room 250
Register Now >
This luncheon is open to all DAC attendees. Seating is limited! You must pre-register for this event.
Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.
This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.
SystemC User Group Meeting
NASCUG XVIII
North American SystemC User’s Group Meeting
Wednesday, June 6, 2:00-6:00pm
Moscone Center, Room 262
Register Now >
This event is open to all DAC attendees. Seating is limited!
The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agendafor the event has a lot offer user group attendees.
Mentor’s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog. Adam’s presentation is scheduled to start at 3:00pm.
Tags: accellera, dac, edac, gary smith, Standards, systemc, TLM, UCIS, upf, UVM, Verification Academy
IEEE Standards in India
IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi
I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi. In the last year, the IEEE announced it opened an office in Bangalore, India. This is the fourth IEEE office in Asia, following China, Japan and Singapore.
A large number of IEEE’s members reside in India and the EDA standards get a lot of use and attention in India. There is a strong and thriving IEEE Std 1800™ SystemVerilog community in India that are helping to extend the verification capabilities of the language. As the IEEE office gets setup, I look forward to it to help better coordinate standards development of a global community of companies and individuals.
Agenda: Bangalore, India Workshop (Register)
Location: Mentor Graphics, Bangalore
| 8:30 | Registration opens | |
| 9:00 | Welcome–Pamela Kumar (IBM) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
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| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
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| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
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| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
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| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Pamela Kumar Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra, Srini Venkataramanan, Anuradha Srinivasan (Intel) |
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| 12:30 | Conclusion & Thank You |
A set of IEEE-SA Board of Governors meetings will be held at the beginning of the the week of February 7th. And in addition to the meeting on design automation standards in Bangalore, a group of workshops are also planned in Mumbai on 4 February 2011 on Cloud Computing and Smart Grid by other colleagues I volunteer with on the IEEE-SA Board of Governors. There are more IEEE-SA events planned for the week of February 7th and a full list can be found here.
For those who wish to join the New Delhi design automation workshop, some details of it can be found below.
Agenda: New Delhi, India Workshop (Register)
Location: IIT
| 8:30 | Registration opens | |
| 9:00 | Welcome—Karen Bartleson (Synopsys) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
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| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
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| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
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| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
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| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Karen Bartleson Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra |
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| 12:30 | Conclusion & Thank You |
Tags: 1666, 1735, 1800, 1801, IEEE-SA, Standards, systemc, SystemVerilog, upf
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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