Posts Tagged ‘systemc’

22 February, 2012

In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this topic at our last face-to-face with the VIP-TSC.  With demand coming from our users, and some positive feedback on our proposal, we have just released UVM Connect, an open-source library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).

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You can find much more information on the UVM Connect page of Verification Academy.

Mentor has always believed that SystemVerilog and SystemC each have their own strengths and that the most productive way to combine them in a system-level environment is to preserve the strengths of each while allowing the free exchange of data between them. Instead of trying to re-implement UVM in SystemC, or to extend SystemC to try and recreate SystemVerilog functional coverage or constrained-random stimulus, UVM Connect provides the framework needed to interoperate between languages. This lets you:

  • Reuse your SystemC architectural models as reference models in UVM verification
  • Reuse your stimulus generation agents in SystemVerilog to verify models in SystemC
  • Have access to a wider array of VIP since you are no longer confined to a single language
  • Utilize and interact with the UVM infrastructure from SystemC, including wait for and control UVM phase transitions, set and get configuration, issue UVM-style reports, set factory type and instance overrides, and more

UVM Connect provides object-based data transfer across the language boundary via TLM1 and TLM2 interfaces, which are natively supported in both languages. It works out-of-the-box with UVM 1.1a and later and lets you use your existing TLM models, regardless of language, in a mixed-language context without modification. In a nutshell, UVM Connect fulfills the principles and purpose of the TLM interface standard, letting you design independent models that communicate without directly referring to each other. The models thus work equally well in both native and mixed-language environments.I encourage you to download the kit and give it a try. In the spirit of “co-op-etition” I also encourage our competitors to qualify the library on their simulators.

In addition to the great material in the UVM/OVM Online Methodology Cookbook on Verification Academy, the kit also includes an HTML User’s Guide, based on extensive, well-documented examples, that includes detailed information on all aspects of the API. Please make sure to stop by the Mentor booth at DVCon and let us know what you think.

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17 February, 2012

It is time to talk about what happens next with UVM

uvm 2The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference organizers had to rearrange the room layout to accommodate a greater than expected number of registrant.  It is clear how important the topic of verification is and UVM in particular has become.

It seems to me that DVCon is the right place to discuss what comes next with UVM.  I have three thoughts about UVM that I think merit discussion.

1. UVM needs a period of stability

While the experts at the Accellera Verification IP Technical Subcommittee (VIP-TSC) standardization table (all good people) continue to hone UVM and debate a few more features they need, they have been unable to make significant progress on those features since last DVCon.  The one major item promised beyond OVM, an update to phasing, remains an open topic.  Mentor has suggested in committee that we allow another year to pass and suspend committee action on this.  Maybe the natural market forces would allow several options to surface, be user-tested and then merit consideration by the VIP-TSC.

This is in keeping with Karen Bartleson’s 9th Commandment for Effective Standards: “Start with Donations; Not From Scratch.”  This is what is happening now with Phasing.  The design by committee process is moving slowly.  It is not the slow part that concerns me, however.

Completing the “last” thing has many in the verification community waiting until it is done before they migrate and adopt UVM.  The best thing the committee could do to encourage use is to give the users certainty that UVM will not change in the next 12 months.  At the same time, the committee could commit to take input from users at the end of those 12 months as a guide to what it does next.

2. UVM needs a simple path to first use

Accellera has an approved and published standard, an open-source implementation and embedded UVM User’s Guide.  This is a lot to digest.  And while one may expect the User’s Guide to help, it calls the reader to supplement it with “education, experience and professional judgment.”  It warns that “not all aspects of this guide may be applicable in all circumstances.”

Users should be offered an unambiguous, easy-to-use and understand means to adopt UVM without having to know everything about it before starting to use it.  UVM was not made for just those who have large verification teams and central CAD groups.  Those large teams are the ones who are already using UVM.  The first step to UVM adoption for the rest of the world should not be too high as it currently is.

UVM needs a simple path for fast adoption.

3. UVM needs to bridge the system domain

Accellera System Initiative has come to life from the unification of Accellera and OSCI.  While the vision to bring the two organizations together is without fault, the lack of a publicly visible plan to leverage each others strengths is noted by Gabe Moretti in his recent blog on DVCon when he wrote: “First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.”  His comment was in response to the questions to be asked at DVCon’s Monday lunch about what the new organization should look like.  Gabe certainly thought “the creators of the organization must have some ideas of the focus, mission and goals.”

I certainly do.  In the case of UVM, I think it needs a bridge between the SystemVerilog world in which it was written and the SystemC world of design and modeling.  As teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models has become an imperative.

It is no secret to the Accellera VIP-TSC that Mentor Graphics thinks this is needed.  Our presentation to committee members on a UVM API to facilitate this outlines exactly what we think should be done to address reusable functional models in the system world.  [Accellera requires registration to download the Mentor presentation.  Accellera members can register here.  Guests require VIP-TSC leadership permission and can request it here.]

UVM must grow and bridge the system world.  The Accellera SystemC Verification Working Group (VWG) knows this.  They have a meeting planned at the DATE conference to discuss future evolutions related to SystemC and Verification on 14 March 2012 from 1230-1340 in Conference Room 4 which I plan to attend.  The VWG meeting is open to external participants, not just Accellera members.

Summary

I don’t know what your thoughts about what should happen next with UVM are.  Feel free to share them here if you wish or join me at DVCon or DATE and we can discuss it with the whole community.  Maybe there is hope we can make progress on these three areas in the coming year.

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16 January, 2012

IEEE Std. 1666™-2011 Available as Free Download

In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011.  One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM).  I pointed to several online resources to learn more about the revised SystemC standard in that blog.  But missing from the list of resources was information on how to get the revised standard from the IEEE.  As I concluded my blog, I indicated that the final editorial review and formatting for publication was underway and that I would report back when this work was completed.

IEEE Std 1666-2011I can report that the IEEE SA concluded their editing of the specification and it is now ready for download.  Many of you know the prior version of the SystemC standard was available for free download and have wondered if this would be the same for this revision update.  The good news is the revision update is available as a free download as well.  If you wish to have a printed and bound copy, that too is available, but that will have to be purchased.

IEEE Std. 1666-2011 is part of the “IEEE Get Program” that offers individuals the ability to retrieve, download and print one copy of the standard for free.  Click on the link above to get your personal copy of the standard.  You will need to share some basic information with the IEEE on your user type (Academic, System/Semiconductor Company,  EDA Company, IP Company or Other).  This is certainly worth if for a free copy.

The original standard, IEEE Std. 1666™-2005, had more than 50,000 free downloads since it was made available and I expect this version to do even better.  With the addition of TLM to the standard and the move up in abstraction to handle system design requirements, the need for this standard is even more pressing today.

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10 November, 2011

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support

A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.

For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI).  OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard.  TLM is important to SystemC, but it has also been leveraged outside of it.

We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog.  This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).

If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity.  The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first.  This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.

As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together.  And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together.  I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.

For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting.  I will share with you when it is ready to use as well as how to get it and where to find it.

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21 June, 2011

System Standards Worlds Initiate Unification

accellera SystemC Logo

Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here.

While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs.  At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit?  Where are they going?,” technical members of the two communities gathered to ponder answers to those questions.  At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.

DAC Slide 5

Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community.  A lot has transpired since then.  Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively.  And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.

In this evolution, it became clear to me that each organization was “completing” the other.  OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™).  As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.

In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.

What do you think about the unification?

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17 June, 2011

How do your favorites rank?

Have you ever wondered how popular the different IEEE standards for electronic design automation are? Have you ever wondered which ones show the least interest? When buying books online, popular book buying websites sites will rank customer purchases. Many newspapers manage lists that you can consult to determine what is the most popular; what has the highest demand. But if you have purchased any IEEE standards, you will know this information is not available from the IEEE Store or the IEEE XPlore platform.

On May 4th, the IEEE Standards Association announced its collaboration with Techstreet to create the New IEEE Standards Store.  Until now, anyone who wanted to order a single standard had to use a more complex system that even made it hard to share a permanent link to one’s favorite standard with another.  Just look at the Accellera homepage for an example of where to get the SystemVerilog (IEEE Std. 1800™) standard.  At the writing of this blog, it simply points to www.ieee.org.  [I will share the fact the IEEE’s new site now has fixed links that can now be used to help others find the most current SystemVerilog standard with the Accellera.]

But back to what is the most popular IEEE EDA standards… Any guesses?

Before I delve into those details, let me say the ranking is just by ordinal.  The New IEEE Standards Store shares no information on the actual number of standards purchased.  So the difference between #1 and #10 could be just 10 copies.  It probably isn’t, but it could be.  But talking about #10, why is it even on the list?  The IP-XACT standard (IEEE Std. 1685™) is available for free under the IEEE Get Program.  Under this program you can download a PDF of the IEEE standard for free.  If you want a printed version, you can print your own copy from the free one you download.  Back in December 2010, Accellera reported that since the IEEE started to offer IP-XACT for free, there had been 1200 downloads.  It also looks like many people did not want the hassle to print and simply ordered the print version directly from the IEEE.  The other IEEE EDA standard offered free is SystemC©  And this is probably the reason it is in 32nd place.  It is very popular in terms of the number of free downloads.

And yes, if you search for the those two standards on the New IEEE Standards Store, you will find you can order print copies there and if you read the small print below, you will see there is a link to take you to the free online versions.

Harry Foster has issued several research reports on the popularity of one language or format the past several months.  In his last blog, he discussed which of the design and verification languages are ranked high and those, well, not so high.  And I guess I feel best to share the correlation between his findings and these more “anecdotal” results from the New IEEE Standards Store.  I have been party to many at the top standards  (Verilog/SystemVerilog) and party to the “least highest” (yes, I can’t say the least liked) VITAL 2000.  For vindication, I will note that VITAL-95 comes in at #18.  In whole, it appears to me that the New IEEE Standards Store ordinal rankings of EDA standards matches the scientific data from the research Harry has reported.

Below is the full ranking of IEEE EDA standards.  Where are your favorites?

1 IEEE 1364-2001 Verilog Hardware Description Language
2 IEEE 1800-2009 SystemVerilog–Unified Hardware Design, Specification, and Verification Language
3 IEEE 1076-2002 VHDL Language Reference Manual
4 IEEE 1076-1993 VHDL Language Reference Manual
5 IEEE 1499-1998 Interface for Hardware Description Models of Electronic Components
6 IEEE 1364-1995 Hardware Description Language Based on the Verilog® Hardware Description Language
7 IEEE 1800-2005 SystemVerilog: Unified Hardware Design, Specification and Verification Language
8 IEEE 1076.2-1996 VHDL Mathematical Packages
9 IEEE 1076.1-1999 VHDL Analog and Mixed-Signal Extensions
10 IEEE 1685-2009 IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows
11 IEEE 1850-2005 Property Specification Language (PSL)
12 IEEE 1076c-2007 VHDL Language Reference Manual – Procedural Language Application Interface
13 IEEE 1164-1993 Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
14 IEEE 1850-2010 Property Specification Language (PSL)
15 IEEE 1076.6-2004 VHDL Register Transfer Level (RTL) Synthesis
16 IEEE 1801-2009 Design and Verification of Low Power Integrated Circuits
17 IEEE 1481-2009 Integrated Circuit (IC) Open Library Architecture (OLA)
18 IEEE 1076.4-1995 VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification
19 IEEE/IEC 61691-5-2004 IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification
20 IEEE 1647-2008 Functional Verification Language e
21 IEEE 1076.1.1-2011 VHDL Analog and Mixed-Signal Extensions — Packages for Multiple Energy Domain Support
22 IEEE/IEC 61691-7-2009 Behavioural languages – Part 7: SystemC Language Reference Manual
23 IEEE 1076-1987 VHDL Language Reference Manual
24 IEEE 1076.1.1-2004 VHDL Analog and Mixed-Signal Extensions—Packages for Multiple Energy Domain Support
25 IEEE 1076.3-1997 VHDL Synthesis Packages
26 IEEE/IEC 61523-3-2004 IEC 61523-3 Ed.1 (IEEE Std 1497(TM)-2001): Delay and Power Calculation Standards – Part 3: Standard Delay Format (SDF) for the Electronic Design Process
27 IEEE 1076/INT-1991 Interpretations: IEEE Std 1076-1987, IEEE Standard VHDL Language Reference Manual
28 IEEE/IEC 62531-2007 IEC 62531 Ed. 1 (2007-11) (IEEE Std 1850-2005): Standard for Property Specification Language (PSL)
29 IEEE 1076.6-1999 VHDL Register Transfer Level Synthesis
30 IEEE 1647-2006 Functional Verification Language “e”
31 IEEE/IEC 61691-6-2009 Behavioural languages – Part 6: VHDL Analog and Mixed-Signal Extensions
32 IEEE 1666-2005 SystemC® Language Reference Manual
33 IEEE/IEC 61691-1-1-2004 IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages – Part 1-1: VHDL Language Reference Manual
34 IEEE 1364-2005 Verilog Hardware Description Language
35 IEEE/IEC 61691-4-2004 IEC 61691-4 Ed.1 (IEEE Std 1364(TM)-2001): Behavioural Languages – Part 4: Verilog® Hardware Description Language
36 IEEE 1076.4-2000 VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification

Learn more about the New IEEE Standards Store

There is much more to the New IEEE Standards Store than just the rankings of the standards we use in electronic design automation.  As I mentioned, it is easier to share fixed links to IEEE standards.  And if you want to track IEEE standards development – and don’t want to have to register your email address with the actual committee developing it just to know when they are done and a standard is ready – you can register to be notified when a new standard is ready.  The New IEEE Standards Store will notify you when a new one is ready.

Check out the short, one minute, video below to learn more about the New IEEE Standards Store.

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12 May, 2011

The standards developing organizations defining and updating front-end EDA standards will be at DAC in force.  And from the looks of if, they are getting an early start to DAC with updates on IEEE, Accellera and OSCI standards at Sunday workshops.  The Sunday workshops may be of particular interest to verification engineers interested in UVM and systems designers interested in SystemC AMS.

Following the workshops, there will be a half-day meeting of the North American SystemC Users Group on Monday where users will share their SystemC experiences.  The following morning, Accellera will host its annual DAC breakfast where the UVM users will meet to share their experiences.  A lively conversation is expected.

Sunday – June 5, 2011

UVM LogoDAC Workshop on Universal Verification Methodology (UVM) – Verifying Blocks to IP to SOCs and Systems

Time: 10:00 AM — 1:00 PM
Location: San Diego Convention Center Room 33A
Summary: The Accellera Verification IP Technical Subcommittee (VIP-TSC), building on over two years of work by verification experts from around the world, released Universal Verification Methodology (UVM) in February 2011. This workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
GET MORE DETAILS

Registration: This is an official DAC sponsored event and DAC registration required.


systemc_amsDAC Workshop on Using the Power of the SystemC AMS Extensions

Time: 10:00 AM — 6:00 PM
Location: San Diego Convention Center Room 33B
Summary: Today’s embedded systems interact more and more tightly with the analog physical environment; where digital HW/SW subsystems become functionally interwoven with analog/mixed-signal (AMS) blocks such as RF interfaces, power electronics, or sensors and actuators. Examples are software defined radios, sensor networks, automotive applications, or systems for image sensing. This requires new means to model and simulate the interaction between AMS subsystems and HW/SW subsystems at functional and architecture levels. Especially for this purpose, the SystemC language standard has been extended with powerful AMS capabilities to tackle the challenges in heterogeneous electronic system-level (ESL) design. You will get a good working knowledge of SystemC AMS by attending the workshop.
GET MORE DETAILS

Registration: This is an official DAC sponsored event and DAC registration required.

Monday – June 6, 2011

SystemC Logo

North American SystemC Users Group Meeting

Time: 8:30 AM – 12:00 PM
Location: OMNI Hotel
Room Salon AB
675 Laurel Street
San Diego, CA 92101
Summary: The North American SystemC Users Group  explores the newest advancements in sustainable and flexible solutions for system-level design using SystemC.
GET MORE DETAILS

Registration: This event is free and open to all registered DAC attendees. Click here to reserve your seat

Tuesday – June 7, 2011

accelleraAccellera Breakfast at DAC: UVM User Experiences

Time: 7:00 AM – 8:30 AM
Location: San Diego Convention Center Room 25AB
Summary: With the introduction of Accellera’s Universal Verification Methodology (UVM) user interest and adoption has been rapidly growing. You are invited to join us and share the experience with fellow users. During the breakfast, you will hear from real users who have migrated to, and/or applied, the UVM for the first time.  Accellera Verification IP Technical Subcommittee (VIP-TSC) participants will provide their insights on UVM. We invite you to take part in the open discussion to foster greater adoption of this important verification standard.
GET MORE DETAILS

Registration: This event is free open to all registered DAC attendees. Click here to reserve your seat

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15 April, 2011

Watch DVCon Co-Located Event Presentations

Two presentations from the second annual SystemC Day at DVCon 2011 are available now.  The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos.  SystemC Day brought users together to discuss the current state of the market for ESL design and the pending content of the SystemC standard that is current in final ballot by the IEEE.

To view the video presentations, you will need to register with the Open SystemC Initiative.

Jim Hogan, Vista Ventures LLC, California, USA
Keynote Presentation: “Navigating the SoC Era”

Abstract: SoCs are becoming ubiquitous in semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.

Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.

John Aynsley, Doulos Ltd., UK
The New IEEE 1666 SystemC Standard

Abstract: The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.

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22 February, 2011

systemcday2011curveOpen SystemC Initiative Tackles the Future

If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM).  And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days.  But you may also want to bring a colleague to attend the SystemC Day activities.

For SystemC Day at DVCon, the morning session is the North American SystemC Users Group (NASCUG) meeting that features a Keynote presentation by industry luminary Jim Hogan.

Jim HoganJim’s keynote will be on “Navigating the SoC Era.”  NASCUG attendance is free, but you need to register to attend.

Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.

After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.

In the afternoon, a tutorial on software-driven verification titled Software-Driven Verification Using TLM-2.0 Virtual Platforms will be presented by experts from the OSCI, Accellera and the user community that are using standards-based methodologies in production today.  The afternoon tutorial requires registration at the DVCon website.  The tutorial is free for conference attendees.  A small fee is charged for those who wish to attend this tutorial only.  Is software-driven verification in your future?  Chances are highly likely it is and I suggest you look at attending this event.

I’ll see you there!

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3 February, 2011

ieee_mb_blueIEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi

I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi.  In the last year, the IEEE announced it opened an office in Bangalore, India.  This is the fourth IEEE office in Asia, following China, Japan and Singapore.

A large number of IEEE’s members reside in India and the EDA standards get a lot of use and attention in India.  There is a strong and thriving IEEE Std 1800™ SystemVerilog community in India that are helping to extend the verification capabilities of the language.  As the IEEE office gets setup, I look forward to it to help better coordinate standards development of a global community of companies and individuals.

Agenda: Bangalore, India Workshop (Register)
Location: Mentor Graphics, Bangalore

8:30 Registration opens
9:00 Welcome–Pamela Kumar (IBM)
9:05 IEEE-SA and the World of Standards
Dennis Brophy, Member, Board of Governors, IEEE-SA
Director of Business Development, Mentor Graphics
9:45 Standards in Design Automation: Influencing Design and Verification Methodologies
Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666)
Yatin Trivedi, Member, Standards Education Committee, IEEE-SA
Director of Standards, Synopsys
10:30 Tea-Break
11:00 Impact of Standards in Design Environment
Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA
CAD Manager, Freescale
11:30 Anecdotes of Participation in Standards Activities
Srinivasan Venkataramanan, CTO, CVC, Bangalore
11:45 Panel Discussion: Standards, Industry and Academia
Moderator: Pamela Kumar
Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra, SriniVenkataramanan, Anuradha Srinivasan (Intel)
12:30 Conclusion & Thank You

A set of IEEE-SA Board of Governors meetings will be held at the beginning of the the week of February 7th.  And in addition to the meeting on design automation standards in Bangalore, a group of workshops are also planned in Mumbai on 4 February 2011 on Cloud Computing and Smart Grid by other colleagues I volunteer with on the IEEE-SA Board of Governors.   There are more IEEE-SA events planned for the week of February 7th and a full list can be found here.

For those who wish to join the New Delhi design automation workshop, some details of it can be found below.

Agenda: New Delhi, India Workshop (Register)
Location: IIT

8:30 Registration opens
9:00 Welcome—Karen Bartleson (Synopsys)
9:05 IEEE-SA and the World of Standards
Dennis Brophy, Member, Board of Governors, IEEE-SA
Director of Business Development, Mentor Graphics
9:45 Standards in Design Automation: Influencing Design and Verification Methodologies
Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666)
Yatin Trivedi, Member, Standards Education Committee, IEEE-SA
Director of Standards, Synopsys
10:30 Tea-Break
11:00 Impact of Standards in Design Environment
Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA
CAD Manager, Freescale
11:30 Anecdotes of Participation in Standards Activities
Srinivasan Venkataramanan, CTO, CVC, Bangalore
11:45 Panel Discussion: Standards, Industry and Academia
Moderator: Karen Bartleson
Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra
12:30 Conclusion & Thank You

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