Posts Tagged ‘systemc’
Getting Your Standards Update @ DAC 2011
The standards developing organizations defining and updating front-end EDA standards will be at DAC in force. And from the looks of if, they are getting an early start to DAC with updates on IEEE, Accellera and OSCI standards at Sunday workshops. The Sunday workshops may be of particular interest to verification engineers interested in UVM and systems designers interested in SystemC AMS.
Following the workshops, there will be a half-day meeting of the North American SystemC Users Group on Monday where users will share their SystemC experiences. The following morning, Accellera will host its annual DAC breakfast where the UVM users will meet to share their experiences. A lively conversation is expected.
Sunday – June 5, 2011 |
DAC Workshop on Universal Verification Methodology (UVM) – Verifying Blocks to IP to SOCs and Systems
Time: 10:00 AM — 1:00 PM
Location: San Diego Convention Center Room 33A
Summary: The Accellera Verification IP Technical Subcommittee (VIP-TSC), building on over two years of work by verification experts from around the world, released Universal Verification Methodology (UVM) in February 2011. This workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
GET MORE DETAILS
Registration: This is an official DAC sponsored event and DAC registration required.
DAC Workshop on Using the Power of the SystemC AMS Extensions
Time: 10:00 AM — 6:00 PM
Location: San Diego Convention Center Room 33B
Summary: Today’s embedded systems interact more and more tightly with the analog physical environment; where digital HW/SW subsystems become functionally interwoven with analog/mixed-signal (AMS) blocks such as RF interfaces, power electronics, or sensors and actuators. Examples are software defined radios, sensor networks, automotive applications, or systems for image sensing. This requires new means to model and simulate the interaction between AMS subsystems and HW/SW subsystems at functional and architecture levels. Especially for this purpose, the SystemC language standard has been extended with powerful AMS capabilities to tackle the challenges in heterogeneous electronic system-level (ESL) design. You will get a good working knowledge of SystemC AMS by attending the workshop.
GET MORE DETAILS
Registration: This is an official DAC sponsored event and DAC registration required.
Monday – June 6, 2011 |
North American SystemC Users Group Meeting
Time: 8:30 AM – 12:00 PM
Location: OMNI Hotel
Room Salon AB
675 Laurel Street
San Diego, CA 92101
Summary: The North American SystemC Users Group explores the newest advancements in sustainable and flexible solutions for system-level design using SystemC.
GET MORE DETAILS
Registration: This event is free and open to all registered DAC attendees. Click here to reserve your seat
Tuesday – June 7, 2011 |
Accellera Breakfast at DAC: UVM User Experiences
Time: 7:00 AM – 8:30 AM
Location: San Diego Convention Center Room 25AB
Summary: With the introduction of Accellera’s Universal Verification Methodology (UVM) user interest and adoption has been rapidly growing. You are invited to join us and share the experience with fellow users. During the breakfast, you will hear from real users who have migrated to, and/or applied, the UVM for the first time. Accellera Verification IP Technical Subcommittee (VIP-TSC) participants will provide their insights on UVM. We invite you to take part in the open discussion to foster greater adoption of this important verification standard.
GET MORE DETAILS
Registration: This event is free open to all registered DAC attendees. Click here to reserve your seat
SystemC Day 2011 Videos Available Now
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state of the market for ESL design and the pending content of the SystemC standard that is current in final ballot by the IEEE.
To view the video presentations, you will need to register with the Open SystemC Initiative.
Jim Hogan, Vista Ventures LLC, California, USA
Keynote Presentation: “Navigating the SoC Era”
Abstract: SoCs are becoming ubiquitous in semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.
Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
John Aynsley, Doulos Ltd., UK
The New IEEE 1666 SystemC Standard
Abstract: The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.
Tags: 1666, esl, IEEE, Jim Aynsley, Jim Hogan, OSCI, SoC, systemc
DVCon: The Present and the Future
Open SystemC Initiative Tackles the Future
If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM). And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days. But you may also want to bring a colleague to attend the SystemC Day activities.
For SystemC Day at DVCon, the morning session is the North American SystemC Users Group (NASCUG) meeting that features a Keynote presentation by industry luminary Jim Hogan.
Jim’s keynote will be on “Navigating the SoC Era.” NASCUG attendance is free, but you need to register to attend.
Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.
In the afternoon, a tutorial on software-driven verification titled Software-Driven Verification Using TLM-2.0 Virtual Platforms will be presented by experts from the OSCI, Accellera and the user community that are using standards-based methodologies in production today. The afternoon tutorial requires registration at the DVCon website. The tutorial is free for conference attendees. A small fee is charged for those who wish to attend this tutorial only. Is software-driven verification in your future? Chances are highly likely it is and I suggest you look at attending this event.
I’ll see you there!
Tags: dvcon, Jim Hogan, nascug, OSCI, systemc, TLM, TLM 2.0, UVM
IEEE Standards in India
IEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi
I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi. In the last year, the IEEE announced it opened an office in Bangalore, India. This is the fourth IEEE office in Asia, following China, Japan and Singapore.
A large number of IEEE’s members reside in India and the EDA standards get a lot of use and attention in India. There is a strong and thriving IEEE Std 1800™ SystemVerilog community in India that are helping to extend the verification capabilities of the language. As the IEEE office gets setup, I look forward to it to help better coordinate standards development of a global community of companies and individuals.
Agenda: Bangalore, India Workshop (Register)
Location: Mentor Graphics, Bangalore
| 8:30 | Registration opens | |
| 9:00 | Welcome–Pamela Kumar (IBM) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
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| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
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| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
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| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
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| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Pamela Kumar Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra, Srini Venkataramanan, Anuradha Srinivasan (Intel) |
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| 12:30 | Conclusion & Thank You |
A set of IEEE-SA Board of Governors meetings will be held at the beginning of the the week of February 7th. And in addition to the meeting on design automation standards in Bangalore, a group of workshops are also planned in Mumbai on 4 February 2011 on Cloud Computing and Smart Grid by other colleagues I volunteer with on the IEEE-SA Board of Governors. There are more IEEE-SA events planned for the week of February 7th and a full list can be found here.
For those who wish to join the New Delhi design automation workshop, some details of it can be found below.
Agenda: New Delhi, India Workshop (Register)
Location: IIT
| 8:30 | Registration opens | |
| 9:00 | Welcome—Karen Bartleson (Synopsys) | |
| 9:05 | IEEE-SA and the World of Standards Dennis Brophy, Member, Board of Governors, IEEE-SA Director of Business Development, Mentor Graphics |
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| 9:45 | Standards in Design Automation: Influencing Design and Verification Methodologies Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666) Yatin Trivedi, Member, Standards Education Committee, IEEE-SA Director of Standards, Synopsys |
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| 10:30 | Tea-Break | |
| 11:00 | Impact of Standards in Design Environment Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA CAD Manager, Freescale |
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| 11:30 | Anecdotes of Participation in Standards Activities Srinivasan Venkataramanan, CTO, CVC, Bangalore |
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| 11:45 | Panel Discussion: Standards, Industry and Academia Moderator: Karen Bartleson Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra |
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| 12:30 | Conclusion & Thank You |
Tags: 1666, 1735, 1800, 1801, IEEE-SA, Standards, systemc, SystemVerilog, upf
IEC’s 47th General Assembly Meeting Opens
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday. On Monday the group reported out conclusions of all the committee’s working groups.
Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users. In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I/O Buffer Information Specification. IBIS 4.2 is on the work plan for standardization. The Japanese National Committee’s technical report from JEITA on their Bird’s eye View of Design Language (BVDL) was also submitted as an official submission.
The TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems. From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).
Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards. For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010). The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo. Different countries have different rules and laws to recognize standards. The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.
Tags: 1076, 1364, 1666, 1800, dual-logo, iec, IEEE, Standards, systemc, SystemVerilog, TC93, verilog, vhdl, WG2
North American SystemC User Group (NASCUG) Meeting at DAC
You Are Invited – Register Now!
(seating is limited)
Sunday, June 13
2:30pm – 6:00pm
Anaheim Hilton, California Ballroom A
Anaheim, California
www.nascug.org
On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.
As a global sponsor of OSCI events, Mentor encourages the SystemC community to meet at this event to learn more about SystemC advances and applications.
Technical presentations on architectural modeling, transaction-level modeling and analog/mixed-signal design using SystemC™ will be featured. You will be able to interact with colleagues and industry experts, and find out first-hand how system-level design with SystemC has become a nuts-and-bolts part of the designer’s toolbox.
AGENDA
| 2:30pm – 3:00pm | Registration |
| 3:00pm – 3:10pm | Welcome & Agenda |
| 3:10pm – 3:30pm | OSCI and Technical Working Group Update Eric Lish, OSCI Chairman |
| 3:30pm – 5:50pm | Technical Presentations: |
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| 5:50pm – 6:00pm | Meeting Close and Prize Drawing |
Special Invitation to DAC 47 Kick-Off Reception
6:00pm – 7:30pm
Anaheim Hilton, Pacific Ballroom
The DAC Executive Committee and the EDA Consortium invite the NASCUG XIII participants to attend their annual DAC Kick-Off Reception at this year’s conference in Anaheim, California. The reception begins just as the user group meeting concludes. Both events are in the Anaheim Hilton and located close to each other. Register Now to attend the Sunday reception.
Tags: ams, cci, dac, edac, nascug, OSCI, Standards, systemc, TLM
SystemC Day Videos from DVCon Available Now
Noted EDA analyst and guru Gary Smith delivered keynote address: “ESL: Where We Are and Where We’re Going”
OSCI sponsored the first annual SystemC Day at DVCon 2010. The presentations were video recorded and are available for free for those who missed DVCon or who may wish to see them again. Gary Smith’s presentation (registration required) and OSCI chair, Eric Lish’s OSCI Update lead the video set from SystemC Day.
The 12th North American SystemC Users Group (NASCUG) meeting was part of SystemC Day at DVCon and featured technical presentations on architectural modeling, verification, and analog/mixed-signal design using SystemC.
OSCI ON YOUTUBE: More videos of users and their perspectives on SystemC events and activities can be found via the OSCI channel on YouTube: http://www.youtube.com/officialsystemc
Click here for completing listing of the following technical presentations.
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The Metaport: A Technique for Managing Code Complexity Jack Donovan, HighIP Design, Texas, USA The metaport is a coding style that can effectively manage code complexity for complex ESL models, especially models that are intended for high-level synthesis. This presentation will give an overview of the metaport concept and dive into the details of a possible implementation. |
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OCP Socket Modeling with TLM-2.0 Hervé Alexanian, Sonics Inc., California, USA This presentation discusses work performed by the OCP-IP Committee, specifically modeling that OCP built upon the TLM-2.0 standard. |
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ADL Synthesis using ArchC Samuel Goto, Master student at UNICAMP The design and implementation of processors is a complex task. Architecture Description Languages (ADLs) were created to extend existing HDLs, to ease the process of developing and prototyping an architecture by providing a set of tools and algorithms to optimize and automate some of the tedious parts. While much has been done on the specification and business levels of ADLs, there is a huge gap between ADL specifications/simulators and real life processors written in RTL. This project addresses the issues of bringing an ADL description to the RTL level, and reports the development of an extension of ArchC to support this level. |
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Look Ma, No Clocks! Improving Model Performance David Black, XtremeEDA, Texas, USA This tutorial-style presentation illustrates some techniques to avoid the inclusion of clocks in SystemC simulations and provide results of simple experiments showing the simulation performance benefits. Concepts discussed include synchronization, clock-free timers, and the effects of clocks on performance. A proposal is made for a simple SystemC class that can simplify coding when clocks are thought to be needed. |
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TLM-driven Design and Verification Methodology Brian Bailey, independent consultant SystemC is well on the road to adoption in a number of areas within the Electronic System Level (ESL) space, but many of those are separated islands today. Virtual Prototyping has seen a huge leap forward with the standardization of TLM 2.0. SystemC is also being used successfully for high-level synthesis at the module level, but to make SystemC pervasive, there must be a link between the applications. In addition, to reap the maximum productivity gains from a migration to a higher-level of abstraction, the verification methodology must also change in significant ways. In this presentation we will explore a new TLM-driven design and verification methodology that is being developed within Cadence, critiqued by their customers and documented in a book, which will be released over a number of months as pieces of it mature. |
SystemC Day at DVCon
SystemC User Group Meeting & DVCon Tutorial Featured
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to support and advance SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22.
Mentor Graphics is one of the sponsors for the event and we will share updates on products that support SystemC during the SystemC Supplier Showcase between 10:00 a.m. – 2:00 p.m. Visit us at the Showcase or at the DVCon tradeshow.
How to Register
Admission is free with advance registration to the North American SystemC Users Group Meeting (NASCUG 12) and complimentary lunch. The afternoon tutorial is part of the DVCon program and requires separate registration.
- NASCUG 12 Meeting and Lunch
Register at: www.mod-marketing.com/osci (FREE)
- DVCon Tutorial: The OSCI TLM-2.0 Standard and Synthesis Subset
Register at: www.dvcon.org/reg.html ($60 DVCon Fee)
Agenda
| 8:30 am – 12:00 pm | NASCUG 12 Meeting (Full agenda at www.nascug.org) |
| Meeting Includes: | |
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| 10:00 am – 2:00 pm | Sponsor Tabletop Exhibits |
| 12:00 pm – 1:30 pm | OSCI Sponsored Lunch |
| 1:30 pm – 5:00 pm | DVCon Tutorial: “The OSCI TLM-2.0 Standard and Synthesis Subset Tutorial information |
| 5:00 pm | DVCon Hosted Reception |
Tags: dvcon, esl, gary smith, nascug, OSCI, Standards, systemc
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
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