Posts Tagged ‘Standards’
Download the standard now – at no charge
The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance and enhancement to the IEEE. Further – Courtesy of Accellera – the standard is available for download without charge directly from the IEEE.
The latest update to IEEE 1801 is ready for download. It joins other EDA standards, like SystemVerilog and SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF. (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)
The official IEEE announcement on the standard’s publication can be found here. And the official Accellera announcement that it has partnered with the IEEE-SA to offer the standard to all at no charge can be found here. This revision of the standard had one of the largest number of IEEE-SA entity members of any corporate standards program. Participation from the IEEE-SA global community of entity participants ensures the needs of a broad set of companies are captured to support this worldwide standard.
Just In Time For DAC
DAC 2013 has many events that will allow you to learn more about the new standard and how to use it to your maximum benefit. And for those who cannot attend DAC, visit the Verification Academy, you will find the Low Power sessions cover the new standard as well. [Registration required; restrictions apply.]
Topic: DAC Workshop: Low-Power Design with the New IEEE 1801-2013 Standard
Date: 2 June 2013
Time: 1:00 p.m. – 5:00 p.m.
Location: Convention Center: Room 18C
Registration: Official DAC Workshop registration required ($). For more information and to register, click here.
Accellera Breakfast & Town Hall Meeting
Topic: The Standard for Low Power Design and Verification is here! What’s next?
Date: 3 June 2013
Time: 7:00 a.m. – 8:45 a.m.
Location: Convention Center: Ballroom D
Registration: This is a free Accellera event, but registration is required. Form more information click here and to register, click here.
Topic: “Low Power Monday”
Date: 3 June 2013
Time: 11:00 a.m. – 6:00 p.m.
Location: Tradeshow Floor – Booth 1215
Registration: The DAC Tradeshow floor is open to all DAC registrants. Visit www.dac.com to register.
The Verification Academy is open to all DAC registrants. There are no restrictions and we invite everyone to visit booth 1215 for Low Power sessions that may be of interest to you on Monday. To help judge attendance, please feel free to pre-register at here. I look forward to see you there as you will find me here most of the time Monday-Wednesday.
|11:00 a.m. – 12:00 p.m.||Low Power Verification||Tim Jordon
|1:00 p.m. – 2:00 p.m||What’s New in UPF 2.1?||Erich Marschner
IEEE 1801 Vice-chair
|2:00 p.m. – 3:00 p.m.||UPF-Based Verification for Cypress PSOC||Ellie Burns
|4:00 p.m. – 5:00 p.m.||Optimizing for Power Efficient Design||Abhishek Ranjan
|5:00 p.m. – 6:00 p.m.||IEEE 1801 UPF Commands and Methodology||John Biggs
IEEE 1801 Chair
If you are coming to DAC and participating in the DAC Low Power Workshop on Sunday, or in other events, download your person copy of the new IEEE 1800-2013 standard today. The PDF form allows you to take it with you and read it using your favorite e-reader or i-device. Let’s me know what you think of the standard. And – See you at DAC!
Power Aware Verification Course Modules Released
I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to out do the other when it came to puns. So it is understandable why the topic of low power standards takes me back to these fun exchanges.
But low power design and verification is a serious issue that design teams continue to grapple. To take advantage of emerging support of the new low power standard takes time and energy on part of practicing engineers and design teams. More information on what IEEE Std. 1801™-2013 (Unified Power Format) is and how you can use it is needed.
Back in March 2013 I blogged that the revised IEEE low power standard had been approved. I also mentioned there would be a short wait until the standard itself was published. And, indeed, we continue to wait for the final editing of the standard. I shared a link to a short article on the content of the standard, but more information is needed.
To address this need, the Verification Academy has added a course on Power Aware Verification. There are six (6) sessions that will introduce you to power aware verification, UPF and walk you through an example to illustrate the use of the standard in more detail in about 1.5 hours. In order to access the course material you will need to be a “full access” registrant of Verification Academy. There is no fee for this, but restrictions apply.
In addition to watching the video course sessions online, you can also download the presentations and MP4 videos of the course for offline viewing.
The six course sessions are:
- Introduction to Power Aware Verification (9 minutes)
- Overview of UPF (13 minutes)
- Getting Started with UPF (23 minutes)
- A Simple UPF Example (17 minutes)
- UPF 2.0 Enhancements (11 minutes)
- Using Supply Set (18 minutes)
We are interested to get your feedback on the Power Aware Verification course and learn what additional sessions you think would help you get AMP’ed up to further the need to conserve energy. Let us know!
This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study.
In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 study, no other industry studies were conducted, which left a void in identifying industry trends.
To address this void, Mentor Graphics commissioned Far West Research to conduct an industry study on functional verification in the fall of 2007. Then in the fall of 2010, Mentor commissioned Wilson Research Group to conduct another functional verification study. Both of these studies were conducted as blind studies to avoid influencing the results. This means that the survey participants did not know that the study was commissioned by Mentor Graphics. In addition, to support trend analysis on the data, both studies followed the same format and questions (when possible) as the original 2002 and 2004 Collett studies.
In the fall of 2012, Mentor Graphics commissioned Wilson Research Group again to conduct a new functional verification study. This study was also a blind study and follows the same format as the Collett, Far West Research, and previous Wilson Research Group studies. The 2012 Wilson Research Group study is one of the largest functional verification studies ever conducted. The overall confidence level of the study was calculated to be 95% with a margin of error of 4.05%.
Unlike the previous Collett and Far West Research studies that were conducted only in North America, both the 2010 and 2012 Wilson Research Group studies were worldwide studies. The regions targeted were:
- North America:Canada,United States
- Asia (minusIndia):China,Korea,Japan,Taiwan
The survey results are compiled both globally and regionally for analysis.
Another difference between the Wilson Research Group and previous industry studies is that both of the Wilson Research Group studies also included FPGA projects. Hence for the first time, we are able to present some emerging trends in the FPGA functional verification space.
Figure 1 shows the percentage makeup of survey participants by their job description. The red bars represents the FPGA participants while the green bars represent the non-FPGA (i.e., IC/ASIC) participants.
Figure 1: Survey participants job title description
Figure 2 shows the percentage makeup of survey participants by company type. Again, the red bars represents the FPGA participants while the green bars represents the non-FPGA (i.e., IC/ASIC) participants.
Figure 2: Survey participants company description
In a future set of blogs, over the course of the next few months, I plan to present the highlights from the 2012 Wilson Research Group study along with my analysis, comments, and obviously, opinions. A few interesting observations emerged from the study, which include:
- FPGA projects are beginning to adopt advanced verification techniques due to increased design complexity.
- The effort spent on verification is increasing.
- The industry is converging on common processes driven by maturing industry standards.
My next blog presents current design trends that were identified by the survey. This will be followed by a set of blogs focused on the functional verification results.
Also, to learn more about the 2012 Wilson Reserach Group study, view my pre-recorded Functional Verification Study web-seminar, which is located out on the Verification Academy website.
Quick links to the 2012 Wilson Research Group Study results (so far…)
- Part 1 – Design Trends
Tags: accellera, Assertion-Based Verification, formal verification, functional coverage, functional verification, IEEE, Simulation, Standards, SystemVerilog, UVM, Verification Academy, Verification Methodology, verilog, vhdl
IEEE 1801™-2013 Enters Pre-Publish Phase
The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now. Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013). The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.
If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).
As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication. So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet. So I won’t do that. If you do need something, the superseded version from 2009 is the only one available at this moment. I will keep you updated as to when it is published and ready for access to the global design community.
Mentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled The Evolution of UPF: What’s Next? (Free access; no registration required; 81KB)
Erich gives a good introduction to the new standard, also known as UPF 2.1. He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.
Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot. This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification. If you are interested to join in with the IEEE 1801 team, visit here for more information.
DVCon UPF Tutorial
The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon. For those who registered for the conference, the tutorial presentation is still available online. Unfortunately, the material has not yet been made available to the general public. If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy. The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.
As for planning you can do now. The IEEE 1801 team will host a tutorial at DAC on Sunday. I will share more information with you on that once the DAC registration site goes live. Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.
Download the standard now – at no charge!
The latest update to the SystemVerilog standard is now ready for download. It joins other EDA standards, like SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF. (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)
Over the years Accellera came to understand that many people continued to use the freely available version that seeded the initial IEEE 1800 SystemVerilog standard. Since it is significantly out of date, Accellera collaborated with the IEEE Standards Association to ensure the latest version of the SystemVerilog standard would be freely available in electronic form to all whom wish to download it. Accellera now hopes all those old 3.1a versions that everyone has and uses can now be placed in the archives.
The new version of standard should be used by the UVM (Universal Verification Methodology) community as the definitive specification of the SystemVerilog standard upon which UVM is built. It goes very well with the UVM Cookbook and the Coverage Cookbook.
From Mentor’s perspective, it also makes a good companion to the Questa verification platform and complements our latest product update in which we announced support for the IEEE 1800-2012 SystemVerilog standard among other things.
If you have not done so already, download your copy now by clicking here.
Learn about new standards, industry surveys and trends
This year’s DVCon is set and if you have not yet registered, you can do it now – or just show up! If you want to secure seating at some of the Monday tutorial events, I strongly encourage pre-registration to ensure you can secure a seat. And if you just want to see the exhibits and chat with suppliers, that’s free.
The IEEE low power format is set to close on its current round standardization shortly and DVCon is a great place to learn all about it from the experts. Harry Foster will update the DVCon attendees on design and verification trends over lunch on Tuesday and later that afternoon, Mentor CEO, Wally Rhines will offer this year’s DVCon keynote. His keynotes are always insightful and entertaining. And if you want to catch me, you can find me with the Mentor staff at the Mentor exhibit booth. Or just follow @dennisbrophy on Twitter and I will share info on paper presentations and other happenings. For more details on the events mentioned above, see below. For more information DVCon in general, visit the website at www.dvcon.org.
Monday | February 25th | 1:30pm – 4:30 | Fir Ballroom
Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™
The past few years, the IEEE P1801™ (Unified Low Power – UPF) Working Group has been busy working on an update to the industry’s standard for low power design, verification and implementation. Accellera has brought together experts from many EDA tool suppliers and users for this tutorial. Attendees can expect to gain a detailed understanding of of the IEEE standard (concepts, terminology & features) as well as an understanding of the practical aspects to apply UPF in real world flows.
The following experts will be help you learn about the new standard – and will be available to interact with at the conclusion of the tutorial.
Tuesday | February 26th | 11:30am – 12:45pm | Pine/Cedar Ballroom
The Changing Landscape in Functional Verification: Industry Trends, Challenges, and Solutions
Presented by Harry Foster
Mentor Graphics invites you to join us for lunch—where we will present, for the first time publicly, highlights from this year’s Wilson Research Group Functional Verification Study. Be the first on your block to learn the latest verification trends, challenges, and solutions.
Learn more, then register.
Tuesday | February 26th | 3:30pm – 4:30pm | Oak/Fir Ballroom
Speaker: Wally Rhines, Chairman and CEO of Mentor Graphics
As a thought provoking, timely, and informative presentation, this keynote session will focus on functional verification trends and the accelerated adoption of advanced functional verification technologies, methodologies and languages.
Learn more, then register.
Tuesday & Wednesday (February 26th & 27th)
3:30pm – 6:30pm
I look forward to meet up with those who attend DVCon. You can catch me at or around the Mentor booth for the last three hours of the conference.
IEEE Std. 1800™-2012 Officially Ratified
The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard. The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.
The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification. DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard. The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics). You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.
For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance. As Stu and Tom said in their presentation, “This is BIG!” If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.
Major work was done to augment the current notion of constraints in SystemVerilog. In past versions of the standard they were known as hard constraints. What this meant was all the conditions of the constraints had to be met otherwise there would be an error. There was no built-in method to relax the need to satisfy the constraints. Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high. To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard. If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard. Stu and Tom said that “This is also a big enhancement!”
IEEE 1800™-2012 has only now been approved. The standard itself is not ready to be published yet. Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013. I will share publication information as it becomes available. And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.
While the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now. For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more. You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well. You can find more information about it on Amazon.com here.
The Story Continues…
There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead. The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.
Stay tuned! For now, I encourage you to get informed!
Ready for 100 billion “things” connected by the Internet?
The IEEE Standards Association (SA) Corporate Advisory Group (CAG) has been working to bring industry input into the standards development organization on the emerging Internet of Things (IoT) trend that will connect billions of devices with each other.
As you can imagine, the impact this will have to the service structure down to the development of connected devices will have impact on tools used to create, verify and test them from the EDA industry to the protocols that will need to be in place to facilitate this.
This past summer the oneM2M was launched to bring some groups together who were dedicated to product technical specification for the M2M Service Layer. The impact on the IEEE, that is responsible for ongoing Internet standardization, is likewise large and not totally known.
I was reminded of the IoT impact this week by ARM’s EVP, Simon Segars. His ARM Techcon keynote presentation this week. noted the IoT is a merging of our digital and physical worlds. He also said predictions are the data from smartphones is “exploding at a 100% growth rate a year for the next 4-5 years.” To make the point even more stunning, Simon shared that Facebook expects 1-2 billion pictures will be taken and uploaded to their website around Halloween 2012. The good news for those who did not have the time to make it to Santa Clara, CA USA for ARM Techcon, his presentation has been made available for viewing on YouTube. You can find it here.
The IoT conversation continues around the globe.
IEEE IoT Workshop: You are invited!
IEEE has restored service to their Internet connection at www.ieee.org. However, connection from IEEE staff locations is tentative due to the widespread devastation of Hurricane Sandy in the New Jersey USA area where they live and work. There may be delays in getting official invitations out on the IoT workshop. The IEEE workshop on Internet of Things has been put together in conjunction with several of the CAG member companies, with direct leadership from our STMicroelectonics representative and input from representatives from Broadcom, GE Medical, Ericsson, Qualcomm and others. The IEEE SA staff and IoT Workshop leadership have asked those who are connected to share workshop information. I am doing that here.
You are invited to attend and participate in the workshop. Details on the event are:
The event will feature a combination of keynote speeches, product showcase and panel sessions with the goal to:
- identify collaboration opportunities and standardization gaps related to IoT
- help industry foster the growth of IoT markets;
- leverage IEEE’s value and platform for IoT industry-wide consensus development,; and
- help industry with the creation of a vibrant IoT ecosystem.
Date: 13 November 2012
Location: Milan, Italy
- Service Provider’s View of the IoT World (SP)
- End to End Systems Security (ST)
- IEEE-SA – Perfect Platform for the New Millennia of Consensus Development
Panel Topics include:
- GW as an Enabler of the New Services in the IoT World
- Monetizing Services in the IoT World
- Security in the IoT World
- Standard, what we have and what is missing, convergence in the technology world, collaboration opportunities.
31 October 2012 4:25 p.m. PDT
Access to ieee.org has been restored. That was quick! You can now access IoT Workshop details from IEEE directly.
31 October 2012 3:00 p.m. PDT
Due to the impact of Hurricane Sandy, power to IEEE servers has been lost and backup power sources have been depleted. Access to the IEEE website for more information, registration and additional details is not available at this moment. The workshop will be held.If the servers return to the Internet, I will update this notice.And if their absence appears to be something that will last longer than another day or so, I will update this blog with alternate contact information for those who would like more detailed information on how to register and where to go to attend the event.
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards”
The EDA industry has seen changes to the international standards paradigm the past few decades. When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version. In addition to anchoring the standard at the IEEE, collaboration with the IEC for international standardization and recognition with the one-country, one-vote process set the stage for international approval of VHDL.
In the early days of Verilog, I encouraged similar support for that IEEE standard. But its support was not immediate and to some may have failed to track the pace of support by industry. Indeed, with Accellera developing SystemVerilog, later to become an IEEE standard and IEC standard, what was missing was the close link between a global industrial community and the international setting in which the standard was developed and deployed.
In the case of SystemVerilog, global markets drove the international deployment of the standard without respect to its formal status. Indeed, on what was called the “birthday” of SystemVerilog in Japan, the day it was approved as an official IEEE standard, the Japanese National Committee on standards hosted an open celebration that I was invited to attend. There was no waiting on their part the formal status. The interdependencies of global design, global commerce and global partnerships have driven all of us to adapt the standards development process for EDA.
You can learn more about the supporters of OpenStand, their guiding principles and how you can give your input, comments and feedback by visiting their website at http://open-stand.org. And if you agree, you can even “stand” with them; with me; with us.
But in short, OpenStand promotes a standards development model that demands:
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- May 2013 (4)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)