Posts Tagged ‘OVM’
Coverage Cookbook Debuts
Verification Academy Adds Major New Technical Resource
The Verification Academy adds another major methodology cookbook to focus on effective coverage adoption. The Coverage Cookbook describes the different types of coverage that are available to track your verification process progress, how to create a functional coverage model from a specification, and provides examples to implement functional coverage for different types of designs.
Verification Academy “full access” members have access to the free Coverage Cookbook and the UVM/OVM Cookbooks as well. Are you a registered full access member? If not, register now to become a full access member. (Restrictions apply.)
Coverage is not a new topic. It was one of major additions to the SystemVerilog (IEEE Std. 1800™-2009) standard. But the SystemVerilog functional coverage extensions were left to the verification engineer to use in such as way to return meaningful measurements of how much of the design specification was being tested. The Universal Verification Methodology (UVM) offers greater structure for coverage over SystemVerilog, but it too, is still only a piece of the puzzle.
As verification teams have come to generate greater amounts of information from use of SystemVerilog, UVM and other verification tools, the data from the verification runs needs to be easily used to drive coverage closure. Within the Mentor Graphics Questa verification platform, this resulted in the development of the Unified Coverage Database (UCDB) and associated verification management and planning features.
Since verification teams use a variety of tools and technology from many sources, it was an imperative that verification information could be easily shared and combined to help drive faster coverage closure across the industry. This is why Mentor Graphics donated its UCDB API to Accellera where it became the Unified Coverage Interoperability Standard (UCIS).
It would be great to think that we are done; but we’re not. Tools and data are just two dimensions of the three dimensions to any IC design project. A comprehensive approach to verification management that handles all of this adds the third dimension. The Mentor Graphics Questa Verification Management features handle all this.
Now the question is how to best adopt and use all the capabilities at hand from the standards to the verification technology at your finger tips.
The Verification Academy Coverage Cookbook is one of the important tools you now have to help pull all the information into a single place where you can learn the theory and put that theory into practice. The Coverage Cookbook is much like the OVM/UVM Cookbooks in that it is web friendly, while supporting the ability for you to generate a PDF file of the whole document in case you want to have a printed copy or have it available for offline reference.
The Theory section covers:
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The Practice section shows three examples you can use today:
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The Coverage Cookbook is a live document. You can expect continued extensions and contributions to enhance it. As Harry Foster, Mentor Graphics’ Chief Scientist Verification put it, “Methodology is the bridge between tools and technologies, which creates a productive, predictable, and repeatable solution.” We should expect that our collective use of this technology will help hone the methodology which is the heart of the Coverage Cookbook. And with this use, we should expect the Coverage Cookbook to evolve as we achieve greater verification productivity.
Let us know what you think about the Coverage Cookbook and what we might be able to do to improve it. In the meantime, Happy Coverage Closing!
Tags: accellera, Coverage, Coverage Closure, Coverage Cookbook, functional coverage, Harry Foster, IEEE 1800, OVM, SystemVerilog, UCDB, UCIS, UVM, Verification Academy
Introducing “Verification Academy 2.0”
A new style takes center stage
It was Fashion Week in Portland, Oregon in early October. And while the thought of Portland and fashion might not be believable to many in the world, especially those who look to the design houses of Paris or Milan, it was. What struck me was the blend of fashion with high tech this year. Intel took the opportunity to roll out its fashion inspired campaign (dressing room mirror sized tablets) and Mitsubishi used it to launch its new electric vehicle (named MiEV in case you did not know). Certainly it was more than just your run-of-the-mill runway show. But that was not the only thing “getting some style” here in the Portland area.
The Verification Academy team at Mentor Graphics has been working hard as well to restyle the Verification Academy website, modernize it and make content easily accessible. It made its debut in late September, a few weeks before the Portland Fashion Show. While these two things are a coincidence, the focus on a refreshed style should not to be totally unexpected.
Some of the changes just had to be made given the success of the Verification Academy. When it started a few years back, Harry Foster (the face in the picture of the Verification Academy website above) knew the adoption of advanced technology was hampered by unequal and slow distribution of knowledge. Part of the Verification Academy’s thrust was to bring information about advanced verification topics to the whole world in a format that could be easily used. The content comes from respected verification subject matter experts and the first “runaway success” was the Open Verification Methodology (OVM) training by John Aynsley from Doulos for the “basic” module and Tom Fitzpatrick from Mentor Graphics for the “advanced” module. The Universal Verification Methodology (UVM) course, likewise, has also joined the ranks of the highly watched. Updates to the Academy improve the services to deliver video.
We have moved to the most current web video protocols that allow modern browsers and mobile devices to easily access course content. You can watch courses on the “smaller” smartphone screens to the largest of TV displays with SD and HD video to support your viewing preferences. Since content is delivered in native web technologies, users do not have to depend on Flash or other plugins.
We have also migrated the Academy to the leading open source content management system and adopted the use SSL throughout the Verification Academy to make it more secure.
When we first started the Verification Academy, we did not know how large the community would grow nor could we predict the demands the community would place on the resources to support it. Today, there are almost 12.5K users making it the largest single site to support the verification professional. The changes we have made to the internals of the site show a speed improvement of over 400% by exploiting a commercial content delivery network to handle large media.
And for many members, where English is a second language, the video captions, when offered, are in plain text. Registered users can click on the picture to the right to see the UVM Introduction and enable closed caption to see how the text appears right below the video. (Or, from reading the text below video in the picture to the right, you can see John is introducing himself at the moment of this screen capture.)
We have also made big improvements to searches. The searching facility now scans across all content at once, from the forums, to the UVM/OVM Cookbook and presents the information to you in an improved way to allow you to filter the results to focus on just that you want to know.
Want to experience the new Verification Academy 2.0 style? Click here to go to the Verification Academy to see these changes and discover these and other changes yourself. Share your comments with me on what you think. Have we made it better for you? And if not, what more can we do to improve your experience even more?
Tags: OVM, UVM, UVM Cookbook, Verification, Verification Academy
OVM Gets Connected
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
OVM Thrives
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
Download
The UVM Connect 2.2 kit supports multilingual use of OVM and can be found at the Verification Academy and the Accellera UVM World contributions download site.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Tags: 1666, 1800, accellera, IEEE, Multilanguage OVM, Multilanguage UVM, OVM, Standards, systemc, SystemVerilog, UVM, UVM Connect
Verification Academy: Up Close & Personal
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design. The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well. A whole host of educational modules and seminars can also be found there too.
If you know about the Verification Academy, you know all about the content mentioned above and that there is much more to be found there. For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum. (Flash is required to watch Harry discuss Verification Academy with Luke.)
The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends. Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations. While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations. Verification Academy “Total Access” members now have access to many of the presentations.
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ARM |
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Doulos |
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Thales Alenia Space |
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Test & Verification Solutions |
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Willamette HDL |
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Sunburst Design |
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Mentor Graphics |
Total Access members can also download all the presentations in a .zip file. Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.
Tags: ABV, ACE, ams, ARM, Assertion-Based Verification, Coverage Closure, dac, Doulos, formal, IEEE, iTBA, Low Power, OVM, SystemVerilog, Tech Design Forum, Thales, upf, UVM, UVM Express, Verification Academy, Verification Trends
Tornado Alert!!!
Is my car trying to tell me something?
This past Friday was the beginning of a two day internal functional verification meeting at Mentor Graphics corporate headquarters on Intelligent Testbench Automation (iTBA). (Mentor’s iTBA product, Questa inFact is hot and getting hotter.) After getting to my car to return home at the end of the first day, I was thinking that the large interest in this technology – demonstrated by a standing room only training event – has got to be a tipping point indication for iTBA.
I turned my car on. (Actually, I “pushed” it on as there is no place to put a key to turn anymore.)
Moments after starting my car a winter storm alert interrupted the music on the radio and displayed two notices. One I am familiar with when the temperature falls and snow begins to collect on the mountain passes. I’m not going to drive in the direction of the snow, so no problem. The other alert was of grave concern. It was a tornado watch. And the tornado watch was not off in some other direction many miles away, it was “0 miles” from me. I looked up, I scanned the horizon and dark black was in one direction and sun in the other. I changed the radio channel to a local AM evening drive station, but no mention of a tornado watch. I headed in the direction of the sun. It seemed the safest direction to head. But before I did, I snapped a quick picture as proof I actually read “Tornado Watch” on the car’s navigation screen.
iTBA to the Rescue?
I returned to ponder if functional verification has just gotten too big for current techniques that iTBA is going from a nice to have, to a must have.
Several years back it was popular to brag about the compute farms & ranches one had. With 5,000 machines here and another 5,000 machines there it seemed a sane demonstration of one’s design and verification prowess. But this gave way to 50,000 multicore machines and who is talking about this with pride? All talk is out of necessity. And what about the next step? Who has 500,000 or 5,000,000 on the drawing board or in their data centers? Looking around, it seems very few admit to more than 100,000 and even fewer have more than 500,000.
Verification may be in crisis, as many will say, but it you hold verification technology constant, it is not in crisis, is on a collision coarse with disaster. Addressing this crisis has been the theme of many of Mentor Graphics CEO Wally Rhines’ keynotes at DVCon. His 2011 keynote was taken to heart by many who attended. The need to improve by a several orders of magnitude the “Velocity of Verification” has been followed by several examples over the year.
One example was shared several months after DVCon when Mentor Graphics and TSMC announced we had partnered to validate advanced functional verification technology. While not all test results at TSMC or our common customer, AppliedMicro, were revealed, one of the slower tests demonstrated the value of iTBA to shorten time-to-coverage by over 100x. Even days after that announcement we disclosed Mentor’s Veloce emulation platform offered 400x OVM/UVM driven verification improvement.
100x and 400x seem like a large numbers, but it appears even bigger when you put it into the context of the time it was measured. With current constrained random techniques, a project that takes 6 weeks of simulator run time to reach 100% closure can reach it in about 10 hours with Questa inFact or about 2.5 hours with Veloce. Instead of using complex scripts to peek in on a simulation run over the course of a month and a half, a verification team could actually leave work for the day, return the next morning and have a full, complete and exhaustive verification run. And when even faster turnaround time is needed, emulation returns results during the work day.
SoC Verification: A Balance of simulation, iTBA & emulation
Wally’s DVCon 2011 keynote referenced 8 customer results coming from Mentor’s Questa inFact tool. Many more have discovered what this can do for them as well. And with each success, come the requests from more to see what it can do for them.
But changing the “Velocity of SoC Verification” has not rested on one technique alone. Stop by the Mentor Graphics DVCon booth and we can share with you the advances we have made to address system-level verification since last year.
Crossing The Chasm
Which brings me to the point of the “Tornado Watch.” As I pondered the iTBA tipping point, about “how little things can make big differences” as can be found in Malcolm Gladwell’s book, my car must have been channeling Geoffrey Moore of “Crossing The Chasm” fame instead. For that reason it must have issued the Tornado Watch. Could it be that iTBA is set to cross the chasm from early adopters to the early majority?
And thankfully, I don’t think my car is programmed to issue tipping point warnings, nor do I want to see if it can.
In the end, it will be with the benefit of hindsight that let’s us know if we are crossing the chasm into the tornado or not now or soon. But for Mentor’s part, full and advanced support of iTBA technology with Questa inFact is ready now, and we are set to cross the chasm into the tornado. My colleague, Mark Olen, blogs about iTBA here. If you have not had a chance yet to read his blog on iTBA delivering 10x to 100x faster functional verification, it is worth the time to do so. You can look for him to give frequent updates on iTBA and comment on the positive impact is has on SoC design and verification teams in the months ahead.
I look forward to seeing you at DVCon.
Tags: Crossing the Chasam, inFact, Intelligent Testbench Automation, iTBA, OVM, questa, SoC, Tipping Point, UVM, Veloce
UVM™ at DVCon 2012
“Ready, Set, Deploy”
The last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification Methodology (UVM) is ready for design and verification teams to adopt. This theme started with a whitepaper from Accellera I authored with two of my peers, Stan Krolikoski from Cadence Design Systems and Yatin Trivedi from Synopsys. A day long UVM tutorial will be featured during “Accellera Day” at DVCon with the same ready, set, deploy theme. The UVM tutorial is timely as I have seen UVM gain traction as OVM users transition at the end of their projects and those who have yet to adopt a standardized methodology have likewise begun their adoption.
The UVM tutorial starts with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. A section on the UVM register package will show how to create and manage stimulus and checking at the register level. Several expert users will show how this fits together in a complex SoC verification environment and relate lessons learned in preparing the transition to UVM, architecting reusable testbenches, debut techniques and use of the TLM 2.0 in real verification environment.
The tutorial will be presented by expert verification methodology architects and engineers as shown below:
| Speakers: | Tom Fitzpatrick | Mentor Graphics Corp. |
| Kathleen Meade | Cadence Design Systems, Inc. | |
| Adiel Khan | Synopsys, Inc. | |
| Stephen D’Onofrio | Paradigm Works, Inc. | |
| John Aynsley | Doulos | |
| Mark Strickland | Cisco Systems, Inc. | |
| Vanessa Cooper | Verilab, Inc. | |
| John Fowler | Advanced Micro Devices, Inc. | |
| Peter J. D’Antonio | The MITRE Corp. | |
| Justin Refice | Advanced Micro Devices, Inc. |
Conference attendees may choose this tutorial or if you wish to attend the tutorial only, DVCon charges a modest fee ($75.00). You can register here for the day long UVM tutorial.
More UVM News
With 33 exhibitors at DVCon and the heavy functional verification content, what other venue could deliver the potential of breaking UVM news? I invite you to stop by the Mentor Graphics booth were we can share with you the latest in support of UVM. You will find us at booth 801.
I look forward to seeing everyone at DVCon!
Tags: accellera, OVM, Standards, UVM, Verification
TLM Becomes an IEEE Standard
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.
For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI). OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard. TLM is important to SystemC, but it has also been leveraged outside of it.
We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog. This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).
If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity. The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first. This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.
As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together. And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together. I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.
For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting. I will share with you when it is ready to use as well as how to get it and where to find it.
Tags: 1666, 1800, accellera, IEEE-SA, OSCI, OVM, Standards, systemc, SystemVerilog, TLM, TLM 1.0, TLM 2.0, UVM, Verification Academy
VHS or Betamax?
Legacy’s Luster Lost
As a follow-on to my last blog, where I shared information about Harry Foster speaking live about the research he has been reporting on the last year and where I noted legacy might hold some back, I was going to finish on some of the work we have done at Mentor Graphics to move forward while trying to keep some of those held back by legacy, whole.
Buy why this title? For some, there may be no recollection of what VHS or Betamax are. And if I were to say it is a format used to tape record video, that still might not help given DVD, MP4, etc. If I were to even say there was once a format war over these two, one could easily shrug one’s shoulder and proclaim they both lost. And that is true.
What do we record on today? Precisely, the answer is neither of these for all but an obscure few. But it was towards the end of this format war I left one area to move to another. VHS had all but become the format of that area for video rentals, while the area I moved to was evenly split between the two formats. I had selected Betamax. I can go into great detail to explain the technical advantages of the format. But those words are all lost on the market forces that ushered in VHS. And thanks to continued innovation, these legacy formats have lost their luster. We have all moved on.
Be Kind – Rewind
As SystemVerilog has become the dominant language standard for verification, the methodology work aggregated in Accellera’s Verification IP Technical Subcommittee (VIP-TSC) where it built the Universal Verification Methodology (UVM). While UVM leverages SystemVerilog, the market’s move from legacy formats has left some who still use those formats to ask if the industry can be “kind, and rewind” – to still support them.
While Accellera’s UVM has been open to bring the dogma of all market participants together to create a single coherent standard, that has not met with total satisfaction of legacy users. What now appears to be more liked by them is a wholesale translation of UVM in SystemVerilog to legacy languages. What’s the value in that? Does one gain greater productivity from this?
Accellera hopes to bridge this divide with a return to its first phase of verification IP interoperability work to suggest additional ways to interoperate. For up-to-the-minute information on this, I suggest you get involved with the group. Full information about the group is only available in the membership area – and everyone is invited to be an observing member. But we should expect Accellera to talk about better bridges to those formats important to those sitting around the standardization table.
Fast Forward
But I still come back to the question about what’s the value in this. It is time to move forward or be stuck in the past? The format is not the value; the algorithms to do better and faster verification are. To that end, for the users of the e language, Mentor Graphics has extended its Intelligent Testbench Automation (iTBA) technology to work in an e environment.
Many UVM (and OVM) users have found they have been able to achieve their coverage goals 10x to 100x faster than before with this innovative technology. And it is now readily available to the 10-15% who still use e. For more information about leveraging iTBA, you can visit the Verification Academy where one of the new modules that was added in the iTBA section, titled Integrating iTBA into an ‘e’ Environment, is ready for viewing and explains how this is done. [Note: Registration is required to view the module and certain restrictions apply.] This module describes integrating Intelligent Testbench Automation into an e environment, re-using existing eVCs, and achieving functional coverage >10X faster.
While legacy language users may fret about their preferred language, the market has already spoken. Maybe it is time to explore how advanced verification algorithms can be back ported to support legacy to ease the transition. After all, its not the language, it’s the algorithms. Go online and see what the advance algorithms can offer you. Or, join us next week in San Jose, CA at the Verification Seminar.
Tags: accellera, betamax, e, OVM, Standards, SystemVerilog, UVM, Verification, vhs, vip-tsc
Verification Issues Take Center Stage
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.
To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:
Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Website: http://www.mentor.com/events/verification/
Cost: Free; registration restrictions apply
Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Website: http://verificationfutures2011.eventbrite.com/
Cost: Free
Legacy set for replacement?
Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.
This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.
When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.
With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.
While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.
Why bring all this up?
We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.
In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.
In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?
I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.
Tags: 1800, accellera, IEEE, OVM, Standards, SystemVerilog, UVM, vip-tsc, vmm
Going from “Standards Development” to “Standards Practice”
Historical Perspective
In my early days of standards development, I was intrigued how a standard went from the development phase to use phase. New standards were heralded with great fanfare but were also followed very quickly with books and other material to allow the “mere mortal” to understand what the IEEE standards prose meant and how best to use it. Everyone had their favorite VHDL book and I think I have them all!
What was clear to me was the IEEE standard was not sufficient to practice or understand the standard. After all, examples were few and far between in the standard. And even if there were examples in the standard, you were reminded that they are not part of the official standard – or in standards-speak – they are nonnormative.
User groups were popular too and continue to be today. VHDL International (now Accellera) had this notion of local VHDL user group chapters. When it came time to drive adoption of the VHDL gate-level library standard (known as VITAL), I attended several user group meetings to share details on how to use the new standard. I even solicited the support of a VHDL notable to put together a seminar series that would help ASIC library makers build their libraries. We took the seminar around the world and met with all the top ASIC suppliers. We even took our product that implemented the standard to the Cloud – while we did not call it the Cloud at the time. We had a model validation service in the early days of the internet that could be used to run training examples to validate ones own understanding or even test models and concepts to see if they would work. Free evaluation software was still a thing of the future then. As one byproduct of that work, we did have one competitor inundate us with the 1000’s of VHDL tests. We did throttle back their access to be fair to the others. But at that time, we left few ideas unexplored on how to drive global use and adoption of that standard.
Lessons Learned
What I understood was crossing the chasm from standards development to practicing the standard meant we had to build the knowledge, expertise and confidence in the user community to help them accept the standard and adopt it. I also learned that the standards developing organizations were not the best equipped to help practice the standard. The simple reason for this is the SDO is in place to bring together competitors to collaborate on the development of the standard but not foster competition on algorithms to best use the standard. This is perhaps better said by Synopsys’ Karen Bartleson in her “First Commandment for Effective Standards: Cooperate on Standards; Compete on Tools.”
Today’s Challenges with UVM & OVM
We are at that chasm with Open Verification Methodology (OVM) and the Universal Verification Methodology (UVM) today. While some may suggest OVM & UVM sit in a homogenous world where it works the same everywhere, the effective practice of the standards is anything but that. There are competitive options for users to explore and they are not ideas best promoted by a standards group. Mentor’s Mark Olen points out the value of an advanced method to generate stimulus rather than relying on the methods built into OVM & UVM in his recent blog post. Mark shows how a user gains 10x-100x in efficiency all the while doing this from within their OVM or UVM testbench.
Mentor has thought long and hard about how to best get this information to users and how to help them practice OVM and UVM better than they can if they only had access to the lowest common denominator of information. We first did a blind survey to see what methodology the design and verification community was using now and what they were going to use 12 months from now to validate our focus on OVM and UVM. Mentor’s Harry Foster has shared a lot of detailed information on this already. If you have not read his blog postings on this yet, you should start with his prologue that outlines the survey.
Survey Says:
The survey clearly showed that UVM was in its ascendency and OVM was going to maintain strong and growing domination into 2012. Other survey results also clearly point out that SystemVerilog is the language of choice. While the survey shows what the user is doing, the standards developers were all collaborating on UVM and giving little time to OVM.
A Little Attention Goes a Long Way
While users were focused on continued use of OVM and planning for major move to UVM in 2012, the community developing standards had all but shifted to UVM, seemingly abandoning OVM. OVM was in need of care and attention given its dominant position in planned and future use.
Mentor stepped into the breach and has brought OVM into a strong, user-centric home that preserves the OVM World openness and augments it with several levels of additional user benefits in the Verification Academy. It also joins OVM and UVM in a single location that would not be appropriate in a standards body. After all, UVM is the standard from Accellera, not OVM. The Verification Academy also opens the cross pollination of ideas between the OVM and UVM users so one group can learn from another. We also brought the SystemVerilog User Group (SVUG) into the forum as well since OVM and UVM are based on the SystemVerilog language.
As we brought all these groups together, we did get many questions about Verification Academy Access Levels. First off, we dropped the OVM World requirement to register to download OVM. UVM and VMM were allowing anonymous downloads, so we made it the same for OVM. Of the 15,000+ OVM World registrants, most registered to download OVM. Just as OVM can now be downloaded without registration, the forums can be accessed in read-only mode without registration as well.
For those who used their OVM World registration to post on the forum, we moved them to “Forum Only Access” members so they could continue their posting privileges. The highest level of membership is “Academy Total Access.” Membership at this level is restricted to those who give a valid business profile. It enables access to training material, courses and lessons to help build SystemVerilog, OVM and UVM skills. It also allows users to gain knowledge about the advance algorithms that can help them get the 10x-100x or more out of OVM and UVM over conventional use. Below is a table of Verification Academy membership levels and privileges:
| Level | Privileges |
| Observer | Read-Only Forum Access. Free OVM/UVM kit download. No registration required. |
| Forum Only Access | Post to Forum and contributions area. Registration with any credentials required. |
| Academy Total Access | Total access. All academy areas open for free use. Registration with valid business profile. |
The response to this has been outstanding. While we strongly urge those who wish to develop the UVM standard to visit www.accellera.org and its www.uvmworld.org site to monitor that work, Verification Academy seems to have a much larger community of users with which to interact. And we will keep the Verification Academy current with the most recent versions of OVM and UVM. As of late July 2011 we recorded the following statistics.
| Forum | Members |
| Verification Academy Forum | 5,476 |
| UVM World Forum | 685 |
| VMM Central Forum | 696 |
We look forward to continue to develop the site and add to the richness of its content and continue to improve your experience with it. Your comments on how we can improve it are always welcome.
Tags: accellera, IEEE, OVM, OVM World, Standards, UVM, UVM World, vhdl, VITAL, vmm
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
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