Posts Tagged ‘OSCI’
IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support
A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE. The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved. While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.
For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI). OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard. TLM is important to SystemC, but it has also been leveraged outside of it.
We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog. This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).
If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity. The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first. This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.
As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together. And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together. I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.
For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting. I will share with you when it is ready to use as well as how to get it and where to find it.
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs. At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit? Where are they going?,” technical members of the two communities gathered to ponder answers to those questions. At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.
Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community. A lot has transpired since then. Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively. And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.
In this evolution, it became clear to me that each organization was “completing” the other. OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™). As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.
In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.
What do you think about the unification?
The standards developing organizations defining and updating front-end EDA standards will be at DAC in force. And from the looks of if, they are getting an early start to DAC with updates on IEEE, Accellera and OSCI standards at Sunday workshops. The Sunday workshops may be of particular interest to verification engineers interested in UVM and systems designers interested in SystemC AMS.
Following the workshops, there will be a half-day meeting of the North American SystemC Users Group on Monday where users will share their SystemC experiences. The following morning, Accellera will host its annual DAC breakfast where the UVM users will meet to share their experiences. A lively conversation is expected.
Sunday – June 5, 2011
Time: 10:00 AM — 1:00 PM
Location: San Diego Convention Center Room 33A
Summary: The Accellera Verification IP Technical Subcommittee (VIP-TSC), building on over two years of work by verification experts from around the world, released Universal Verification Methodology (UVM) in February 2011. This workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
GET MORE DETAILS
Registration: This is an official DAC sponsored event and DAC registration required.
Time: 10:00 AM — 6:00 PM
Location: San Diego Convention Center Room 33B
Summary: Today’s embedded systems interact more and more tightly with the analog physical environment; where digital HW/SW subsystems become functionally interwoven with analog/mixed-signal (AMS) blocks such as RF interfaces, power electronics, or sensors and actuators. Examples are software defined radios, sensor networks, automotive applications, or systems for image sensing. This requires new means to model and simulate the interaction between AMS subsystems and HW/SW subsystems at functional and architecture levels. Especially for this purpose, the SystemC language standard has been extended with powerful AMS capabilities to tackle the challenges in heterogeneous electronic system-level (ESL) design. You will get a good working knowledge of SystemC AMS by attending the workshop.
GET MORE DETAILS
Registration: This is an official DAC sponsored event and DAC registration required.
Monday – June 6, 2011
North American SystemC Users Group Meeting
Time: 8:30 AM – 12:00 PM
Location: OMNI Hotel
Room Salon AB
675 Laurel Street
San Diego, CA 92101
Summary: The North American SystemC Users Group explores the newest advancements in sustainable and flexible solutions for system-level design using SystemC.
GET MORE DETAILS
Registration: This event is free and open to all registered DAC attendees. Click here to reserve your seat
Tuesday – June 7, 2011
Time: 7:00 AM – 8:30 AM
Location: San Diego Convention Center Room 25AB
Summary: With the introduction of Accellera’s Universal Verification Methodology (UVM) user interest and adoption has been rapidly growing. You are invited to join us and share the experience with fellow users. During the breakfast, you will hear from real users who have migrated to, and/or applied, the UVM for the first time. Accellera Verification IP Technical Subcommittee (VIP-TSC) participants will provide their insights on UVM. We invite you to take part in the open discussion to foster greater adoption of this important verification standard.
GET MORE DETAILS
Registration: This event is free open to all registered DAC attendees. Click here to reserve your seat
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state of the market for ESL design and the pending content of the SystemC standard that is current in final ballot by the IEEE.
To view the video presentations, you will need to register with the Open SystemC Initiative.
Abstract: SoCs are becoming ubiquitous in semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.
Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
John Aynsley, Doulos Ltd., UK
The New IEEE 1666 SystemC Standard
Abstract: The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.
If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM). And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days. But you may also want to bring a colleague to attend the SystemC Day activities.
For SystemC Day at DVCon, the morning session is the North American SystemC Users Group (NASCUG) meeting that features a Keynote presentation by industry luminary Jim Hogan.
Jim’s keynote will be on “Navigating the SoC Era.” NASCUG attendance is free, but you need to register to attend.
Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.
In the afternoon, a tutorial on software-driven verification titled Software-Driven Verification Using TLM-2.0 Virtual Platforms will be presented by experts from the OSCI, Accellera and the user community that are using standards-based methodologies in production today. The afternoon tutorial requires registration at the DVCon website. The tutorial is free for conference attendees. A small fee is charged for those who wish to attend this tutorial only. Is software-driven verification in your future? Chances are highly likely it is and I suggest you look at attending this event.
I’ll see you there!
You Are Invited – Register Now!
(seating is limited)
Sunday, June 13
2:30pm – 6:00pm
Anaheim Hilton, California Ballroom A
On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.
As a global sponsor of OSCI events, Mentor encourages the SystemC community to meet at this event to learn more about SystemC advances and applications.
Technical presentations on architectural modeling, transaction-level modeling and analog/mixed-signal design using SystemC™ will be featured. You will be able to interact with colleagues and industry experts, and find out first-hand how system-level design with SystemC has become a nuts-and-bolts part of the designer’s toolbox.
|2:30pm – 3:00pm||Registration|
|3:00pm – 3:10pm||Welcome & Agenda|
|3:10pm – 3:30pm||OSCI and Technical Working Group Update
Eric Lish, OSCI Chairman
|3:30pm – 5:50pm||Technical Presentations:|
|5:50pm – 6:00pm||Meeting Close and Prize Drawing|
6:00pm – 7:30pm
Anaheim Hilton, Pacific Ballroom
The DAC Executive Committee and the EDA Consortium invite the NASCUG XIII participants to attend their annual DAC Kick-Off Reception at this year’s conference in Anaheim, California. The reception begins just as the user group meeting concludes. Both events are in the Anaheim Hilton and located close to each other. Register Now to attend the Sunday reception.
Noted EDA analyst and guru Gary Smith delivered keynote address: “ESL: Where We Are and Where We’re Going”
OSCI sponsored the first annual SystemC Day at DVCon 2010. The presentations were video recorded and are available for free for those who missed DVCon or who may wish to see them again. Gary Smith’s presentation (registration required) and OSCI chair, Eric Lish’s OSCI Update lead the video set from SystemC Day.
The 12th North American SystemC Users Group (NASCUG) meeting was part of SystemC Day at DVCon and featured technical presentations on architectural modeling, verification, and analog/mixed-signal design using SystemC.
OSCI ON YOUTUBE: More videos of users and their perspectives on SystemC events and activities can be found via the OSCI channel on YouTube: http://www.youtube.com/officialsystemc
Click here for completing listing of the following technical presentations.
|The Metaport: A Technique for Managing Code Complexity
Jack Donovan, HighIP Design, Texas, USA
The metaport is a coding style that can effectively manage code complexity for complex ESL models, especially models that are intended for high-level synthesis. This presentation will give an overview of the metaport concept and dive into the details of a possible implementation.
|OCP Socket Modeling with TLM-2.0
Hervé Alexanian, Sonics Inc., California, USA
This presentation discusses work performed by the OCP-IP Committee, specifically modeling that OCP built upon the TLM-2.0 standard.
|ADL Synthesis using ArchC
Samuel Goto, Master student at UNICAMP
The design and implementation of processors is a complex task. Architecture Description Languages (ADLs) were created to extend existing HDLs, to ease the process of developing and prototyping an architecture by providing a set of tools and algorithms to optimize and automate some of the tedious parts. While much has been done on the specification and business levels of ADLs, there is a huge gap between ADL specifications/simulators and real life processors written in RTL. This project addresses the issues of bringing an ADL description to the RTL level, and reports the development of an extension of ArchC to support this level.
|Look Ma, No Clocks! Improving Model Performance
David Black, XtremeEDA, Texas, USA
This tutorial-style presentation illustrates some techniques to avoid the inclusion of clocks in SystemC simulations and provide results of simple experiments showing the simulation performance benefits. Concepts discussed include synchronization, clock-free timers, and the effects of clocks on performance. A proposal is made for a simple SystemC class that can simplify coding when clocks are thought to be needed.
|TLM-driven Design and Verification Methodology
Brian Bailey, independent consultant
SystemC is well on the road to adoption in a number of areas within the Electronic System Level (ESL) space, but many of those are separated islands today. Virtual Prototyping has seen a huge leap forward with the standardization of TLM 2.0. SystemC is also being used successfully for high-level synthesis at the module level, but to make SystemC pervasive, there must be a link between the applications. In addition, to reap the maximum productivity gains from a migration to a higher-level of abstraction, the verification methodology must also change in significant ways. In this presentation we will explore a new TLM-driven design and verification methodology that is being developed within Cadence, critiqued by their customers and documented in a book, which will be released over a number of months as pieces of it mature.
SystemC User Group Meeting & DVCon Tutorial Featured
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to support and advance SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22.
Mentor Graphics is one of the sponsors for the event and we will share updates on products that support SystemC during the SystemC Supplier Showcase between 10:00 a.m. – 2:00 p.m. Visit us at the Showcase or at the DVCon tradeshow.
How to Register
Admission is free with advance registration to the North American SystemC Users Group Meeting (NASCUG 12) and complimentary lunch. The afternoon tutorial is part of the DVCon program and requires separate registration.
- NASCUG 12 Meeting and Lunch
Register at: www.mod-marketing.com/osci (FREE)
- DVCon Tutorial: The OSCI TLM-2.0 Standard and Synthesis Subset
Register at: www.dvcon.org/reg.html ($60 DVCon Fee)
|8:30 am – 12:00 pm||NASCUG 12 Meeting (Full agenda at www.nascug.org)|
|10:00 am – 2:00 pm||Sponsor Tabletop Exhibits|
|12:00 pm – 1:30 pm||OSCI Sponsored Lunch|
|1:30 pm – 5:00 pm||DVCon Tutorial: “The OSCI TLM-2.0 Standard and Synthesis Subset
|5:00 pm||DVCon Hosted Reception|
No, this is not an early Olympics update.
But none the less, these three organizations have all earned 10’s. Thursday, 28 January 2010 at EDSFair, JEITA EDA-TC the Japan Electronics and Information Technology Industries Association’s standards group, celebrated their 10-year anniversary. The JEITA EDA-TC collaborates with the IEEE, Accellera and the Open SystemC Initiative. During the EDSFair opening remarks, JEITA announced their 10-year anniversary and recognized SystemC’s and Accellera’s 10-year anniversaries as well. Three organizations celebrated 10 years of bringing standards to the electronics industry.
Accellera and OSCI were invited to offer a welcome speech of congratulations to JEITA. As vice-chair of Accellera, I spoke on behalf of Accellera to a standing-room only crowd. Dr. Stan Krolikoski, treasurer of OSCI spoke on behalf of OSCI.
The engineers assembled heard from JEITA speakers under the theme that each of them is the best engineer in their company. Accellera and OSCI both reinforced their commitments to evolve and advance design automation standards to forge productivity and interoperability to help all the “number one” engineers to continue to be the “best engineers” they can be.
The following day, at the joint IEEE Design Automation Standards Committee (DASC) and JEITA EDA-TC standards meeting, Shigemi Saito (from Sony) and EDSF2010 executive committee chair and past chair of the EDA-TC standards activities announced his retirement from Sony effective at the end of the day. After 31 years with Sony, Saito-san will cast his sail and set a new course. He has been a friend of EDA standards for many years. And I thank him for this friendship and his help two years ago when the IEEE Standards Association held an educational seminar at “Sony Square” in Tokyo. The seminar opened with a welcome keynote from Sony’s Keiji Kimura, EVP, Corporate Executive Officer, Officer in Charge of Technology Strategies, Intellectual Property and Electronics Business Strategies. Kimura-san cited the importance of EDA standards as they underpin all electronic design and called out by name many that are used by Sony. I know Saito-san was instrumental to bring out the importance of EDA standards for Kimura-san to share. Saito-san, I wish you a happy retirement!
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
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- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
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- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
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- Part 3: The 2010 Wilson Research Group Functional Verification Study
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
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- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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