Posts Tagged ‘nascug’
If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM). And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days. But you may also want to bring a colleague to attend the SystemC Day activities.
For SystemC Day at DVCon, the morning session is the North American SystemC Users Group (NASCUG) meeting that features a Keynote presentation by industry luminary Jim Hogan.
Jim’s keynote will be on “Navigating the SoC Era.” NASCUG attendance is free, but you need to register to attend.
Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.
In the afternoon, a tutorial on software-driven verification titled Software-Driven Verification Using TLM-2.0 Virtual Platforms will be presented by experts from the OSCI, Accellera and the user community that are using standards-based methodologies in production today. The afternoon tutorial requires registration at the DVCon website. The tutorial is free for conference attendees. A small fee is charged for those who wish to attend this tutorial only. Is software-driven verification in your future? Chances are highly likely it is and I suggest you look at attending this event.
I’ll see you there!
You Are Invited – Register Now!
(seating is limited)
Sunday, June 13
2:30pm – 6:00pm
Anaheim Hilton, California Ballroom A
On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.
As a global sponsor of OSCI events, Mentor encourages the SystemC community to meet at this event to learn more about SystemC advances and applications.
Technical presentations on architectural modeling, transaction-level modeling and analog/mixed-signal design using SystemC™ will be featured. You will be able to interact with colleagues and industry experts, and find out first-hand how system-level design with SystemC has become a nuts-and-bolts part of the designer’s toolbox.
|2:30pm – 3:00pm||Registration|
|3:00pm – 3:10pm||Welcome & Agenda|
|3:10pm – 3:30pm||OSCI and Technical Working Group Update
Eric Lish, OSCI Chairman
|3:30pm – 5:50pm||Technical Presentations:|
|5:50pm – 6:00pm||Meeting Close and Prize Drawing|
6:00pm – 7:30pm
Anaheim Hilton, Pacific Ballroom
The DAC Executive Committee and the EDA Consortium invite the NASCUG XIII participants to attend their annual DAC Kick-Off Reception at this year’s conference in Anaheim, California. The reception begins just as the user group meeting concludes. Both events are in the Anaheim Hilton and located close to each other. Register Now to attend the Sunday reception.
SystemC User Group Meeting & DVCon Tutorial Featured
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to support and advance SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22.
Mentor Graphics is one of the sponsors for the event and we will share updates on products that support SystemC during the SystemC Supplier Showcase between 10:00 a.m. – 2:00 p.m. Visit us at the Showcase or at the DVCon tradeshow.
How to Register
Admission is free with advance registration to the North American SystemC Users Group Meeting (NASCUG 12) and complimentary lunch. The afternoon tutorial is part of the DVCon program and requires separate registration.
- NASCUG 12 Meeting and Lunch
Register at: www.mod-marketing.com/osci (FREE)
- DVCon Tutorial: The OSCI TLM-2.0 Standard and Synthesis Subset
Register at: www.dvcon.org/reg.html ($60 DVCon Fee)
|8:30 am – 12:00 pm||NASCUG 12 Meeting (Full agenda at www.nascug.org)|
|10:00 am – 2:00 pm||Sponsor Tabletop Exhibits|
|12:00 pm – 1:30 pm||OSCI Sponsored Lunch|
|1:30 pm – 5:00 pm||DVCon Tutorial: “The OSCI TLM-2.0 Standard and Synthesis Subset
|5:00 pm||DVCon Hosted Reception|
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
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- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
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- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
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- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
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- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
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- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
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- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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