Posts Tagged ‘Low Power’

10 August, 2015

ASIC/IC Power Trends

This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group Functional Verification Study (click here).  In my previous blog (click here), I presented our study findings on various verification language and library adoption trends. In this blog, I focus on power trends.

Today, we see that about 73 percent of design projects actively manage power with a wide variety of techniques, ranging from simple clock-gating, to complex hypervisor/OS-controlled power management schemes. What is interesting from our 2014 study is that the data indicates that there has been a 19% increase in the last two years in the designs that actively manage power (see Figure 1).

2014-WRG-BLOG-ASIC-11-1

Figure 1. ASIC/IC projects working on designs that actively manage power

Figure 2 shows the various aspects of power-management that design projects must verify (for those 73 percent of design projects that actively manage power). The data from our study suggest that many projects are moving to more complex power-management schemes that involve software control. This adds a new layer of complexity to a project’s verification challenge, since these more complex power management schedules often require emulation to fully verify.

2014-WRG-BLOG-ASIC-11-2

Figure 2. Aspects of power-managed design that are verified

Since the power intent cannot be directly described in an RTL model, alternative supporting notations have recently emerged to capture the power intent. In the 2014 study, we wanted to get a sense of where the industry stands in adopting these various notations. For projects that actively manage power, Figure 3 shows the various standards used to describe power intent that have been adopted. Some projects are actively using multiple standards (such as different versions of UPF or a combination of CPF and UPF). That’s why the adoption results do not sum to 100 percent.

2014-WRG-BLOG-ASIC-11-3

Figure 3. Notation used to describe power intent

In an earlier blog in this series, I provided data that suggest a significant amount of effort is being applied to ASIC/IC functional verification. An important question the various studies have tried to answer is whether this increasing effort is paying off. In my next blog (click here), I present verification results findings in terms of schedules, number of required spins, and classification of functional bugs.

Quick links to the 2014 Wilson Research Group Study results

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25 June, 2015

There are intrinsic limitations in the current approach for estimating dynamic power consumption. Briefly, the approach consists of a file-based flow that evolves through two steps. First, a simulator or emulator tracks the switching activity either cumulatively for the entire run in a switching activity interchange format (SAIF) file, or on a cycle-by-cycle basis for each signal in a signal database file such as FSDB or VCD. Then, a power estimation tool fed by as SAIF file calculates the average power consumption of a whole circuit, or an FSDB file computes the peak power in time and space of the design.

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Figure 1: Conventional power analysis is grounded in the two-step, file-based approach.

The method may be acceptable when the design-under-test (DUT) is relatively small, in a ball-park of a few million gates or less, and the analysis is performed within a limited time window of up to a million or so clock cycles. Such time windows are typical when the DUT is tested with adaptive functional testbenches.

When applied to modern, large SoC designs of tens of hundreds or millions of gates executing embedded software, such as booting an operating system and running application programs that require billions of cycles, three problems defeat the conventional approach:

  1. The sizes of SAIF and, even more so, FSDB/VCD files become massive and unmanageable
  2. The file generation process slows to a crawl that extends to hours, possibly exceeding a day
  3. File loading into a power estimation tool extends to several days or more than a week

New software for the Veloce emulation platform eliminates the core problems affecting the conventional approach to estimate power consumption. It eliminates the two-step, file-based flow by tightly integrating the emulator to the power analysis tool.

In this new approach, an Activity Plot maps in one simple chart the global design switching activity over time as it is occurring, booting an OS and running live applications.Image 2

Chart 1: The Activity Plot identifies focus areas over long runs.

It identifies time frames of high switching activities that may pose power threats to the design team. While this chart is not unique, its creation is an order of magnitude faster than the generation time of file-based power charts. As a data-point, Veloce takes 15 minutes to generate an Activity Plot of a 100-million gate design for 75-million design clock cycles. Power analysis tools could consume more than a week to generate similar information. Moreover, they may not be able to handle such a large volume of data.

Of course, the next questions are, “where” are those peaks happening in the DUT and “what” is causing them? This is addressed by replacing the file based approach with a Dynamic Read Waveform API for the signal data.

Dynamic Read Waveform API Flow

Once high-switching activity time frames are identified at the top level of the design, the design team can zoom into those frames. Users can dig deep into the hierarchy of the design and the embedded software to uncover the main source of such high-switching activity.

The Dynamic Read Waveform API replaces the cumbersome SAIF/FSDB/VCD file generation process by live streaming switching data from the emulator into the power analysis tool. All operations run concurrently, from emulating the SoC, design capturing switching data, reading switching data by the power analysis tool and generating power numbers. The net effect is a jump in overall performance from booting an OS and running real applications.

As a side benefit, the Dynamic Read Waveform API also delivers improved accuracy compared to SAIF-based average flows because conditional controls are incorporated automatically for switching.

The bottom line is that the Activity Plot and the Dynamic Read Waveform API enable power analysis and power exploration at the system level that is not possible with a file-based flow.

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7 May, 2015

For all things verification, you will want to stop by the Verification Academy booth #2408 at DAC to interact with experts exploring the challenges of IC design and verification.  At the top of each hour, the Verification Academy will feature a presentation followed by a lively conversation.  Presentations will not be repeated so each hour will be unique.

We have themed each of the days as well:

  • Monday is “Debug Day
  • Tuesday is “Standards & FPGA Day
  • Wednesday is “Formal Verification Day

Naturally, you will find a few exceptions to those rules when you look at the program in detail.  Please register for Verification Academy sessions here: Monday Registration | Tuesday Registration | Wednesday Registration.  [NOTE: the Verification Academy sessions are highlighted with a blue background when you visit the registration site.]  A concise listing of all the Verification Academy sessions can be found here.

We will feature an end of the day reception on Monday at the Verification Academy booth after the last presentation.  Neil Johnson (XtremeEDA) and Mentor’s Harry Foster will explore Agile Evolution in SoC Verification in that last session.  The session begins at 5pm.  Neil is a proponent of this methodology as a means to to help build in design quality and simplify the task of verification.  In addition to being an advocate for this, he is also a practitioner of it.  He is an open-source hardware developer and Moderator at www.AgileSoC.com.  We think the conversation that follows this informative session will be a lively one in which we invite everyone to continue over cocktails and hor d’oeuvres at 5:30pm.

We are sponsoring other events outside of the Verification Academy as well.  Tuesday is truly “Standards Day” at DAC.  In addition to the standards theme at the Verification Academy booth, you can kick off the day at the Accellera Breakfast and later in the day attend the IEEE DASC, Accellera and Si2 System Level Low Power Workshop.  Here is a partial list of Standards Day activities:

Registration

If you have not yet registered for DAC, do so now.  If you do not have plans to register for the full technical conference, many conference events are fee free if you select the “I LOVE DAC” registration option before May 19th!  In fact, all the “Standards Day” events listed above are free with early I Love DAC registration. Simply click here and you will be taken to the “I Love DAC” location to register.  Register before May 19th as after that date a $95 minimum fee sets in.

See you at DAC!

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17 March, 2015

StPatricksDay

With a name like “Fitzpatrick,” you knew I’d be celebrating today, right?

Well, there’s no better way to celebrate this fine day than to announce that our latest edition of Verification Horizons is available online! Now that Spring is almost here, there’s a bit less snow on the ground than there was when I wrote my introduction, but everything is still covered. I’m considering spray-painting it all green in honor of the occasion, so at least it looks like I have a lawn again.

In this issue of Verification Horizons, I’d particularly like to draw your attention to “Successive Refinement: A Methodology for Incremental Specification of Power Intent,” by my friend and colleague Erich Marschner and several of our friends at ARM® Ltd. In this article, you’ll find out how the Unified Power Format (UPF) specification can be used to specify and verify your power architecture abstractly, and then add implementation information later in the process. This methodology is still relatively new in the industry, so if you’re thinking about making your next design PowerAware, you’ll want to read this article to be up on the very latest approach.

In addition to that, we’ve also got Harry Foster discussing some of the results from his latest industry study in “Does Design Size Influence First Silicon Success?” Harry is also blogging about his survey results on Verification Horizons here and here (with more to come).

Our friends at L&T Technology Services Ltd. share some of their experience in doing PowerAware design in “PowerAware RTL Verification of USB 3.0 IPs,” in which you’ll see how UPF can let you explore two different power management architectures for the same RTL.

Next, History class is in session, with Dr. Lauro Rizzatti, long-time EDA guru, giving us part 1 of a 3-part lesson in “Hardware Emulation: Three Decades of Evolution.”

Our friends at Oracle® are up next with “Evolving the Use of Formal Model Checking in SoC Design Verification,” in which they share a case study of their use of formal methods as the central piece in verifying an SoC design they recently completed with first-pass silicon success. By the way, I’d also like to take this opportunity to congratulate the author of this article, Ram Narayan, for his Best Paper award at DVCon(US) 2015. Well done, Ram!

We round out the issue with our famous “Partners’ Corner” section, which includes two articles. In “Small, Maintainable Tests,” our friends at Sondrel IC Design Services show you a few tricks on how to make use of UVM virtual sequences to raise the level of abstraction of your tests. In “Functional Coverage Development Tips: Do’s and Don’ts,” our friends at eInfochips give you a great overview of functional coverage, especially the covergroup and related features in SystemVerilog.

I’d also like to take a moment to thank all of you who came by our Verification Academy booth at DVCon to say hi. I found it incredibly humbling and gratifying to hear from so many of you who have learned new verification skills from the Verification Academy. That’s a big part of why we do what we do, and I appreciate you letting us know about it.

Now, it’s time to celebrate St. Patrick’s Day for real!

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5 November, 2014

Between 2006 and 2014, the average number of IPs integrated into an advanced SoC increased from about 30 to over 120. In the same period, the average number of embedded processors found in an advanced SoC increased from one to as many as 20. However, increased design size is only one dimension of the growing verification complexity challenge. Beyond this growing-functionality phenomenon are new layers of requirements that must be verified. Many of these verification requirements did not exist ten years ago, such as multiple asynchronous clock domains, interacting power domains, security domains, and complex HW/SW dependencies. Add all these challenges together, and you have the perfect storm brewing.

It’s not just the challenges in design and verification that have been changing, of course. New technologies have been developed to address emerging verification challenges. For example, new automated ways of applying formal verification have been developed that allow non-Formal experts to take advantage of the significant benefits of formal verification. New technology for stimulus generation have also been developed that allow verification engineers to develop complex stimulus scenarios 10x more efficiently than with directed tests and execute those tests 10x more efficiently than with pure-random generation.

It’s not just technology, of course. Along with new technologies, new methodologies are needed to make adoption of new technologies efficient and repeatable. The UVM is one example of these new methodologies that make it easier to build complex and modular testbench environments by enabling reuse – both of verification components and knowledge.

The Verification Academy website provides great resources for learning about new technologies and methodologies that make verification more effective and efficient. This year, we tried something new and took Verification Academy on the road with live events in Austin, Santa Clara, and Denver. It was great to see so many verification engineers and managers attending to learn about new verification techniques and share their experiences applying these techniques with their colleagues.

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If you weren’t able to attend one of the live events – or if you did attend and really want to see a particular session again – you’re in luck. The presentations from the Verification Academy Live seminars are now available on the Verification Academy site:

  • Navigating the Perfect Storm: New School Verification Solutions
  • New School Coverage Closure
  • New School Connectivity Checking
  • New School Stimulus Generation Techniques
  • New School Thinking for Fast and Efficient Verification using EZ-VIP
  • Verification and Debug: Old School Meets New School
  • New Low Power Verification Techniques
  • Establishing a company-wide verification reuse library with UVM
  • Full SoC Emulation from Device Drivers to Peripheral Interfaces

You can find all the sessions via the following link:

https://verificationacademy.com/seminars/academy-live

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15 October, 2013

Low Power Flow Kicks-off Symposium

In the world of electronic design automation, as an idea takes hold and works its way from thought to silicon, numerous tools are used by engineers and the like to help bring a good idea to product fruition.  Standards play a key and important role to help move your user information from high-level concepts into the netlists can be realized in silicon.  The IEEE Standards Association is holding a Symposium on EDA Interoperability to help members of the electronics/semiconductor design and verification community better understand the landscape of EDA and IP standards and the role they play to address interoperability.

Another key component are the programs and business relationships we foster to promote tool connectivity and interoperability among each other.  The Questa users rely on the Questa Vanguard Partnership program so their trusted tool and technology partners have access to our verification technology to allow them to craft the leading edge design and verification flows with technology from numerous sources.  If your users want you to connect with Questa, we invite them to explore the benefits of this program.  Even better, join us at the IEEE SA Symposium on EDA Interoperability where can also discuss this in person – Register Here!

Event Details
Date: 24 October 2013
Time: 9:00 a.m. – 6:00 p.m. PT
Location: Techmart – 5201 Great America Parkway, Santa Clara, CA 95054-1125
Cost: Free!
Program: http://standards.ieee.org/events/edasymposium/program.html

One of the more pressing issues in design and verification today is address the issue of low power.  The IEEE SA Symposium on EDA kicks-off the morning with its first session on “Interoperability Challenges: Power Management in Silicon.”  The session will feature an opening presentation on the state of standardization by the Vice Chair of the IEEE P1801 Working Group (and Mentor Graphics Verification Architect) as well as two presentations from ARM on the use of the IEEE 1801 (UPF) standard.

11:00 a.m. – 12:00 p.m. Session 1: Interoperability Challenges: Power Management in Silicon
IEEE 1801 Low Power Format: Impact and Opportunities
Erich Marschner, Vice Chair of IEEE P1801 Working Group, Verification Architect, Mentor Graphics
Power Intent Constraints: Using IEEE1801 to improve the quality of soft IP
Stuart Riches, Project Manager, ARM
Power Intent Verification: Using IEEE1801 for the verification of ARM Cortex A53 processor
Adnan Khan, Senior Engineer, ARM

The event is sponsored by Mentor Graphics and Synopsys and we have made sure the symposium is free to attend.  You just need to register.  There are other great aspects to the event, not just the ability to have a conversation on the state of standards for low power design and verification in the morning.  In fact, the end of the event will take a look at EDA 2020 and what is needed in the future.  This will be a very interactive session that will open the conversation to all attendees.  I can’t wait to learn what you have to share!  See you at the Techmart on the 24th.

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28 June, 2013

Clocking and Power Trends

In Part 2 of this series of blogs, I continued the discussion focused on design trends (click here) as identified by the 2012 Wilson Research Group Functional Verification Study (click here). In this blog, I continue presenting the study findings related to design trends, with a focus on clocking and power trends.

Independent Asynchronous Clock Domains

Figure 1 shows the percentage of designs developed today by the number of independent asynchronous clock domains. The asynchronous clock domain data for FPGA designs is shown in red, while the data for the non-FPGA designs is shown in green.

 

Figure 1. Number of independent asynchronous clock domains

Figure 2 shows the trends in number of independent asynchronous clock domains for non-FPGA designs. The comparison includes the 2002 Collett study (in dark green), the 2007 Far West Research study (in gray), the 2010 Wilson Research Group study (in blue), and the 2010 Wilson Research Group study (in green).

Figure 2. Trends: Number of independent asynchronous clock domain

It’s interesting to note that, although the number of clock domains is increasing over time, the sweet spot in terms of number of independent asynchronous clock domains seems to remain between 2 and 20, and it hasn’t changed significantly in the past ten years.

Figure 3 provides a different analysis of the data by partitioning the projects by design sizes, and then calculating the mean number of independent asynchronous clock domains by project design. The design size partitions are represented as: less than 5M gates, 5M to 20M gates, and greater than 20M gates.

Figure 3. Mean number of independent clock domains by design size

Power Management

Today, we see that about 67 percent of design projects actively manage power with a wide variety of techniques, ranging from simple clock-gating, to complex hypervisor/OS-controlled power management schemes. We decided for the 2012 Wilson Research Group study that we wanted to take a closer look at power management related to functional verification. Hence, I can share some interesting results with you here. However, since this aspect of functional verification has never been studied in previous surveys, I will not be able to show trends. Our goal is to carry these same questions forward in our future studies so that we can identify trends.

For these, Figure 4 shows the various aspects of their power-managed design that they verify (for those 67 percent of design projects that actively manage power).

Figure 4. Aspects of power-managed design that are verified

In our study, we asked what percentage of simulation was power-aware (that is, verifying some functional aspect of the power-management scheme), and the results are shown in Figure 5. We were surprised to learn that about 10 percent of all designs that actively manage power perform no power-aware simulation to verify the power management scheme.

Figure 5. Percentage of simulation that verified some aspect of power management

In addition, we asked what percent of verification resources were focused on power management verification, and the results are shown in Figure 6. You will note that the curve is very similar to the percentage of total simulations that were power-aware, which you would expect. Again, we see that about 10 percent of the projects that actively manage power provide no verification resources to verify the power-management scheme.

 

Figure 6. Percentage of verification resources focused on power management

Figure 7 shows the different types of simulation-based functional testing approaches that are currently applied to verifying power management. It’s not a surprise that most power-aware simulation is based on directed-testing approaches since often (but not always) power-aware simulations are performed at the SoC integration level where directed testing is common.

 

Figure 7. Percentage of simulation that verified some aspect of power management

Since the power intent cannot be directly described in an RTL model, alternative supporting notations have recently emerged to capture the power intent. In the 2012 study, we wanted to get a sense of where the industry stands in adopting the notation. For projects that actively manage power, Figure 8 shows the various notations that have been adopted to describe the power intent. Some projects are actively using multiple standards (such as different versions of UPF or a combination of CPF and UPF). That’s why the adoption results do not sum to 100 percent.

 

Figure 8. Notation used to describe power intent

In my next blog (click here), I’ll present data on design and verification reuse trends.

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29 May, 2013

Download the standard now – at no charge

The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance and enhancement to the IEEE.  Further – Courtesy of Accellera – the standard is available for download without charge directly from the IEEE.

1801-2013_Page_001The latest update to IEEE 1801 is ready for download.  It joins other EDA standards, like SystemVerilog and SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF.  (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)

The official IEEE announcement on the standard’s publication can be found here.  And the official Accellera announcement that it has partnered with the IEEE-SA to offer the standard to all at no charge can be found here.  This revision of the standard had one of the largest number of IEEE-SA entity members of any corporate standards program.  Participation from the IEEE-SA global community of entity participants ensures the needs of a broad set of companies are captured to support this worldwide standard.

Just In Time For DAC

50th DACDAC 2013 has many events that will allow you to learn more about the new standard and how to use it to your maximum benefit.  And for those who cannot attend DAC, visit the Verification Academy, you will find the Low Power sessions cover the new standard as well. [Registration required; restrictions apply.]

Sunday
Topic: DAC Workshop:  Low-Power Design with the New IEEE 1801-2013 Standard
Date: 2 June 2013
Time: 1:00 p.m. – 5:00 p.m.
Location: Convention Center: Room 18C
Registration: Official DAC Workshop registration required ($). For more information and to register, click here.


Monday
Accellera Breakfast & Town Hall Meeting
Topic: The Standard for Low Power Design and Verification is here!  What’s next?
Date: 3 June 2013
Time: 7:00 a.m. – 8:45 a.m.
Location: Convention Center: Ballroom D
Registration: This is a free Accellera event, but registration is required.  Form more information click here and to register, click here.


Monday
Verification Academy
Topic: “Low Power Monday”
Date: 3 June 2013
Time: 11:00 a.m. – 6:00 p.m.
Location: Tradeshow Floor – Booth 1215
Registration: The DAC Tradeshow floor is open to all DAC registrants. Visit www.dac.com to register.

The Verification Academy is open to all DAC registrants.  There are no restrictions and we invite everyone to visit booth 1215 for Low Power sessions that may be of interest to you on Monday.  To help judge attendance, please feel free to pre-register at here.  I look forward to see you there as you will find me here most of the time Monday-Wednesday.

Time Description Presenter
11:00 a.m. – 12:00 p.m. Low Power Verification Tim Jordon
MicroChip Technlogy
1:00 p.m. – 2:00 p.m What’s New in UPF 2.1? Erich Marschner
IEEE 1801 Vice-chair
Mentor Graphics
2:00 p.m. – 3:00 p.m. UPF-Based Verification for Cypress PSOC Ellie Burns
Mentor Graphics
4:00 p.m. – 5:00 p.m. Optimizing for Power Efficient Design Abhishek Ranjan
Calypto
5:00 p.m. – 6:00 p.m. IEEE 1801 UPF Commands and Methodology John Biggs
ARM
IEEE 1801 Chair

If you are coming to DAC and participating in the DAC Low Power Workshop on Sunday, or in other events, download your person copy of the new IEEE 1800-2013 standard today.  The PDF form allows you to take it with you and read it using your favorite e-reader or i-device.  Let’s me know what you think of the standard.  And – See you at DAC!

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29 April, 2013

Power Aware Verification Course Modules Released

I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to out do the other when it came to puns. So it is understandable why the topic of low power standards takes me back to these fun exchanges.

But low power design and verification is a serious issue that design teams continue to grapple. To take advantage of emerging support of the new low power standard takes time and energy on part of practicing engineers and design teams. More information on what IEEE Std. 1801™-2013 (Unified Power Format) is and how you can use it is needed.

Back in March 2013 I blogged that the revised IEEE low power standard had been approved. I also mentioned there would be a short wait until the standard itself was published. And, indeed, we continue to wait for the final editing of the standard. I shared a link to a short article on the content of the standard, but more information is needed.

PA Verificatio Intro.jpgTo address this need, the Verification Academy has added a course on Power Aware Verification. There are six (6) sessions that will introduce you to power aware verification, UPF and walk you through an example to illustrate the use of the standard in more detail in about 1.5 hours. In order to access the course material you will need to be a “full access” registrant of Verification Academy. There is no fee for this, but restrictions apply.

In addition to watching the video course sessions online, you can also download the presentations and MP4 videos of the course for offline viewing.

The six course sessions are:

We are interested to get your feedback on the Power Aware Verification course and learn what additional sessions you think would help you get AMP’ed up to further the need to conserve energy. Let us know!

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14 March, 2013

IEEE 1801™-2013 Enters Pre-Publish Phase

The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.

If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).

As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication.  So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet.  So I won’t do that.  If you do need something, the superseded version from 2009 is the only one available at this moment.  I will keep you updated as to when it is published and ready for access to the global design community.

imageMentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled Bringing Verification and Validation under One Umbrella The Evolution of UPF: What’s Next?  (Free access; no registration required; 81KB)

Erich gives a good introduction to the new standard, also known as UPF 2.1.  He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.

Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot.  This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification.  If you are interested to join in with the IEEE 1801 team, visit here for more information.

DVCon UPF Tutorial

The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon.  For those who registered for the conference, the tutorial presentation is still available online.  Unfortunately, the material has not yet been made available to the general public.  If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy.  The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.

As for planning you can do now.  The IEEE 1801 team will host a tutorial at DAC on Sunday.  I will share more information with you on that once the DAC registration site goes live.  Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.

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