Posts Tagged ‘Low Power’
Power Aware Verification Course Modules Released
I guess I could continue the puns on the low-power theme as a few readers may get a charge out of it. And there is a reason I seem to gravitate to puns from the start. The first chair of the IEEE 1801 committee and I exchanged puns one time that resulted in him shipping me a Pun DVD that recorded a pun contest in which one person and another tried to out do the other when it came to puns. So it is understandable why the topic of low power standards takes me back to these fun exchanges.
But low power design and verification is a serious issue that design teams continue to grapple. To take advantage of emerging support of the new low power standard takes time and energy on part of practicing engineers and design teams. More information on what IEEE Std. 1801™-2013 (Unified Power Format) is and how you can use it is needed.
Back in March 2013 I blogged that the revised IEEE low power standard had been approved. I also mentioned there would be a short wait until the standard itself was published. And, indeed, we continue to wait for the final editing of the standard. I shared a link to a short article on the content of the standard, but more information is needed.
To address this need, the Verification Academy has added a course on Power Aware Verification. There are six (6) sessions that will introduce you to power aware verification, UPF and walk you through an example to illustrate the use of the standard in more detail in about 1.5 hours. In order to access the course material you will need to be a “full access” registrant of Verification Academy. There is no fee for this, but restrictions apply.
In addition to watching the video course sessions online, you can also download the presentations and MP4 videos of the course for offline viewing.
The six course sessions are:
- Introduction to Power Aware Verification (9 minutes)
- Overview of UPF (13 minutes)
- Getting Started with UPF (23 minutes)
- A Simple UPF Example (17 minutes)
- UPF 2.0 Enhancements (11 minutes)
- Using Supply Set (18 minutes)
We are interested to get your feedback on the Power Aware Verification course and learn what additional sessions you think would help you get AMP’ed up to further the need to conserve energy. Let us know!
IEEE 1801™-2013 Enters Pre-Publish Phase
The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now. Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013). The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.
If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).
As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication. So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet. So I won’t do that. If you do need something, the superseded version from 2009 is the only one available at this moment. I will keep you updated as to when it is published and ready for access to the global design community.
Mentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled The Evolution of UPF: What’s Next? (Free access; no registration required; 81KB)
Erich gives a good introduction to the new standard, also known as UPF 2.1. He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.
Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot. This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification. If you are interested to join in with the IEEE 1801 team, visit here for more information.
DVCon UPF Tutorial
The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon. For those who registered for the conference, the tutorial presentation is still available online. Unfortunately, the material has not yet been made available to the general public. If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy. The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.
As for planning you can do now. The IEEE 1801 team will host a tutorial at DAC on Sunday. I will share more information with you on that once the DAC registration site goes live. Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.
Learn about new standards, industry surveys and trends
This year’s DVCon is set and if you have not yet registered, you can do it now – or just show up! If you want to secure seating at some of the Monday tutorial events, I strongly encourage pre-registration to ensure you can secure a seat. And if you just want to see the exhibits and chat with suppliers, that’s free.
The IEEE low power format is set to close on its current round standardization shortly and DVCon is a great place to learn all about it from the experts. Harry Foster will update the DVCon attendees on design and verification trends over lunch on Tuesday and later that afternoon, Mentor CEO, Wally Rhines will offer this year’s DVCon keynote. His keynotes are always insightful and entertaining. And if you want to catch me, you can find me with the Mentor staff at the Mentor exhibit booth. Or just follow @dennisbrophy on Twitter and I will share info on paper presentations and other happenings. For more details on the events mentioned above, see below. For more information DVCon in general, visit the website at www.dvcon.org.
Monday | February 25th | 1:30pm – 4:30 | Fir Ballroom
Low Power Design, Verification, and Implementation with IEEE 1801™ UPF™
The past few years, the IEEE P1801™ (Unified Low Power – UPF) Working Group has been busy working on an update to the industry’s standard for low power design, verification and implementation. Accellera has brought together experts from many EDA tool suppliers and users for this tutorial. Attendees can expect to gain a detailed understanding of of the IEEE standard (concepts, terminology & features) as well as an understanding of the practical aspects to apply UPF in real world flows.
The following experts will be help you learn about the new standard – and will be available to interact with at the conclusion of the tutorial.
Tuesday | February 26th | 11:30am – 12:45pm | Pine/Cedar Ballroom
The Changing Landscape in Functional Verification: Industry Trends, Challenges, and Solutions
Presented by Harry Foster
Mentor Graphics invites you to join us for lunch—where we will present, for the first time publicly, highlights from this year’s Wilson Research Group Functional Verification Study. Be the first on your block to learn the latest verification trends, challenges, and solutions.
Learn more, then register.
Tuesday | February 26th | 3:30pm – 4:30pm | Oak/Fir Ballroom
Speaker: Wally Rhines, Chairman and CEO of Mentor Graphics
As a thought provoking, timely, and informative presentation, this keynote session will focus on functional verification trends and the accelerated adoption of advanced functional verification technologies, methodologies and languages.
Learn more, then register.
Tuesday & Wednesday (February 26th & 27th)
3:30pm – 6:30pm
I look forward to meet up with those who attend DVCon. You can catch me at or around the Mentor booth for the last three hours of the conference.
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design. The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well. A whole host of educational modules and seminars can also be found there too.
If you know about the Verification Academy, you know all about the content mentioned above and that there is much more to be found there. For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum. (Flash is required to watch Harry discuss Verification Academy with Luke.)
The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends. Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations. While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations. Verification Academy “Total Access” members now have access to many of the presentations.
Thales Alenia Space
Test & Verification Solutions
Total Access members can also download all the presentations in a .zip file. Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.
Tags: ABV, ACE, ams, ARM, Assertion-Based Verification, Coverage Closure, dac, Doulos, formal, IEEE, iTBA, Low Power, OVM, SystemVerilog, Tech Design Forum, Thales, upf, UVM, UVM Express, Verification Academy, Verification Trends
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
- May 2013 (2)
- April 2013 (2)
- March 2013 (2)
- February 2013 (5)
- January 2013 (1)
- December 2012 (1)
- November 2012 (1)
- October 2012 (4)
- September 2012 (1)
- August 2012 (1)
- July 2012 (6)
- June 2012 (1)
- May 2012 (3)
- March 2012 (1)
- February 2012 (6)
- January 2012 (2)
- December 2011 (2)
- November 2011 (2)
- October 2011 (3)
- September 2011 (1)
- July 2011 (3)
- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
- February 2011 (4)
- January 2011 (1)
- December 2010 (2)
- October 2010 (3)
- September 2010 (4)
- August 2010 (1)
- July 2010 (3)
- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
- July 2009 (1)
- May 2009 (1)