Posts Tagged ‘IEEE’
In my previous blog, I introduced the 2012 Wilson Research Group Functional Verification Study (click here). The objective of my previous blog was to provide background on this large, worldwide industry study. I will present the key findings from this study in a set of upcoming blogs.
This blog begins the process of revealing the 2012 Wilson Research Group study findings by first focusing on current design trends. Let’s begin by examining process geometry adoption trends, as shown in Figure 1. Here, you will see trend comparisons between the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (blue line), and the 2012 Wilson Research Group study (green line).
Figure 1. Process geometry trends
Worldwide, the median process geometry size from the 2007 Far West Research study was about 90nm, while the median process geometry size is about 65nm in 2010. Today, the mean process geometry size for a typical project is about 45nm—although you can see that over a third of projects today are designing below 32nm.
In addition to the industry moving to smaller process geometries, the industry is also moving to larger design sizes as measured in number of gates of logic and datapath, excluding memories (which should not be a surprise). Figure 2 compares design sizes from the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line).
Figure 2. Number of gates of logic and datapath trends, excluding memories
The study revealed that about a third of the non-FPGA designs today are less than 5M gates, while a third range in size between 5M to 20M gates, and about a third of all designs are larger than 20M gates.
It’s important to note here that the data on the mean design size trends does not reflect volume in terms of semiconductor production. For example, you could have fewer projects designing at a small geometry, yet they have higher volume in terms of production.
In Figure 3, I show the mean design size trends between the 2002 Collett study (dark blue line), the 2007 Far West Research study (gray line), the 2010 Wilson Research Group study (light blue line), and the 2012 Wilson Research Group study (green line). Obviously, gate counts have increased over the years, yet a significant number of designs continue to be developed with smaller (and larger) gate counts as indicated by the mean calculation. Another observation is that, as you would expect, the mean gate count trend is essentially following Moore’s law.
Figure 3. Mean design size trends
Figure 4 presents the current design implementation trends for non-FPGAs as identified by the survey participants.
Figure 4. Non-FPGA current design implementation trends
The data in Figure 4 presents trends in design implementation approaches for non-FPGA designs, ranging from the 2002 Collett study (dark blue bar), the 2004 Collet study (dark green bar), the 2007 Far West Research study (gray bar), the 2010 Wilson Research Group study (blue bar), and the 2012 Wilson Research Group study (green bar). Note that the study seems to indicate that there is a downward trend in standard cell design implementation.
Figure 5. FPGA design implementation trends
For the 2012 study, we decided that we wanted to get a sense of the percentage of FPGA projects that target the very complex programmable SoC FPGAs that have recently emerged, which is shown in Figure 5. Examples of these programmable SoC FPGAs include: Xilinx’s Zynq, Altera’s Arria/Cydone, and Microsemi’s SmarFusion.
In my next blog (click here), I’ll continue discussing current design trends, focusing specifically on embedded processors, power, and clock domains.
This is the first in a series of blogs that presents the results from the 2012 Wilson Research Group Functional Verification Study.
In 2002 and 2004, Ron Collett International, Inc. conducted its well known ASIC/IC functional verification studies, which provided invaluable insight into the state of the electronic industry and its trends in design and verification. However, after the 2004 study, no other industry studies were conducted, which left a void in identifying industry trends.
To address this void, Mentor Graphics commissioned Far West Research to conduct an industry study on functional verification in the fall of 2007. Then in the fall of 2010, Mentor commissioned Wilson Research Group to conduct another functional verification study. Both of these studies were conducted as blind studies to avoid influencing the results. This means that the survey participants did not know that the study was commissioned by Mentor Graphics. In addition, to support trend analysis on the data, both studies followed the same format and questions (when possible) as the original 2002 and 2004 Collett studies.
In the fall of 2012, Mentor Graphics commissioned Wilson Research Group again to conduct a new functional verification study. This study was also a blind study and follows the same format as the Collett, Far West Research, and previous Wilson Research Group studies. The 2012 Wilson Research Group study is one of the largest functional verification studies ever conducted. The overall confidence level of the study was calculated to be 95% with a margin of error of 4.05%.
Unlike the previous Collett and Far West Research studies that were conducted only in North America, both the 2010 and 2012 Wilson Research Group studies were worldwide studies. The regions targeted were:
- North America:Canada,United States
- Asia (minusIndia):China,Korea,Japan,Taiwan
The survey results are compiled both globally and regionally for analysis.
Another difference between the Wilson Research Group and previous industry studies is that both of the Wilson Research Group studies also included FPGA projects. Hence for the first time, we are able to present some emerging trends in the FPGA functional verification space.
Figure 1 shows the percentage makeup of survey participants by their job description. The red bars represents the FPGA participants while the green bars represent the non-FPGA (i.e., IC/ASIC) participants.
Figure 1: Survey participants job title description
Figure 2 shows the percentage makeup of survey participants by company type. Again, the red bars represents the FPGA participants while the green bars represents the non-FPGA (i.e., IC/ASIC) participants.
Figure 2: Survey participants company description
In a future set of blogs, over the course of the next few months, I plan to present the highlights from the 2012 Wilson Research Group study along with my analysis, comments, and obviously, opinions. A few interesting observations emerged from the study, which include:
- FPGA projects are beginning to adopt advanced verification techniques due to increased design complexity.
- The effort spent on verification is increasing.
- The industry is converging on common processes driven by maturing industry standards.
My next blog presents current design trends that were identified by the survey. This will be followed by a set of blogs focused on the functional verification results.
Also, to learn more about the 2012 Wilson Reserach Group study, view my pre-recorded Functional Verification Study web-seminar, which is located out on the Verification Academy website.
Quick links to the 2012 Wilson Research Group Study results (so far…)
- Part 1 – Design Trends
Tags: accellera, Assertion-Based Verification, formal verification, functional coverage, functional verification, IEEE, Simulation, Standards, SystemVerilog, UVM, Verification Academy, Verification Methodology, verilog, vhdl
Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program.
As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements that will be of interest to design and verification engineers alike. However, providing the standard as freely available download is major news.
Even though the relative cost of the LRM was minor compared to the cost of most projects utilizing the standard, there seemed to be a barrier in most engineer’s minds in justifying the expense. So most just continued to use the last freely available SystemVerilog 3.1a LRM, which was 9 years old and very obsolete for such a rapidly changing technology.
Ready for 100 billion “things” connected by the Internet?
The IEEE Standards Association (SA) Corporate Advisory Group (CAG) has been working to bring industry input into the standards development organization on the emerging Internet of Things (IoT) trend that will connect billions of devices with each other.
As you can imagine, the impact this will have to the service structure down to the development of connected devices will have impact on tools used to create, verify and test them from the EDA industry to the protocols that will need to be in place to facilitate this.
This past summer the oneM2M was launched to bring some groups together who were dedicated to product technical specification for the M2M Service Layer. The impact on the IEEE, that is responsible for ongoing Internet standardization, is likewise large and not totally known.
I was reminded of the IoT impact this week by ARM’s EVP, Simon Segars. His ARM Techcon keynote presentation this week. noted the IoT is a merging of our digital and physical worlds. He also said predictions are the data from smartphones is “exploding at a 100% growth rate a year for the next 4-5 years.” To make the point even more stunning, Simon shared that Facebook expects 1-2 billion pictures will be taken and uploaded to their website around Halloween 2012. The good news for those who did not have the time to make it to Santa Clara, CA USA for ARM Techcon, his presentation has been made available for viewing on YouTube. You can find it here.
The IoT conversation continues around the globe.
IEEE IoT Workshop: You are invited!
IEEE has restored service to their Internet connection at www.ieee.org. However, connection from IEEE staff locations is tentative due to the widespread devastation of Hurricane Sandy in the New Jersey USA area where they live and work. There may be delays in getting official invitations out on the IoT workshop. The IEEE workshop on Internet of Things has been put together in conjunction with several of the CAG member companies, with direct leadership from our STMicroelectonics representative and input from representatives from Broadcom, GE Medical, Ericsson, Qualcomm and others. The IEEE SA staff and IoT Workshop leadership have asked those who are connected to share workshop information. I am doing that here.
You are invited to attend and participate in the workshop. Details on the event are:
The event will feature a combination of keynote speeches, product showcase and panel sessions with the goal to:
- identify collaboration opportunities and standardization gaps related to IoT
- help industry foster the growth of IoT markets;
- leverage IEEE’s value and platform for IoT industry-wide consensus development,; and
- help industry with the creation of a vibrant IoT ecosystem.
Date: 13 November 2012
Location: Milan, Italy
- Service Provider’s View of the IoT World (SP)
- End to End Systems Security (ST)
- IEEE-SA – Perfect Platform for the New Millennia of Consensus Development
Panel Topics include:
- GW as an Enabler of the New Services in the IoT World
- Monetizing Services in the IoT World
- Security in the IoT World
- Standard, what we have and what is missing, convergence in the technology world, collaboration opportunities.
31 October 2012 4:25 p.m. PDT
Access to ieee.org has been restored. That was quick! You can now access IoT Workshop details from IEEE directly.
31 October 2012 3:00 p.m. PDT
Due to the impact of Hurricane Sandy, power to IEEE servers has been lost and backup power sources have been depleted. Access to the IEEE website for more information, registration and additional details is not available at this moment. The workshop will be held.If the servers return to the Internet, I will update this notice.And if their absence appears to be something that will last longer than another day or so, I will update this blog with alternate contact information for those who would like more detailed information on how to register and where to go to attend the event.
OVM Bridges SystemVerilog and SystemC Languages
When UVM Connect was first released, the multilingual connection between IEEE Std. 1800™ (SystemVerilog) and IEEE Std. 1666™ (SystemC) standards bridged the two languages to allow design and verification engineers to access UVM from SystemC or SystemVerilog to exploit native languages advantages. OVM users wondered if it was possible to support them as well since OVM is a derived from UVM.
It is possible and UVM Connect has been extended to allow OVM users to enjoy the same benefits. An update to UVM Connect now allows it to be compiled to run with the OVM. And since the extensions are based on IEEE standards, they can be used in your simulator of choice.
The thriving OVM community is of no surprise. Last year, Harry Foster blogged about research on the use and adoption of verification methodologies. The research was done after UVM was established as an Accellera standard, and showed OVM continued its leading position as shown in one of the charts from Harry’s blog (see below). The chart even showed OVM was predicted to have a modest growth in adoption as well.
Mentor continues to bring many of the UVM additions back to the OVM user community in a way that does not disturb the upgrade path from OVM to UVM. The major addition to UVM in the first round of Accellera standardization was the addition of a register and memory package. This was back ported to OVM. (The OVM register and memory kit can be found here, if you are interested.) Now, UVM Connect has been extended to provide full OVM use.
If you find issues or have other suggestions that we should consider, you can always share your input at the OVM Forum or UVM Forum. In addition to interacting with other users, the Verification Academy is a good site for online resources like the UVM/OVM Cookbook, basic and advanced OVM/UVM training, and more.
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards”
The EDA industry has seen changes to the international standards paradigm the past few decades. When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version. In addition to anchoring the standard at the IEEE, collaboration with the IEC for international standardization and recognition with the one-country, one-vote process set the stage for international approval of VHDL.
In the early days of Verilog, I encouraged similar support for that IEEE standard. But its support was not immediate and to some may have failed to track the pace of support by industry. Indeed, with Accellera developing SystemVerilog, later to become an IEEE standard and IEC standard, what was missing was the close link between a global industrial community and the international setting in which the standard was developed and deployed.
In the case of SystemVerilog, global markets drove the international deployment of the standard without respect to its formal status. Indeed, on what was called the “birthday” of SystemVerilog in Japan, the day it was approved as an official IEEE standard, the Japanese National Committee on standards hosted an open celebration that I was invited to attend. There was no waiting on their part the formal status. The interdependencies of global design, global commerce and global partnerships have driven all of us to adapt the standards development process for EDA.
You can learn more about the supporters of OpenStand, their guiding principles and how you can give your input, comments and feedback by visiting their website at http://open-stand.org. And if you agree, you can even “stand” with them; with me; with us.
But in short, OpenStand promotes a standards development model that demands:
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design. The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well. A whole host of educational modules and seminars can also be found there too.
If you know about the Verification Academy, you know all about the content mentioned above and that there is much more to be found there. For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum. (Flash is required to watch Harry discuss Verification Academy with Luke.)
The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends. Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations. While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations. Verification Academy “Total Access” members now have access to many of the presentations.
Thales Alenia Space
Test & Verification Solutions
Total Access members can also download all the presentations in a .zip file. Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.
Tags: ABV, ACE, ams, ARM, Assertion-Based Verification, Coverage Closure, dac, Doulos, formal, IEEE, iTBA, Low Power, OVM, SystemVerilog, Tech Design Forum, Thales, upf, UVM, UVM Express, Verification Academy, Verification Trends
Open-Source Proof-of-Concept Library Released
Accellera Systems Initiative has released for general industry use an open-source proof-of-concept library as a companion to the recently minted IEEE Std. 1666™-2011, SystemC Language Reference Manual standard
In November 2011, the IEEE Standards Association approved IEEE Std. 1666-2011. The completed and published standard was made available to the community as a whole for free in an agreement between Accellera Systems Initiative and the IEEE Standards Association in February 2012. As a reminder, you can download your personal copy of IEEE 1666 here for free.
In the nearly 6 months since this version of the standard has been available about 7,000 copies have been downloaded under the IEEE Get program.
The previous version was also made available for free download and was just as popular as this version of the standard is.
While the approved standard was being made ready for publication, Accellera Systems Initiative was also busy completing the open-source proof-of-concept library. After taking comments and feedback from a public review process, version 2.3.0 of the library was completed and is now available.
IEEE 1666-2011 added a number of important new features, including support for transaction-level modeling (TLM) that has proven to be an important element to enable high-level design and is a key component upon which the Universal Verification Methodology (UVM) is built from.
For those who want to used the SystemC library directly, it is now available for wide industry access.
The downloads from the IEEE and Accellera Systems Initiative will require some license agreement approvals. The links are not one-click access to the material below.
- IEEE 1666-2011 Standard
All who download will need to agree to a click-through IEEE license and declare a “user type.”
- SystemC 2.3.0 Open-Source Proof-of-Concept Library
Non-members need to register as a “community participant” in order to download the library and regression tests.
IEEE Std. 1666™-2011 Available as Free Download
In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011. One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM). I pointed to several online resources to learn more about the revised SystemC standard in that blog. But missing from the list of resources was information on how to get the revised standard from the IEEE. As I concluded my blog, I indicated that the final editorial review and formatting for publication was underway and that I would report back when this work was completed.
I can report that the IEEE SA concluded their editing of the specification and it is now ready for download. Many of you know the prior version of the SystemC standard was available for free download and have wondered if this would be the same for this revision update. The good news is the revision update is available as a free download as well. If you wish to have a printed and bound copy, that too is available, but that will have to be purchased.
IEEE Std. 1666-2011 is part of the “IEEE Get Program” that offers individuals the ability to retrieve, download and print one copy of the standard for free. Click on the link above to get your personal copy of the standard. You will need to share some basic information with the IEEE on your user type (Academic, System/Semiconductor Company, EDA Company, IP Company or Other). This is certainly worth if for a free copy.
The original standard, IEEE Std. 1666™-2005, had more than 50,000 free downloads since it was made available and I expect this version to do even better. With the addition of TLM to the standard and the move up in abstraction to handle system design requirements, the need for this standard is even more pressing today.
Is Legacy Holding You Back?
Harry Foster, Mentor’s Verification Chief Scientist, will take center stage to give live presentations on the pressing SoC verification issues as he highlights recent research he has been reporting on in his numerous blogs. The first event will be held in San Jose, CA USA (18 October 2011) and the second event will be held in Reading, UK (15 November 2011).
Harry has been reporting on the 2010 Wilson Research Group Functional Verification Study that has shown a rapid market move towards the broadly supported SystemVerilog (IEEE 1800) language standard and ubiquitous support of the OVM/UVM methodologies. While humans have a general disdain for change, human nature also seems to wait to respond to the “crowd effect” to make a change. It appears the market is in the throes of this strain as the market moves in a direction leaving legacy behind.
To learn firsthand from Harry, I recommend attending two upcoming events where he will speak:
Date: 18 October 2011 (Tuesday)
Event: Design & Verification in the SoC Era
Location: DoubleTree – San Jose, CA USA
Cost: Free; registration restrictions apply
Date: 15 November 2011 (Tuesday)
Event: Verification Futures: The Next Five Years
Location: Hilton Hotel, Reading, UK
Legacy set for replacement?
Have you ever noticed that one restaurant alone may get little traffic, but if there are many restaurants clustered together, they garner much greater traffic than going it alone? The crowd effect demonstrates its power and user benefit with choice and bounty. After DVCon 2011, I blogged about Wally Rhines’ keynote address and pointed to one slide that showed SystemVerilog is the clear language winner and pointed to another slide that showed OVM/UVM, built on top of SystemVerilog, as the clear methodology winner.
This has impact on legacy. And those with entrenched legacy may find it hard to adopt market driven standards practice quickly. This is to be expected.
When Accellera began its Verification IP Technical Subcommittee (VIP-TSC), I argued that the first step is to preserve legacy investment and offer a path to reuse that which has proven valuable in the past. The vote to move in this direction was close with consumer input saying all efforts should focus on a single industry supported base class library and standard. My point was we could build it, but if there was no path from where consumers were, there would be limited uptake. In a short time, a proof that OVM and VMM could interoperate demonstrated that we knew how to do this. It also gave hope that other proprietary and single-supplier solutions could take this work and adapt it for their paths forward.
With that finished, the Accellera VIP-TSC set to create the Universal Verification Methodology (UVM) standard. This has now been completed, short of finishing one commitment to expand the Phasing scheme and address a few lingering issues. While Accellera could focus on completing this work, users and owners of legacy verification languages and proprietary environments have come to realize a startling truth: the market has moved away from them. And, proprietary and single-solution suppliers have offered little in terms of paths forward. They now look for Accellera to address legacy preservation requirements and do it for them.
While this was to be expected, their shock has exposed the fact that more work could have been done on building the bridges to legacy’s past in the initial phase rather than now when the market demands time and focus on its adopted standards practice instead.
Why bring all this up?
We now find the Accellera VIP-TSC has a bifurcated focus. Part of the focus is to complete the content promises for UVM 1.0 and the other is to preserve legacy investment. But can Accellera overcome the crowd effect? The crowd effect, after all, has taken hold. In terms of product choice, legacy offers one product from a single supplier to SystemVerilog’s multiple competitive suppliers. When it comes to bounty, the availability of legacy verification IP has fewer and fewer sources while OVM/UVM offer an expanding bounty.
In the face of this rapid market move, one can expect single solution suppliers will extol features of their solution over the market’s choice. Users faced with the grim prospect of having to adapt to market changes will praise the past in hopes others will depart from the crowd. I am at a loss to think of a time when actions like this have worked to change the market. Maybe someone knows of examples and can share them.
In fact, I was a user who praised the technical benefits of one format over another. I made further investments in it. I even moved to a new job in a new area to find the community I moved to seemed to favor my selected format equally with what was to be the market winner. In time, in very short time, even my new community gave way to the market and the crowd. Can you guess what that format was?
I will share the details this with you next week when I discuss how one might actually bring value to legacy while allowing the market to continue its move forward. In the meantime, if you are close to the San Jose, CA or Reading, UK events, I suggest you register to attend.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Texas-Sized DAC Edition of Verification Horizons Now Up on Verification Academy
- IEEE 1801™-2013 UPF Standard Is Published
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- May 2013 (4)
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- February 2013 (5)
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- June 2011 (6)
- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
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- January 2011 (1)
- December 2010 (2)
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- June 2010 (9)
- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
- February 2010 (5)
- January 2010 (5)
- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
- September 2009 (2)
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