Posts Tagged ‘IEEE-SA’

8 September, 2013

Schedules, respins, and bug classification

This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here).

In my previous blog (Part 11 click here), I focused on some of the 2012 Wilson Research Group findings related to formal verification, acceleration/emulation, and FPGA prototyping trends. In this blog, I present verification results findings in terms of schedules, respins, and classification of functional bugs.

We have seen in previous blogs that a significant amount of effort is being applied to functional verification. An important question the various studies have tried to answer is whether this increasing effort is paying off.

Schedules

Figure 1 presents the design completion time compared to the project’s original schedule. What is interesting is that we really have not seen a change in this trend in over five years. That is, 67 percent of all projects are behind schedule with respect to the original plan. One could argue that designs have increased in complexity in terms of gate counts, embedded processors, and lots of software between 2007 and 2012. Yet, achieving project schedules has not worsened.

Figure 1. Non-FPGA design completion time compared to the project’s original schedule

What’s interesting is that the FPGA designs follows this same trend, as shown in figure 2.

Figure 2. Non-FPGA vs. FPGA design completion time relative to the original plan

Respins

Other verification data points worth looking at relate to the number of spins required between the start of a project and final production. Figure 3 shows this industry trend all the way back to the 2004 Collett study. Again, even though designs have increased in complexity, the data suggest that projects are not getting any worse in terms of the number of spins before production. If anything, there appears to be a slight improvement recently in this trend in projects requiring three or more spins.

Figure 3. Number of spins required from start of project until production

Bug classification

Figure 4 shows various categories of flaws that are contributing to respins. Note that the sum is greater than 100% on this graph, which is because a respin can be triggered by multiple flaws. 

Figure 4. Number of spins required from start of project until production

Although logic and functional flaws remain the leading causes of respins, the data suggest that there has been some improvement in this area over the past eight years. Is this due to the increased amount of reuse that is occurring in the industry? Or is the industry maturing its verification processes? Or is something entirely different going on? This data point raises some interesting questions worth exploring.

Figure 5 examines root cause of functional bugs by various categories. The data suggest an improvement in logic errors over an eleven year period, and potentially, a worsening of problems related to changing specifications. Problems associated with changing, incorrect, and incomplete specifications is a common theme I often hear when visiting customers.

Figure 5. Root cause of functional flaws

In my next blog (click here), I plan to wrap up this series of blogs in what I call the Epilogue—which will discuss potential gotchas and cautions on interpreting certain aspects of the data and thoughts about how the data might be used constructively.

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5 August, 2013

Language and Library Trends

This blog is a continuation of a series of blogs that present the highlights from the 2012 Wilson Research Group Functional Verification Study (for a background on the study, click here).

In my previous blog (Part 7 click here), I focused on some of the 2012 Wilson Research Group findings related to testbench characteristics and simulation strategies. In this blog, I present design and verification language trends, as identified by the Wilson Research Group study.

You might note that for some of the language and library data I present, the percentage sums to more than one hundred percent. The reason for this is that some participants’ projects use multiple languages.

RTL Design Languages

Let’s begin by examining the languages used for RTL design. Figure 1 shows the trends in terms of languages used for design, by comparing the 2007 Far West Research study (in gray), the 2010 Wilson Research Group study (in blue), the 2012 Wilson Research Group study (in green), as well as the projected design language adoption trends within the next twelve months (in purple) as identified by the study participants. Note that the design language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption continues to increase.

Also, it’s important to note that this study focused on languages used for RTL design. We have conducted a few informal studies related to languages used for architectural modeling—and it’s not too big of a surprise that we see increased adoption of C/C++ and SystemC in that space. However, since those studies have (thus far) been informal and not as rigorously executed as the Wilson Research Group study, I have decided to withhold that data until a more formal blind study can be executed related to architectural modeling and virtual prototyping.

Figure 1. Trends in languages used for Non-FPGA design

Let’s now look at the languages used specifically for FPGA RTL design. Figure 2 shows the trends in terms of languages used for FPGA design, by comparing the 2012 Wilson Research Group study (in red) with the projected design language adoption trends within the next twelve months (in purple).

Figure 2. Languages used for Non-FPGA design

It’s not too big of a surprise that VHDL is the predominant language used for FPGA RTL design, although we are starting to see increased interest in SystemVerilog.

Verification Languages

Next, let’s look at the languages used to verify Non-FPGA designs (that is, languages used to create simulation testbenches). Figure 3 shows the trends in terms of languages used to create simulation testbenches by comparing the 2007 Far West Research study (in gray), the 2010 Wilson Research Group study (in blue), and the 2012 Wilson Research Group study (in green).

Figure 3. Trends in languages used in verification to create Non-FPGA simulation testbenches

The study revealed that verification language adoption is declining for most of the languages with the exception of SystemVerilog whose adoption is increasing. In fact, SystemVerilog adoption increased by 8.3 percent between 2010 and 2012.

Figure 4 provides a different analysis of the data by partitioning the projects by design size, and then calculating the adoption of SystemVerilog for creating testbenches by size. The design size partitions are represented as: less than 5M gates, 5M to 20M gates, and greater than 20M gates. Obviously, we find that the larger the design size, the greater the adoption of SystemVerilog for creating testbenches. Yet, probably the most interesting observation we can make from examining Figure 4 is related to smaller designs that are less than 5M gates. Here we see that 58.8 percent of the industry has adopted SystemVerilog for verification. In other words, it is safe to say that SystemVerilog for verification has become mainstream today and not just limited to early adopters or leading-edge design projects.

Figure 4. SystemVerilog (for verification) adoption by design size

Let’s now look at the languages used specifically for FPGA RTL design. Figure 5 shows the trends in terms of languages used for FPGA design, by comparing the 2012 Wilson Research Group study (in red) with the projected design language adoption trends within the next twelve months (in purple).

Figure 5. Trends in languages used in verification to create FPGA simulation testbenches

In my next blog (click here), I’ll continue the discussion on design and verification language trends as revealed by the 2012 Wilson Research Group Functional Verification Study.

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14 March, 2013

IEEE 1801™-2013 Enters Pre-Publish Phase

The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.

If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).

As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication.  So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet.  So I won’t do that.  If you do need something, the superseded version from 2009 is the only one available at this moment.  I will keep you updated as to when it is published and ready for access to the global design community.

imageMentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled Bringing Verification and Validation under One Umbrella The Evolution of UPF: What’s Next?  (Free access; no registration required; 81KB)

Erich gives a good introduction to the new standard, also known as UPF 2.1.  He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.

Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot.  This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification.  If you are interested to join in with the IEEE 1801 team, visit here for more information.

DVCon UPF Tutorial

The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon.  For those who registered for the conference, the tutorial presentation is still available online.  Unfortunately, the material has not yet been made available to the general public.  If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy.  The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.

As for planning you can do now.  The IEEE 1801 team will host a tutorial at DAC on Sunday.  I will share more information with you on that once the DAC registration site goes live.  Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.

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25 February, 2013

Today at this week’s DVCon 2013 conference, the IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera) have jointly announced the public availability of the IEEE 1800 SystemVerilog Language Reference Manual at no charge through the IEEE Get Program.

As I posted a few weeks ago, the 1800-2012 is not a major revision of the standard, but does contain a few enhancements that will be of interest to design and verification engineers alike. However, providing the standard as freely available download is major news.

Even though the relative cost of the LRM was minor compared to the cost of most projects utilizing the standard, there seemed to be a barrier in most engineer’s minds in justifying the expense. So most just continued to use the last freely available SystemVerilog 3.1a LRM, which was 9 years old and very obsolete for such a rapidly changing technology.

Thanks Accellera!

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5 December, 2012

IEEE Std. 1800™-2012 Officially Ratified

The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard.  The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.

What’s New?

The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification.  DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard.  The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics).  You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.

For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance.  As Stu and Tom said in their presentation, “This is BIG!”  If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.

Major work was done to augment the current notion of constraints in SystemVerilog.  In past versions of the standard they were known as hard constraints.  What this meant was all the conditions of the constraints had to be met otherwise there would be an error.  There was no built-in method to relax the need to satisfy the constraints.  Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high.  To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard.  If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard.  Stu and Tom said that “This is also a big enhancement!”

Availability

IEEE 1800™-2012 has only now been approved.  The standard itself is not ready to be published yet.  Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013.  I will  share publication information as it becomes available.  And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.

sva3rdE_cover-wsWhile the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now.  For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more.  You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well.  You can find more information about it on Amazon.com here.

The Story Continues…

There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead.  The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.

Stay tuned!  For now, I encourage you to get informed!

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22 March, 2012

Remembering Don Loughry

“How did you get involved in standards,” I was asked.

On a business trip to India in 2009, I was asked to come by the Mentor office in Noida to meet with some “freshers” and other participants in Mentor’s Displaced Worker Program who were in the middle of a SystemVerilog training.  As one of many who have been engaged in the development of the SystemVerilog (aka IEEE Std 1800™-2009) standard the past decade, they were curious to know how I became involved in the development of this standard.

“How did you get involved in standards,” I was asked.

“My work on SystemVerilog comes from an early exposure to IEEE standards, much like you are getting today,” I told them.

In the late 1970’s a visiting lecture from Hewlett-Packard spent a year at UC Davis where I went to school.  One of the courses I took was a hardware interface to computers course that borrowed from the Hewlett-Packard Interface Bus (HP-IB).  While we all called the protocol HP-IB, it was already an IEEE standard.  Today it is known as IEEE Std 488.1™-2003.

In addition to the normal material that had to be purchased for the class, I also had to buy a copy of the IEEE standard.  My first thought was the standard was expensive!  When looking inside the standard, it looked more like a someone used an IBM Selectric typewriter to write it and inserted hand-drawn state diagrams.  Maybe I bought a draft of the standard instead.  This is not at all the IEEE standards of today.

Recently I visited IEEE Xplore and downloaded the current standard and the content, as I would expect, looks nothing like the one I bought for my class.  Print was professional as all the standards look today.  Even the state diagrams are computer generated.

This was my first IEEE standard I bought, studied and built prototype interfaces to connect.  While one might have expected we would have spent 100% of our course time on the application of what we were learning, we did not.  We got a dose of indoctrination on the importance of standards.  “There may be times in your professional career where you may need to volunteer on standards development: Do it,” we were told.

This is the story I related to those learning SystemVerilog in Noida.  I told them the knowledge they gain may prove to be indispensable in the work they do in the years ahead.  But thank you for the question on how I got involved in standards, as it reminds me I should encourage you to be mindful of standards in your future.  Let me pass on what I learned from Hewlett-Packard that if there is a time in your professional career where you  may need to volunteer for standards development: Do it.

My Mentor, In Pectore

In late 2006, my home phone number rings.  I answer.  “Hi, this is Don Loughry calling on behalf of the IEEE and I have some good news to share with you.”  “What is the good news,” I ask.  “You have been elected to the IEEE Standards Association Board of Governors.  As past chair it is my privilege to bring you this news,” he says.  […] “Thank you, I look forward to serving,” I said as I concluded the call.

Many weeks later, my office number rings and I answer.  “Hi this is Don Loughry calling.  Dennis, is this you,” he asks.  “Yes, this is Dennis,” I say.  “Did you see the email I sent to you asking if you would join the Charles Proteus Steinmetz awards committee,” he asked.  “No, I can’t recall seeing that email.  Does your email come in with your first or last name listed,” I asked.  “Neither,” Don told me.  “You will see my email address as ‘Sunkist,’” he said.  “Oh, I thought I got some message from the ‘orange company’ and did not read it.  Let me do that now,” I said.  And, yes I joined the committee.  [From this moment on, Don Loughry was known to me as Sunkist, though I never told him.]

Not too long ago, I related the story of getting involved in standards – the story above – with the now chair of the IEEE SA BoG, Steve Mills.  Steve is with Hewlett-Packard Co. and told me that standardization of HP-IB/IEEE 488 was the work of Don Loughry.  He was also instrumental in setting a corporate culture that was pro-standardization and Steve told me the encouragement I got  to “think standards” while in college is “all Don.”

Interesting, I thought.  How I got here has a lot to do with what Don Loughry has done.  This was not self evident to me, and kept in secret, in pectore, to me and Don for that matter.  Don, my mentor, in pectore.

As you have read the title of the blog, you know there is some sad news to share.  This is it:

Don passed away about a month ago.  And as I write this, family and friends plan to gather this weekend to remember him.  While his life will be recounted by personal and professional accomplishments extraordinaire – and Don’s are certainly substantial by any measure – his ripples on the pond of life continue to radiate and touch many.  In my case, his call to volunteer for standards has become my endeavor.  As Don has called to action, I have with those I met in Noida in 2009, as I do now with you dear reader of this blog.

Expression of Gratitude

While Don led the development of IEEE 488, he was also key to the development of IEEE 802.3 (the Ethernet LAN standard) that connects 100’s of millions of machines around the world today.  We should all be grateful for that.

He launched the IEEE Standards Association and served as its first president.  We all benefit from his vision.  Standards developers around the globe are grateful for this.

And as for Don appointing me to be a member of the Charles Proteus Steinmetz committee, I went on to be its chair for a couple years.  I am grateful for his trust.

As an aside, Don was given the 2003 Steinmetz award.  Having been on the committee and its chair, I was offered one action of privilege this year.  And that was to appoint myself to be a member of the committee a last time as its past chair.  I appointed myself.  Thank you Don for your initial appointment to this committee.

The week before last, while in India, after concluding a long week of meetings for the IEEE SA Corporate Advisory Group, it was bittersweet as I dialed into my last Steinmetz committee meeting.   I could not finish the call in my hotel room before having to check out and share a ride to the Bangalore airport.  Therefore I continued the call on my mobile phone in the car.  I thank my friend from Broadcom for sharing his car to the airport with me.  And, knowing Broadcom may like 802.3 a bit, perhaps I can be forgiven for this minor annoyance – knowing the rest of the story now.  After all, “How did I get here?”  How did I become to be on the phone for this call at this moment?  In large measure by Don, the same person who helped sow the seeds that Broadcom reaps today with 802.3.

To Sunkist

Yes, I know why Don’s email address has “sunkist” in it.  I came to learn why when we were on the Stienmetz committee together when he participated as “past chair.”  And no, it is not about oranges.  However, oranges will be one of those things that will remind me of him.  So why it is his email address that way?  Well, let’s say that is one thing I will keep in pectore.

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5 December, 2011

The DASC Participates in IEEE Standards Association Gala Event

The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA  on 4 December 2011.  Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor the few who are exceptional examples.

The DASC recognized Larry Saunders as its “Ron Waxman Design Automation Standards Committee Meritorious Service Award” recipient.  Larry was recognized “for pioneering the standardization of VHDL that fundamentally changed the electronic system design process.”

As someone who has worked with Larry on and off over the years to promote the use of VHDL, I know firsthand he is very deserving of this recognition and it was a pleasure to be present as he, one of the renowned VHDL fathers, was given this award.  Yatin Trivedi, vice-chair of the DASC and director of standards at Synopsys gave a glowing tribute to Larry, not just from his DASC leadership role, but as a colleague, friend and mentor.

Pearl & Ron Waxman, myself, Larry Saunders, April Mitchell, Yatin Trevidi and Karen Bartleson from the DASC pose for a photo after the ceremony.

In addition to the “Ron Waxman” award, the IEEE-SA Working Group Chair Awards were also officially recognized.  From the DASC, two of the working groups completed standards development and published their work and a few members of each of those groups were given Working Group Chair awards.

1076.1.1™-2010 IEEE Standard for VHDL Analog and Mixed-Signal Extensions – Packages for Multiple Energy Domain Support
Tom Alderton, Peter J. Ashendon, Ernst Christen, David W. Smith

1647™-2011 IEEE Standard for the Functional Verification Language e
Mike Bartley, Darren Galpin, Amy Witherow

Yatin’s citation for the Ron Waxman Award, Ron’s additional background on Larry’s contributions and Larry’s acceptance video can be seen below.  The microphone was a bit away from the speakers and it was recorded at some distance from the speakers so the sound may be a bit hard to hear unless you use headphones.  But for those who were not there and might like to see it, it is offered for you.

Larry Saunders Accepts DASC Ron Waxman Meritorious Service Award

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10 November, 2011

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support

A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC standard, IEEE 1666™-2005, the major new feature added was Transaction-Level Modeling (TLM), which is new to an IEEE standard.

For many years now, the TLM specification and accompanying open source code has been incubating in the Open SystemC Initiative (OSCI).  OSCI’s TLM Working Group has developed the TLM 1.0 and TLM 2.0 specifications, both of which are part of the revised IEEE 1666 standard.  TLM is important to SystemC, but it has also been leveraged outside of it.

We at Mentor Graphics pioneered the use of TLM in SystemVerilog (IEEE 1800™-2009) when our seminal open-source work on the Advanced Verification Methodology (AVM) brought an implementation to the verification community based on SystemVerilog.  This lives on today, as AVM motivated the Open Verification Methodology (OVM), which became the basis for Accellera’s Universal Verification Methodology (UVM).

If you don’t already know what TLM is and how the verification community is using it in OVM and UVM, the Verification Academy has a lot of written material and video training modules that will help you learn how this important new IEEE standard is used from simulation to emulation and has boosted verification productivity.  The “Understanding TLM” module is featured in the Advanced UVM section, so if you are still a novice to UVM, you may wish to start with the Basic material first.  This module is presented by fellow Verification Horizons Blogger, Tom Fitzpatrick and offers subtitles in English, Russian, Japanese and Chinese (Traditional & Simplified) to help drive rapid global adoption.

As we brought TLM into the modern verification methodology practice with a SystemVerilog implementation, it also surfaced that there is an opportunity for the creator of TLM, OSCI, and an adopter of it in UVM, Accellera, to discuss what they could do together.  And as I’ve blogged before, those two organizations announced their intention to unite before the end of 2011, as others have seen the potential when both are brought together.  I expect to see more great ideas come from these two groups when they join forces, just like the TLM work that is now an IEEE standard.

For those who want a copy of the revised IEEE 1666 standard, it is still in final IEEE editorial review as the they do their last formatting.  I will share with you when it is ready to use as well as how to get it and where to find it.

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3 February, 2011

ieee_mb_blueIEEE Standards Association Hosts Design Automation Standardization Workshops in Bangalore & Delhi

I, along with several other individuals, will participate in two IEEE-SA EDA standardization workshops in India on Friday, 4 February 2011 in Bangalore and on Thursday 10 February 2011 in New Delhi.  In the last year, the IEEE announced it opened an office in Bangalore, India.  This is the fourth IEEE office in Asia, following China, Japan and Singapore.

A large number of IEEE’s members reside in India and the EDA standards get a lot of use and attention in India.  There is a strong and thriving IEEE Std 1800™ SystemVerilog community in India that are helping to extend the verification capabilities of the language.  As the IEEE office gets setup, I look forward to it to help better coordinate standards development of a global community of companies and individuals.

Agenda: Bangalore, India Workshop (Register)
Location: Mentor Graphics, Bangalore

8:30 Registration opens
9:00 Welcome–Pamela Kumar (IBM)
9:05 IEEE-SA and the World of Standards
Dennis Brophy, Member, Board of Governors, IEEE-SA
Director of Business Development, Mentor Graphics
9:45 Standards in Design Automation: Influencing Design and Verification Methodologies
Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666)
Yatin Trivedi, Member, Standards Education Committee, IEEE-SA
Director of Standards, Synopsys
10:30 Tea-Break
11:00 Impact of Standards in Design Environment
Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA
CAD Manager, Freescale
11:30 Anecdotes of Participation in Standards Activities
Srinivasan Venkataramanan, CTO, CVC, Bangalore
11:45 Panel Discussion: Standards, Industry and Academia
Moderator: Pamela Kumar
Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra, SriniVenkataramanan, Anuradha Srinivasan (Intel)
12:30 Conclusion & Thank You

A set of IEEE-SA Board of Governors meetings will be held at the beginning of the the week of February 7th.  And in addition to the meeting on design automation standards in Bangalore, a group of workshops are also planned in Mumbai on 4 February 2011 on Cloud Computing and Smart Grid by other colleagues I volunteer with on the IEEE-SA Board of Governors.   There are more IEEE-SA events planned for the week of February 7th and a full list can be found here.

For those who wish to join the New Delhi design automation workshop, some details of it can be found below.

Agenda: New Delhi, India Workshop (Register)
Location: IIT

8:30 Registration opens
9:00 Welcome—Karen Bartleson (Synopsys)
9:05 IEEE-SA and the World of Standards
Dennis Brophy, Member, Board of Governors, IEEE-SA
Director of Business Development, Mentor Graphics
9:45 Standards in Design Automation: Influencing Design and Verification Methodologies
Low power (1801); Design & Verification productivity (1800, 1735); System Design (1666)
Yatin Trivedi, Member, Standards Education Committee, IEEE-SA
Director of Standards, Synopsys
10:30 Tea-Break
11:00 Impact of Standards in Design Environment
Sri Chandra, Chair, Standards Interest Group, India Chapter, IEEE-SA
CAD Manager, Freescale
11:30 Anecdotes of Participation in Standards Activities
Srinivasan Venkataramanan, CTO, CVC, Bangalore
11:45 Panel Discussion: Standards, Industry and Academia
Moderator: Karen Bartleson
Participants: Dennis Brophy, Yatin Trivedi, Sri Chandra
12:30 Conclusion & Thank You

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14 April, 2010

Accellera and The SPIRIT Consortium Merger is Complete

An open SystemVerilog requirements gathering meeting sponsored by the IEEE Design Automation Standards Committee’s (DASC) SystemVerilog Study Group was hosted at Mentor Graphics after DVCon 2010. While the meeting room was packed with many of the world’s SystemVerilog cognoscenti – as well as many from around the world on the phone.

Cliff-at-SV-Req-Gathering-Mtg-Web

MGC-Victory-Room-Web Dave Rich posted his blog on the meeting and shared a link that allowed everyone to see the top-3 items Users and Producers sought from the next version of SystemVerilog.  But while Cliff was making his presentation on “Design Connectivity Features,” a few people slipped out of the room into the “Victory” room next door.

What can now be disclosed was the Accellera and The SPRIRIT Consortium representatives were signing final documents to ensure the merger of the two organizations, announced at DAC 2009, would become final.

Shrenik-Stan-Web Shrenik Mehta, for Accellera and Stan Krolikoski, for The Spirit Consortium could be seen taking pen to paper as the final signatures were done to cement the merger.  With final legal and governmental reviews complete, the merger became official and was announced today.  The press release crossed the wires this morning.  The merged organization will retain the Accellera name and have 8 active standards projects.  It has also recommitted that is is aligned to create formal standards through the IEEE Standards Association.

Congratulations to the merger teams and staff that worked hard to make it a smooth merger process.  Mentor Graphics looks forward to the benefits of the electronics industry when electronic design language-based standards are brought together with Intellectual Property (IP) standards.

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