Posts Tagged ‘iec’
VHDL-2008 Explained Via 7 Course Modules
For some time now a dedicated group of engineers have defined and standardized an important update to the VHDL standard. Also know as IEEE Std. 1076™-2008, this update to VHDL took an interesting path to get to where it is today. The VHDL standards team started the standards development work in the IEEE but sought additional input and standards project funding from industry. Accellera provided a good venue in which to get industry input and feedback for an update to the VHDL standard along with funding. Once industry input was taken into account, the proposed update to VHDL, approved by Accellera, was returned to the IEEE for official standards ratification and ongoing maintenance. Jim Lewis, the IEEE VHDL Working Group Chair, points out this is the greatest update to VHDL since VHDL 93. And I agree. Jim is also the subject matter expert for the VHDL-2008 course modules on Verification Academy mentioned in this blog.
Verification Academy Modules
In less than an hour and half – over 7 course modules – Jim will layout out the additions and changes to VHDL-2008 to simplify the language and extend it to address more of your pressing design and verification challenges with the addition of reusable data structures, simplified RTL coding and the inclusion of fixed and floating point math packages.
As part of my role in international standardization as co-convenor of the IEC TC 93 WG2 (now known as IEC TC 91 WG 13) and in keeping with the IEEE/IEC dual-logo agreement, I helped complete the dual logo process for this version of VHDL in 2011. VHDL-2008 is also now known as IEC 61691-1-1-2011 – Behavioural languages – Part 1-1: VHDL Language Reference Manual. I think we can all agree that that name is a bit much that we can simply call it VHDL-2008.
With this round of standardization complete, the VHDL-2008 course modules arrive just as complete support for VHDL-2008 emerges here at Mentor Graphics in our ModelSim and Questa products.
I encourage and invite VHDL users to get acquainted with VHDL-2008 via the seven course modules on Verification Academy. Verification Academy “Full Access” membership is required. And it is easy to sign up (certain restrictions apply). For a quick look at what the courses offer, the introduction page found here will show you more details about the following modules.
|“VHDL-2008 Why It Matters” Modules|
Additional Reference Material
There is additional reference material you may wish to have to get the most out of VHDL-2008. Here is my short list:
- IEEE Std. 1076-2008 Language Reference Manual (Click here)
- VHDL-2008: Just the New Stuff (Click here)
- The Designer’s Guide to VHDL, Third Edition (Click here)
Five Leading Global Organizations Affirm “The Modern Paradigm for Standards”
The EDA industry has seen changes to the international standards paradigm the past few decades. When industry helped launch VHDL with the help of government support, it transferred ongoing maintenance and enhancement to the IEEE when it completed its first version. In addition to anchoring the standard at the IEEE, collaboration with the IEC for international standardization and recognition with the one-country, one-vote process set the stage for international approval of VHDL.
In the early days of Verilog, I encouraged similar support for that IEEE standard. But its support was not immediate and to some may have failed to track the pace of support by industry. Indeed, with Accellera developing SystemVerilog, later to become an IEEE standard and IEC standard, what was missing was the close link between a global industrial community and the international setting in which the standard was developed and deployed.
In the case of SystemVerilog, global markets drove the international deployment of the standard without respect to its formal status. Indeed, on what was called the “birthday” of SystemVerilog in Japan, the day it was approved as an official IEEE standard, the Japanese National Committee on standards hosted an open celebration that I was invited to attend. There was no waiting on their part the formal status. The interdependencies of global design, global commerce and global partnerships have driven all of us to adapt the standards development process for EDA.
You can learn more about the supporters of OpenStand, their guiding principles and how you can give your input, comments and feedback by visiting their website at http://open-stand.org. And if you agree, you can even “stand” with them; with me; with us.
But in short, OpenStand promotes a standards development model that demands:
United States Plays Host in Seattle, WA
The IEC’s 47th General Assembly meeting opened on October 11th in Seattle, WA USA. Plans had been put in place for about 2,500 delegates but that number was exceeded by nearly 25% with more than 3,100 people registered. Three days before the start of the meeting the Technical Committee 93, which addresses all the design automation standards held seven working group meetings from Friday-Sunday. On Monday the group reported out conclusions of all the committee’s working groups.
Working Group 2 manages the process to promote dual-logo standards development between the IEEE and IEC for design languages and may be of particular interest to VHDL, Verilog, SystemVerilog and SystemC users. In addition to the responsibility to manage design language dual-logo standards, WG 2 has maintenance responsibility for IBIS, the I/O Buffer Information Specification. IBIS 4.2 is on the work plan for standardization. The Japanese National Committee’s technical report from JEITA on their Bird’s eye View of Design Language (BVDL) was also submitted as an official submission.
The TC 93 addresses a broad spectrum of standards for the design automation of electronic devices ranging from printed circuit boards and systems to semiconductor devices and systems. From that broad swath of interests, two dual-logo candidates germane to language-based design flows were on the agenda for consideration by the IEC Standards Management Board (SMB).
Specifically, IEEE Std 1076-2008 and IEEE Std 1800-2009 were approved by the SMB at the start of the meeting series on 11 October 2010 as dual-logo standards. For those who purchase their standards from the IEC or their national standards bodies, the VHDL standard is known as IEC 61691-1-1 Ed. 2.0 (2010) and the SystemVerilog standard is known as IEC 62530 Ed. 2.0 (2010). The content between the IEEE and IEC are the same with the exception of the cover page of the standard, which will carry both the IEEE and IEC logo. Different countries have different rules and laws to recognize standards. The IEC plays a key role to bridge these differences to promote efficient and effective global use of VHDL, Verilog, SystemVerilog, SystemC and more.
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This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
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