Latest posts

Simulation is Key in design verification process

The importance of simulation in the pursuit of absolute speed!

A casual conversation with an ex-insider of the high frequency trading sector reveals surprising details about simulation and their design-verification process

In Memoriam: Chris Spear

Our friend and colleague Chris Spear passed away suddenly. He was a long-time veteran of our industry and was known…

SystemVerilog

Get your free copy of the IEEE 1800-2023 SystemVerilog LRM

At last year’s Design & Verification Conference (DVCon), I presented a few changes to the upcoming revision to the SystemVerilog…

DVCon 2024 – Verify Real Number Models

Solving Puzzle Do you like to solve puzzles? I do, and I think every engineer does. Since we are solving…

UVM Objections at DVCON US 2024 – and Grape Jelly

Boiling Grape Jelly Stay with me – trust me. There’s a tie in to UVM Objections and DVCON US 2024….

Accellera Day at DVCon U.S. 2024

DVCon U.S. 2024 will be a week packed with paper sessions, tutorials, panels, keynotes and more on the latest in…

Join us at DVCon for a panel on Generative AI

It’s that time of year again, and I couldn’t be more excited for the 2024 Design & Verification Conference &…

Welcome to the enhanced Verification Academy 2.0 forums!

We’ve recently enhanced the Verification Academy, moving to an all new platform. The Verification Academy is the industry’s leading resource…

Welcome to Verification Academy 2.0!

Step into the enhanced Verification Academy 2.0! After a year of meticulous development, we are thrilled to unveil its array…