Posts Tagged ‘esl’
Watch DVCon Co-Located Event Presentations
Two presentations from the second annual SystemC Day at DVCon 2011 are available now. The first presentation is the keynote by Jim Hogan, serial EDA entrepreneur at Vista Ventures, LLC and the second is an introduction to the emerging IEEE Std. 1666™, SystemC standard by Jim Aynsley at Doulos. SystemC Day brought users together to discuss the current state of the market for ESL design and the pending content of the SystemC standard that is current in final ballot by the IEEE.
To view the video presentations, you will need to register with the Open SystemC Initiative.
Abstract: SoCs are becoming ubiquitous in semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.
Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
John Aynsley, Doulos Ltd., UK
The New IEEE 1666 SystemC Standard
Abstract: The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.
Noted EDA analyst and guru Gary Smith delivered keynote address: “ESL: Where We Are and Where We’re Going”
OSCI sponsored the first annual SystemC Day at DVCon 2010. The presentations were video recorded and are available for free for those who missed DVCon or who may wish to see them again. Gary Smith’s presentation (registration required) and OSCI chair, Eric Lish’s OSCI Update lead the video set from SystemC Day.
The 12th North American SystemC Users Group (NASCUG) meeting was part of SystemC Day at DVCon and featured technical presentations on architectural modeling, verification, and analog/mixed-signal design using SystemC.
OSCI ON YOUTUBE: More videos of users and their perspectives on SystemC events and activities can be found via the OSCI channel on YouTube: http://www.youtube.com/officialsystemc
Click here for completing listing of the following technical presentations.
|The Metaport: A Technique for Managing Code Complexity
Jack Donovan, HighIP Design, Texas, USA
The metaport is a coding style that can effectively manage code complexity for complex ESL models, especially models that are intended for high-level synthesis. This presentation will give an overview of the metaport concept and dive into the details of a possible implementation.
|OCP Socket Modeling with TLM-2.0
Hervé Alexanian, Sonics Inc., California, USA
This presentation discusses work performed by the OCP-IP Committee, specifically modeling that OCP built upon the TLM-2.0 standard.
|ADL Synthesis using ArchC
Samuel Goto, Master student at UNICAMP
The design and implementation of processors is a complex task. Architecture Description Languages (ADLs) were created to extend existing HDLs, to ease the process of developing and prototyping an architecture by providing a set of tools and algorithms to optimize and automate some of the tedious parts. While much has been done on the specification and business levels of ADLs, there is a huge gap between ADL specifications/simulators and real life processors written in RTL. This project addresses the issues of bringing an ADL description to the RTL level, and reports the development of an extension of ArchC to support this level.
|Look Ma, No Clocks! Improving Model Performance
David Black, XtremeEDA, Texas, USA
This tutorial-style presentation illustrates some techniques to avoid the inclusion of clocks in SystemC simulations and provide results of simple experiments showing the simulation performance benefits. Concepts discussed include synchronization, clock-free timers, and the effects of clocks on performance. A proposal is made for a simple SystemC class that can simplify coding when clocks are thought to be needed.
|TLM-driven Design and Verification Methodology
Brian Bailey, independent consultant
SystemC is well on the road to adoption in a number of areas within the Electronic System Level (ESL) space, but many of those are separated islands today. Virtual Prototyping has seen a huge leap forward with the standardization of TLM 2.0. SystemC is also being used successfully for high-level synthesis at the module level, but to make SystemC pervasive, there must be a link between the applications. In addition, to reap the maximum productivity gains from a migration to a higher-level of abstraction, the verification methodology must also change in significant ways. In this presentation we will explore a new TLM-driven design and verification methodology that is being developed within Cadence, critiqued by their customers and documented in a book, which will be released over a number of months as pieces of it mature.
SystemC User Group Meeting & DVCon Tutorial Featured
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to support and advance SystemC™ as an industry-standard language for electronic system-level (ESL) design, announced its lineup of events at DVCon 2010, most notably the first annual SystemC Day on Monday, Feb. 22.
Mentor Graphics is one of the sponsors for the event and we will share updates on products that support SystemC during the SystemC Supplier Showcase between 10:00 a.m. – 2:00 p.m. Visit us at the Showcase or at the DVCon tradeshow.
How to Register
Admission is free with advance registration to the North American SystemC Users Group Meeting (NASCUG 12) and complimentary lunch. The afternoon tutorial is part of the DVCon program and requires separate registration.
- NASCUG 12 Meeting and Lunch
Register at: www.mod-marketing.com/osci (FREE)
- DVCon Tutorial: The OSCI TLM-2.0 Standard and Synthesis Subset
Register at: www.dvcon.org/reg.html ($60 DVCon Fee)
|8:30 am – 12:00 pm||NASCUG 12 Meeting (Full agenda at www.nascug.org)|
|10:00 am – 2:00 pm||Sponsor Tabletop Exhibits|
|12:00 pm – 1:30 pm||OSCI Sponsored Lunch|
|1:30 pm – 5:00 pm||DVCon Tutorial: “The OSCI TLM-2.0 Standard and Synthesis Subset
|5:00 pm||DVCon Hosted Reception|
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Part 7: The 2010 Wilson Research Group Functional Verification Study
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- Part 5: The 2010 Wilson Research Group Functional Verification Study
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- Part 3: The 2010 Wilson Research Group Functional Verification Study
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
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- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
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- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
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- UVM Register Package 2.0 Available for Download
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- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
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- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
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- Truth in Labeling: VMM2.0
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- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
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- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
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- Welcome to the Verification Horizons Blog!
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