Posts Tagged ‘dvcon’

3 March, 2014

DVCon is always one of my favorite events in our industry, and I am proud to let you know that the latest issue of Verification Horizons is available “hot off the presses” at the Verification Academy to mark the occasion. For those of you attending the conference, please consider this issue as an addendum to the great technical program being offered (especially paper 8.1, “Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It” by Dave Rich and yours truly). For those of you not able to join us at DVCon this year, consider this your consolation prize.

Although fewer in number, I’m sure you’ll find the articles in Verification Horizons as informational and useful as any you’ll see at DVCon. In particular, I’d like to make sure you check out these articles by our partners:

  • “Don’t Forget the Little Things That Can Make Verification Easier” by our friend Stu Sutherland of Sutherland HDL
  • “Taming Power-Aware Bugs with Questa Ultra” by SmartPlay Technologies
  • “Using Mentor Questa for pre-silicon validation of IEEE 1149.1-2013 based Silicon Instruments” by Intellitech
  • “Dealing With UVM and OVM Sequences” by eInfochips

If you’re at DVCon, please make sure to stop by the Mentor Graphics booth (#501) to say hi. Please join us on Wednesday for our luncheon presentation at noon, right after Session 8, in which I’ll present my paper mentioned above (that’s right. I’m not above shameless self-promotion). And we’ll wrap up the week with two Mentor-sponsored tutorials on Thursday:

Both of these tutorials feature a mix of Mentor presenters and customers to offer some practical examples that will give you some new ideas for improving your verification process. I hope to see you at DVCon.

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27 February, 2014

DVCon 2014 LogoPsst!  I’ll let you in on some news…

While DVCon calls the free portion of the conference “Exhibits Only,” let me share a little secret for you – You also gain access to the conference panels and the keynote presentation.

For those in Silicon Valley and local to DVCon, I invite you to register for the FREE side of the conference, not just for the conference exhibition that will have (in evening hours) drinks and appetizers, but for the industry conversation that will be offered via panels and CEO keynote.  The two panels will also feature Mentor Graphics speakers so you can learn our opinions on the topics as well.

How do you secure your FREE pass?  That’s the simple part!  Go here and start the registration process by clicking the “REGISTER NOW” button in the upper right.  After entering your contact information and completing a brief survey, you will be asked to select the part of the conference you wish to attend.  Select “Exhibit Only” for no charge.  Then “checkout” to complete your registration and you are done!  Of course, you can just show up and do this onsite.  But why waste time in line when you can do this from your computer or mobile device?

See you there!  You can find us at our Mentor Graphics booth.  We are booth 501.  (P.S., if you cannot spare the time to attend but would like to see a running commentary on the sessions, panels and other happenings follow me on Twitter: @dennisbrophy or look for the conference hashtag #DVCon.)

Now here is what you can get for free:

Panels

Is Software the Missing Piece In Verification?

Moderator Ed Sperling – Semiconductor Engineering
Panelists Tom Anderson – Breker
Kenneth Knowlson – Intel
Steve Chappell – Synopsys
Sandeep Pendharkar – Vayavya Labs
Frank Schirrmeister – Cadence Design Systems
Mark Olen – Mentor Graphics
Location Oak Ballroom
Date & Time Wednesday – 5 March 2014 8:30am – 9:45am

Did We Create the Verification Gap?

Moderator John Blyler – Extension Media
Panelists Janick Bergeron – Synopsys
Jim Caravella – NXP
Harry Foster – Mentor Graphics
John Goodenough – ARM
Bill Grundmann – Xilinx
Mike Stellfox – Cadence Design Systems
Location Oak Ballroom
Date & Time Wednesday – 5 March 2014 1:30pm – 3:00pm

Keynote

An Executive View of Trends and Technologies in Electronics
Lip-Bu Tan, President & CEO Cadence Design Systems
Oak Ballroom
Tuesday – 4 March 2014 2:00pm – 2:30pm

Exhibition

Monday: 5:00pm – 7:00pm (Booth Crawl included; Attendees open to win $500 gift card!)
Tuesday: 2:30pm – 6:00pm (Reception 5:00pm – 6:00pm)
Wednesday: 2:00pm – 6:00pm (Reception 5:00pm – 6:00pm)

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25 February, 2014

As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well.  Would you expect less?

In DVCon’s recent past, it was a tradition for the North American SystemC User Group (NASCUG) to sponsor a day of activity before the official start of the conference.  When OSCI merged with Accellera, the day before the official conference start grew to become Accellera Day with a broader set of meetings and activities covering many of Accellera’s standards.  This has all grown into a more official part of the DVCon program.  On Monday at DVCon – or as many still call it – Accellera Day – the tradeshow now joins in opening.  I covered this in detail in an earlier blog, so I won’t repeat myself now.

The pre-conference education and meet-up to discuss the latest in standards development is joined by an end of conference tutorial series that has expanded to allow four parallel sessions from three.  Instead of the one tutorial we at Mentor Graphics would otherwise sponsor at DVCon, we will offer two in this expanded series. Given the impact verification has on design it would seem right that more time be devoted to topics that address this.  One half-day tutorial is just to short to give the subject its due respect.

The two Mentor Graphics sponsored tutorials at DVCon, to be run in series, will devote a day to explore the application of current verification technology by us and users like you.  If you are already attending DVCon, you are making your tutorial selections now.  And for those who might only be interested to attend the tutorials themselves, DVCon offers a tutorials-only package ($145/Tutorial).  Mentor’s two tutorials are:

The first tutorial references “smooth sailing,” not because this will be a “no-pirate zone,” although I can tell you that since International Talk Like a Pirate Day is in late September, one won’t have to worry about a morning of pirate talk! [Interesting Fun Fact: Mentor Graphics’ headquarters in Wilsonville, OR USA is a short 50 miles (~80 km) north of the creators of this parotic holiday.]  The smooth sailing comes from the ability to easily use multiple engines from simulation, formal, emulation, FPGA prototyping to address your block to system-level verification needs.

The second tutorial is all about formal.  Or, in a more colloquial way to say it, we will answer the question: Whatsup with formal?  No, I doubt we will find more slang terms for formal technology being used and created in the tutorial.  But the tutorial will certainly look at more focused applications of formal technology.  As a pioneer in focused formal applications (like clock domain crossing) the creation of these focused formal applications has greatly simplified use and expanded technology access to verification teams with RTL design checks, X-state verification, and more joining the list.  Maybe we should ask Whatsapp with formal! But wait!  That slang question is already taken – and Facebook affirmed ownership with a $19B purchase of it recently.  Oh well, I lament.  Join me at this tutorial and we can explore something suitable and not yet taken as a replacement.  I can’t think of a better way to close DVCon than to see if we can invent another $19B term (or app).

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23 February, 2014

UVM 1.2 Release is Imminent

As vice chair of DVCon 2014, I can share with you that the Universal Verification Methodology (UVM) remains a topic of great interest.  It sets the pace for tutorials and given the pending release by Accellera, learning what is new in UVM 1.2 is a compelling reason to attend DVCon.

The Accellera Day tutorial series on Monday at DVCon is popular with UVM being a session of great interest.  Aside from the “verification crisis” driving the need to explore this industry standard, the first major update is also a reason to generate this interest.  The UVM tutorial is meant for the novice and expert alike.  UVM experts can expect to walk away with more information on the new UVM 1.2 features and how they might plan to deploy them.

Naturally, I suggest you consider registering for the conference to attend this tutorial.  (There are still a few seats left; but you will need to hurry!)

UVM Working Group Discussions

As a member of the Accellera UVM Working Group, I have asked the team to consider adopting the SystemC development scheme of an open public review of a pending release of open source code.  While the merger of OSCI and Accellera to form Accellera Systems Initiative inherited the OSCI style of public review, Accellera has not fully embraced it for all its projects.

In a disclosure of a bit of insider conversation I had with the UVM WG this last week, I asked the group to confirm that we were going to bypass the “official” public review option and go to an internal 30-day review cycle only – then release to the public.  While the conclusion was to stay on the 30-day internal review path, the group also noted that one who may be familiar with Git might be able to locate the source code (and many have) and do testing.

Since the bleeding-edge users know they can access as it is being developed, why not share the Git commands for everyone to gain access?  So the group has done just this.  When last minute changes for Release Candidate 4 were put in place, the Git script to offer access for early review was shared publicly.  You can find can find this public message here, thanks to UVM WG member Adiel Khan (from Synopsys).

If you are a seasoned UVM user and are attending DVCon the week of March 3rd, I would encourage you to do some testing now so you can connect with the developers first hand.  And even if you are not attending DVCon but want to migrate to UVM 1.2, you might want to get an early start to determine what you might need to do to adopt this release.

If you are not going to attend the DVCon UVM tutorial and want a short update on what this version will offer, the UVM WG secretary, Adam Sherer (from Cadence), put together a brief slide set that he presented at the TVS DVClub event in September 2013 that you can download.  You may find it a useful companion to the download of the open source code.

Even if you are not attending DVCon, the adoption of UVM is globally substantial and it might be good to reflect on the need for broader testing.  In the first releases of UVM, this may not have been as important as few were using it and the number of tests limited to the main developers.  However, as its popularity has grown and adoption increased, it is probably a good idea for the Accellera UVM Working Group to consider the impact of a new release on teams actively using it now.  While the UVM WG drives to closure on its release candidate and the UVM 1.2 standard, you are offered the opportunity to give us feedback.  For those who have time, please do!

Mentor Commentary on Standards Development

Lastly, for those attending DVCon, check out our own Tom Fitzpatrick’s Wednesday morning paper – Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It. His commentary on the development process may shed some additional light into how technology additions, changes and enhancements are judged for inclusion in updates to standards, like UVM.

Resources:
- UVM 1.2 New Feature Presentation (Sept 2013): Download Here (Free)
- UVM 1.2 Public Review Instructions (Feb 2014): Download Here (Free)
- Mentor Commentary at DVCon: Register Here ($)

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11 February, 2014

DVCon 2014 LogoOne of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera standards.  And this year’s DVCon is no exception.  The four days of DVCon begin and end with tutorials that cover updates to popular standards like UVM, UPF, SystemC and more.  For our part, Mentor Graphics is participating in the development and delivery of these updates with our peers.

UVM LogoI have written in the past about the productivity challenges before us to address the verification crisis and the emergence of machine-to-machine communication and the Internet of Things driving power aware design and verification.  To advance the demands on improved verification and help to address the verification crisis, the next round in the Universal Verification Methodology (UVM) standard is being readied for industry adoption.  UVM 1.2, the emerging update will be covered in some detail in a Monday morning tutorial to help you learn “What’s Now and What’s Next.”  Mentor Graphics’ Tom Fitzpatrick and Accellera Working Group representative will present in this tutorial.

UVM 1.2 is an active development project of Accellera and has not yet been released so there is no official standard available for download and use yet.  I’ll share standardization details as they happen.

At the same time on Monday, those who are concerned with power aware design and verification can attend the tutorial on the Unified Low Power Format (UPF), or as it is officially called IEEE 1801™-2013.  The tutorial will cover the full spectrum of UPF capabilities and methodology from basic to advanced applications.  So if you are new to UPF and want to learn, this is a great tutorial to attend.  And if you are already an expert, the advanced application of UPF as highlighted by those companies who have adopted UPF make this valuable for you as well.  Mentor Graphics’ Erich Marschner and IEEE 1801 Working Group vice-chair will participate in this tutorial.

UPF is an official IEEE standard.  Have you downloaded your copy yet?  Accellera has worked with the IEEE to make no-charge access to the official standard for you.  You can find the UPF standard here.

In the afternoon, there will be a session on case studies in SystemC.  User and vendor presentations will explore use of this standard.  SystemC offers much in the verification space, not just in technology but learning on how to bridge the RTL world with transaction level modeling world.  Mentor Graphics’ John Stickley will review what we have learned and how you can apply it to your most pressing verification needs.

SystemC is an official IEEE standard.  Have you downloaded your copy yet?  Under the Accellera agreement with the IEEE, you can download SystemC standard here.

There is a lot more to DVCon than just the use of current standards and planning adoption of emerging standards.  I encourage you to check out the whole agenda and join me at DVCon 2014 March 3-6.

Mentor Graphics presentations during the conference include:

  • Tuesday Paper Sessions
    • Amit Srivastava – Stepping Into UPF 2.1 World: Easy Solution to Complex
      Power Estimation
    • Kenneth Bakalar – Interpreting UPF For A Mixed-Signal Design Under Test
    • Gordon Allan – Tried and Tested Speedups for Software-Driven SoC Simulatio
  • Tuesday Poster Sessions
    • Rich Edelman – Debugging Communicating Systems: The Blame Game – Blurring
      the Line Between Performance Analysis and Debug
    • Matthew Balance – Tackling Random Blind Spots with Strategy-Driven Stimulus Generation
    • Gaurav K. Verma – Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology
    • Andreas Meyer – So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
    • Rich Edelman – UVM SchmooVM – I Want My C Tests!
    • Thom Ellis – Are  You Really Confident That You Are Getting the Very Best From Your Verification Resources?
    • Jitesh Bansal – Is Your Power Aware Design Really X-Aware
  • Wednesday Paper Sessions
    • Avidan Efody – Wiretap Your SoC: Why Scattering Verification IPs Throughout Your Design Is A Smart Thing To Do
    • Tom Fitzpatrick – Of Camels and Committees: Standards Should Enable Innovation, Not Strangle It

Mentor Graphics will host its traditional lunch at DVCon on Wednesday on the theme of Accelerating Verification.  And we have lively panel participants for the Tuesday and Wednesday panels.  And, as always, the Exhibit, CEO Keynote and Panels are open to all a no charge – you just have to REGISTER!

I look forward to seeing you there!

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14 March, 2013

IEEE 1801™-2013 Enters Pre-Publish Phase

The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now.  Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013).  The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.

If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).

As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication.  So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet.  So I won’t do that.  If you do need something, the superseded version from 2009 is the only one available at this moment.  I will keep you updated as to when it is published and ready for access to the global design community.

imageMentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled Bringing Verification and Validation under One Umbrella The Evolution of UPF: What’s Next?  (Free access; no registration required; 81KB)

Erich gives a good introduction to the new standard, also known as UPF 2.1.  He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.

Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot.  This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification.  If you are interested to join in with the IEEE 1801 team, visit here for more information.

DVCon UPF Tutorial

The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon.  For those who registered for the conference, the tutorial presentation is still available online.  Unfortunately, the material has not yet been made available to the general public.  If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy.  The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.

As for planning you can do now.  The IEEE 1801 team will host a tutorial at DAC on Sunday.  I will share more information with you on that once the DAC registration site goes live.  Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.

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5 December, 2012

IEEE Std. 1800™-2012 Officially Ratified

The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard.  The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.

What’s New?

The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification.  DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard.  The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics).  You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.

For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance.  As Stu and Tom said in their presentation, “This is BIG!”  If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.

Major work was done to augment the current notion of constraints in SystemVerilog.  In past versions of the standard they were known as hard constraints.  What this meant was all the conditions of the constraints had to be met otherwise there would be an error.  There was no built-in method to relax the need to satisfy the constraints.  Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high.  To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard.  If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard.  Stu and Tom said that “This is also a big enhancement!”

Availability

IEEE 1800™-2012 has only now been approved.  The standard itself is not ready to be published yet.  Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013.  I will  share publication information as it becomes available.  And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.

sva3rdE_cover-wsWhile the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now.  For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more.  You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well.  You can find more information about it on Amazon.com here.

The Story Continues…

There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead.  The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.

Stay tuned!  For now, I encourage you to get informed!

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12 July, 2012

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)

For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency.  Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification goals.  Collecting information on how each tool adds to verification closure and sharing this information for ever larger designs among different tools has become a daunting challenge.

As a precursor to addressing this from a standardization point of view, many companies built their own way of collecting and sharing this information.  Users recognized the need for a standard and market participants responded.  For Mentor Graphics part, we developed and deployed the Unified Coverage Database (UCDB) technology for our verification products several years back.  Via our Questa Vanguard Partnership program, many partners have integrated into the UCDB to help drive further verification efficiency and productivity for mutual customers.

Yet, users were still left with the challenge to use the emerging coverage database technologies from multiple vendors.  Those users sought a solution to this dilemma from Accellera.  After users completed a requirements document that outlined their needs, we at Mentor Graphics noted that our UCDB technology offered a good match.  We offered to seed the standards development with our tested technology, as did other suppliers.  In the end and with extensions from consultations with other suppliers, an updated UCDB Application Programming Interface (API) specification from Mentor Graphics formed the basis from which Accellera created the UCIS API standard.

UCIS CoverpageIn July 2008 we announced the Mentor Graphics technology donation to this Accellera standards effort.  And on the day Accellera announced completion and availability of the standard at DAC 2012, Mentor Graphics was the first to announce product support.

To read more about support of UCIS and how it plays a critical role in verification, you may wish to read the article in the DAC issue of Verification Horizons.

The UCIS co-chair, Dr. Richard Ho from D.E. Shaw Research presented a comprehensive overview of UCIS at DAC.  Dr. Ho along with his co-chair, Dr. Ambar Sarkar of Paradigm Works, Inc. also presented a tutorial at DVCon 2012 titled An Introduction to the Unified Coverage Interoperability Standard.  The tutorial is available online.  Accellera does require registration for the tutorial.  The DVCon 2012 website on the UCIS tutorial goes into detail about what is covered in this 1 hour presentation.

I highly recommend you register and watch the DVCon 2012 tutorial for a good overview of UCIS.  You can also download, for free and without registration, your copy of the Unified Coverage Interoperability Standard here.  It makes a good companion for the tutorial.

What will you do with UCIS?

After reading the standard and watching the tutorial you should have a solid understanding of the importance it plays to reach coverage closure.  You will learn how you can create applications to improve your own verification productivity and efficiency.  Do you want to share the applications you write?  The new UCIS forum and contribution area was created just for this purpose by Accellera.  Please visit the site, register and contribute.

As more users begin to adopt UCIS, I envision this site will provide a good site for users to share applications.

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22 February, 2012

In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this topic at our last face-to-face with the VIP-TSC.  With demand coming from our users, and some positive feedback on our proposal, we have just released UVM Connect, an open-source library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).

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You can find much more information on the UVM Connect page of Verification Academy.

Mentor has always believed that SystemVerilog and SystemC each have their own strengths and that the most productive way to combine them in a system-level environment is to preserve the strengths of each while allowing the free exchange of data between them. Instead of trying to re-implement UVM in SystemC, or to extend SystemC to try and recreate SystemVerilog functional coverage or constrained-random stimulus, UVM Connect provides the framework needed to interoperate between languages. This lets you:

  • Reuse your SystemC architectural models as reference models in UVM verification
  • Reuse your stimulus generation agents in SystemVerilog to verify models in SystemC
  • Have access to a wider array of VIP since you are no longer confined to a single language
  • Utilize and interact with the UVM infrastructure from SystemC, including wait for and control UVM phase transitions, set and get configuration, issue UVM-style reports, set factory type and instance overrides, and more

UVM Connect provides object-based data transfer across the language boundary via TLM1 and TLM2 interfaces, which are natively supported in both languages. It works out-of-the-box with UVM 1.1a and later and lets you use your existing TLM models, regardless of language, in a mixed-language context without modification. In a nutshell, UVM Connect fulfills the principles and purpose of the TLM interface standard, letting you design independent models that communicate without directly referring to each other. The models thus work equally well in both native and mixed-language environments.I encourage you to download the kit and give it a try. In the spirit of “co-op-etition” I also encourage our competitors to qualify the library on their simulators.

In addition to the great material in the UVM/OVM Online Methodology Cookbook on Verification Academy, the kit also includes an HTML User’s Guide, based on extensive, well-documented examples, that includes detailed information on all aspects of the API. Please make sure to stop by the Mentor booth at DVCon and let us know what you think.

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17 February, 2012

It is time to talk about what happens next with UVM

uvm 2The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification.  If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is.  As one of the three organizers of the UVM Tutorial on Monday, I know the conference organizers had to rearrange the room layout to accommodate a greater than expected number of registrant.  It is clear how important the topic of verification is and UVM in particular has become.

It seems to me that DVCon is the right place to discuss what comes next with UVM.  I have three thoughts about UVM that I think merit discussion.

1. UVM needs a period of stability

While the experts at the Accellera Verification IP Technical Subcommittee (VIP-TSC) standardization table (all good people) continue to hone UVM and debate a few more features they need, they have been unable to make significant progress on those features since last DVCon.  The one major item promised beyond OVM, an update to phasing, remains an open topic.  Mentor has suggested in committee that we allow another year to pass and suspend committee action on this.  Maybe the natural market forces would allow several options to surface, be user-tested and then merit consideration by the VIP-TSC.

This is in keeping with Karen Bartleson’s 9th Commandment for Effective Standards: “Start with Donations; Not From Scratch.”  This is what is happening now with Phasing.  The design by committee process is moving slowly.  It is not the slow part that concerns me, however.

Completing the “last” thing has many in the verification community waiting until it is done before they migrate and adopt UVM.  The best thing the committee could do to encourage use is to give the users certainty that UVM will not change in the next 12 months.  At the same time, the committee could commit to take input from users at the end of those 12 months as a guide to what it does next.

2. UVM needs a simple path to first use

Accellera has an approved and published standard, an open-source implementation and embedded UVM User’s Guide.  This is a lot to digest.  And while one may expect the User’s Guide to help, it calls the reader to supplement it with “education, experience and professional judgment.”  It warns that “not all aspects of this guide may be applicable in all circumstances.”

Users should be offered an unambiguous, easy-to-use and understand means to adopt UVM without having to know everything about it before starting to use it.  UVM was not made for just those who have large verification teams and central CAD groups.  Those large teams are the ones who are already using UVM.  The first step to UVM adoption for the rest of the world should not be too high as it currently is.

UVM needs a simple path for fast adoption.

3. UVM needs to bridge the system domain

Accellera System Initiative has come to life from the unification of Accellera and OSCI.  While the vision to bring the two organizations together is without fault, the lack of a publicly visible plan to leverage each others strengths is noted by Gabe Moretti in his recent blog on DVCon when he wrote: “First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.”  His comment was in response to the questions to be asked at DVCon’s Monday lunch about what the new organization should look like.  Gabe certainly thought “the creators of the organization must have some ideas of the focus, mission and goals.”

I certainly do.  In the case of UVM, I think it needs a bridge between the SystemVerilog world in which it was written and the SystemC world of design and modeling.  As teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models has become an imperative.

It is no secret to the Accellera VIP-TSC that Mentor Graphics thinks this is needed.  Our presentation to committee members on a UVM API to facilitate this outlines exactly what we think should be done to address reusable functional models in the system world.  [Accellera requires registration to download the Mentor presentation.  Accellera members can register here.  Guests require VIP-TSC leadership permission and can request it here.]

UVM must grow and bridge the system world.  The Accellera SystemC Verification Working Group (VWG) knows this.  They have a meeting planned at the DATE conference to discuss future evolutions related to SystemC and Verification on 14 March 2012 from 1230-1340 in Conference Room 4 which I plan to attend.  The VWG meeting is open to external participants, not just Accellera members.

Summary

I don’t know what your thoughts about what should happen next with UVM are.  Feel free to share them here if you wish or join me at DVCon or DATE and we can discuss it with the whole community.  Maybe there is hope we can make progress on these three areas in the coming year.

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