Posts Tagged ‘dvcon’
IEEE Approves New Low Power Standard
IEEE 1801™-2013 Enters Pre-Publish Phase
The completion and approval of electronic design automation standards has seemed to be the order of the day for several months now. Added to this list is the IEEE Standards Association (SA) approval of their newly revised low power standard (IEEE 1801™-2013). The IEEE SA’s Review Committee (RevCom) unanimously recommended approval and that was confirmed by the IEEE SA’s Standards Board last week.
If you don’t recognize IEEE 1801, you may also know it as the Unified Power Format (UPF).
As with all the IEEE standards, after approval, they are sent to editorial staff to prepare them for publication. So while you might expect me to suggest you get a copy of the standard, if low power design and verification is important to you, I know you cannot get a copy yet. So I won’t do that. If you do need something, the superseded version from 2009 is the only one available at this moment. I will keep you updated as to when it is published and ready for access to the global design community.
Mentor Graphics’ Erich Marschner and vice chair of the IEEE 1801 working group has published a short article in the DVCon edition of Verification Horizons titled 
The Evolution of UPF: What’s Next? (Free access; no registration required; 81KB)
Erich gives a good introduction to the new standard, also known as UPF 2.1. He describes that UPF 2.1 is an incremental update of UPF 2.0 and not a major revision. He shares that UPF 2.1 contains a large number of small changes, ranging from subtle refinements of existing commands to improve usability, to new concepts that help ensure accurate modeling of power management effects. His article describes some of the more interesting enhancements and refinements that can be found in the new standard.
Erich also shared that the 1801 working group is composed of more than 16 user and vendor companies with even many more participating in the final ballot. This gives us good confidence in the content of this standard and that the group will be ready to tackle the next issues and emerging requirements to further improve low power design and verification. If you are interested to join in with the IEEE 1801 team, visit here for more information.
DVCon UPF Tutorial
The IEEE 1801 leadership hosted a half day tutorial on the new standard in late February at DVCon. For those who registered for the conference, the tutorial presentation is still available online. Unfortunately, the material has not yet been made available to the general public. If you know someone who attended DVCon, and went to the tutorial, you might want to see if you can borrow their copy. The conference did an audio recording and I believe plans are to sync the audio with slides for those who were unable to attend DVCon. Stay tuned for this and I will share information when this becomes available.
As for planning you can do now. The IEEE 1801 team will host a tutorial at DAC on Sunday. I will share more information with you on that once the DAC registration site goes live. Until then, I guess we all have to wait and be patient – and plan our trips to DAC in Austin, TX.
Tags: dvcon, Erich Marschner, IEEE 1801, IEEE-SA, Low Power, RevCom, Standards, upf
IEEE Approves Revised SystemVerilog Standard
IEEE Std. 1800™-2012 Officially Ratified
The IEEE Standards Association (SA) Standards Board (SASB) officially approved the latest SystemVerilog revision, Draft 6, as an IEEE standard. The SASB Review Committee (RevCom) agenda and the SASB agenda include review and formal approval of the latest work by the IEEE Computer Society Design Automation Standards Committee’s (DASC) SystemVerilog Working Group at their December 2012 meeting series.
What’s New?
The new standard has many new features, numerous clarifications and various corrections to improve the standard and keep pace with electronic system design and verification. DVCon 2012 included a session presentation, Keeping Up with Chip – The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” that detailed the standard. The paper was written by Stuart Sutherland (Sutherland HDL, Inc.) and Tom Fitzpatrick (Mentor Graphics). You can find a copy of the paper here at the DVCon 2012 archive and the presentation can be found at Sutherland HDL’s site here.
For users of Mentor Graphics’ Questa Verification Platform, many of the major SystemVerilog 2012 features can be used today, like multiple inheritance. As Stu and Tom said in their presentation, “This is BIG!” If you read their full paper, they discuss some ways this new feature might be useful for a UVM testbench.
Major work was done to augment the current notion of constraints in SystemVerilog. In past versions of the standard they were known as hard constraints. What this meant was all the conditions of the constraints had to be met otherwise there would be an error. There was no built-in method to relax the need to satisfy the constraints. Given the world of multiple constraints is the norm for testbenches today the potential for conflicts between them is high. To alleviate this the SystemVerilog Working Group introduced soft constraints to the standard. If you are interested in the details of what was proposed to be added the standard, you can reference the full proposal here that is included in the standard. Stu and Tom said that “This is also a big enhancement!”
Availability
IEEE 1800™-2012 has only now been approved. The standard itself is not ready to be published yet. Plans are to have it ready to be published before DVCon 2013, which is scheduled for late February 2013. I will share publication information as it becomes available. And, I hope you join me and attend DVCon 2013 where we can plan to celebrate the unveiling of the published standard.
While the IEEE publication will be the authoritative source on the standard, I have pointed to the presentation and paper by Stu Sutherland and Tom Fitzpatrick for information on the new standard that you can reference now. For those who depend on assertions, you will find SystemVerilog-2012 has a major update with enhancements for properties and sequences in the area of immediate assertions, data type support, argument passing, vacuity definitions, global clock resolution and inferred clocking in sequences and much more. You may find the SystemVerilog Assertions Handbook 3rd Edition by Ben Cohen, et. al. to be of value as well. You can find more information about it on Amazon.com here.
The Story Continues…
There is much more to the SystemVerilog-2012 story I will share more of that in the months ahead. The global team of experts who have put this together has been an outstanding collection of individuals ranging from producers and suppliers of electronic design automation software to consumers of said technology who have ensured the language can be used to design and verify the most demanding of electronic systems.
Stay tuned! For now, I encourage you to get informed!
Tags: 1800, Assertions, Ben Cohen, DASC, dvcon, Hard Constraints, IEEE SASB, IEEE-SA, Muttiple Inheritance, RevCom, Soft Constraints, Standards, Stu Sutherland, SystemVerilog, Tom Fitzpatrick, UVM
Verification Standards Take Another Step Forward
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)
For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency. Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification goals. Collecting information on how each tool adds to verification closure and sharing this information for ever larger designs among different tools has become a daunting challenge.
As a precursor to addressing this from a standardization point of view, many companies built their own way of collecting and sharing this information. Users recognized the need for a standard and market participants responded. For Mentor Graphics part, we developed and deployed the Unified Coverage Database (UCDB) technology for our verification products several years back. Via our Questa Vanguard Partnership program, many partners have integrated into the UCDB to help drive further verification efficiency and productivity for mutual customers.
Yet, users were still left with the challenge to use the emerging coverage database technologies from multiple vendors. Those users sought a solution to this dilemma from Accellera. After users completed a requirements document that outlined their needs, we at Mentor Graphics noted that our UCDB technology offered a good match. We offered to seed the standards development with our tested technology, as did other suppliers. In the end and with extensions from consultations with other suppliers, an updated UCDB Application Programming Interface (API) specification from Mentor Graphics formed the basis from which Accellera created the UCIS API standard.
In July 2008 we announced the Mentor Graphics technology donation to this Accellera standards effort. And on the day Accellera announced completion and availability of the standard at DAC 2012, Mentor Graphics was the first to announce product support.
To read more about support of UCIS and how it plays a critical role in verification, you may wish to read the article in the DAC issue of Verification Horizons.
The UCIS co-chair, Dr. Richard Ho from D.E. Shaw Research presented a comprehensive overview of UCIS at DAC. Dr. Ho along with his co-chair, Dr. Ambar Sarkar of Paradigm Works, Inc. also presented a tutorial at DVCon 2012 titled An Introduction to the Unified Coverage Interoperability Standard. The tutorial is available online. Accellera does require registration for the tutorial. The DVCon 2012 website on the UCIS tutorial goes into detail about what is covered in this 1 hour presentation.
I highly recommend you register and watch the DVCon 2012 tutorial for a good overview of UCIS. You can also download, for free and without registration, your copy of the Unified Coverage Interoperability Standard here. It makes a good companion for the tutorial.
What will you do with UCIS?
After reading the standard and watching the tutorial you should have a solid understanding of the importance it plays to reach coverage closure. You will learn how you can create applications to improve your own verification productivity and efficiency. Do you want to share the applications you write? The new UCIS forum and contribution area was created just for this purpose by Accellera. Please visit the site, register and contribute.
As more users begin to adopt UCIS, I envision this site will provide a good site for users to share applications.
Introducing UVM Connect
In his recent post on UVM: Some Thoughts Before DVCon, Dennis outlined some great ideas about what we think should happen next for UVM. His 3rd point, “UVM needs to bridge the system domain,” is particularly relevant given the newly-formed Accellera Systems Initiative. This is actually an area we’ve been contemplating for a while here at Mentor, and as Dennis indicated, we shared our thoughts on this topic at our last face-to-face with the VIP-TSC. With demand coming from our users, and some positive feedback on our proposal, we have just released UVM Connect, an open-source library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog models and components, as well as a UVM Command API for accessing and controlling UVM simulation from SystemC (or C or C++).
You can find much more information on the UVM Connect page of Verification Academy.
Mentor has always believed that SystemVerilog and SystemC each have their own strengths and that the most productive way to combine them in a system-level environment is to preserve the strengths of each while allowing the free exchange of data between them. Instead of trying to re-implement UVM in SystemC, or to extend SystemC to try and recreate SystemVerilog functional coverage or constrained-random stimulus, UVM Connect provides the framework needed to interoperate between languages. This lets you:
- Reuse your SystemC architectural models as reference models in UVM verification
- Reuse your stimulus generation agents in SystemVerilog to verify models in SystemC
- Have access to a wider array of VIP since you are no longer confined to a single language
- Utilize and interact with the UVM infrastructure from SystemC, including wait for and control UVM phase transitions, set and get configuration, issue UVM-style reports, set factory type and instance overrides, and more
UVM Connect provides object-based data transfer across the language boundary via TLM1 and TLM2 interfaces, which are natively supported in both languages. It works out-of-the-box with UVM 1.1a and later and lets you use your existing TLM models, regardless of language, in a mixed-language context without modification. In a nutshell, UVM Connect fulfills the principles and purpose of the TLM interface standard, letting you design independent models that communicate without directly referring to each other. The models thus work equally well in both native and mixed-language environments.I encourage you to download the kit and give it a try. In the spirit of “co-op-etition” I also encourage our competitors to qualify the library on their simulators.
In addition to the great material in the UVM/OVM Online Methodology Cookbook on Verification Academy, the kit also includes an HTML User’s Guide, based on extensive, well-documented examples, that includes detailed information on all aspects of the API. Please make sure to stop by the Mentor booth at DVCon and let us know what you think.
Tags: dvcon, functional verification, systemc, SystemVerilog, UVM, UVM Connect, UVM-1.1, Verification Academy, Verification Methodology
UVM: Some Thoughts Before DVCon
It is time to talk about what happens next with UVM
The Design and Verification Conference (DVCon) has become the premier event to discuss front-end design issues with an emphasis on verification. If one listens to the Conversation Central interview of DVCon leadership it is clear how singularly important DVCon is. As one of the three organizers of the UVM Tutorial on Monday, I know the conference organizers had to rearrange the room layout to accommodate a greater than expected number of registrant. It is clear how important the topic of verification is and UVM in particular has become.
It seems to me that DVCon is the right place to discuss what comes next with UVM. I have three thoughts about UVM that I think merit discussion.
1. UVM needs a period of stability
While the experts at the Accellera Verification IP Technical Subcommittee (VIP-TSC) standardization table (all good people) continue to hone UVM and debate a few more features they need, they have been unable to make significant progress on those features since last DVCon. The one major item promised beyond OVM, an update to phasing, remains an open topic. Mentor has suggested in committee that we allow another year to pass and suspend committee action on this. Maybe the natural market forces would allow several options to surface, be user-tested and then merit consideration by the VIP-TSC.
This is in keeping with Karen Bartleson’s 9th Commandment for Effective Standards: “Start with Donations; Not From Scratch.” This is what is happening now with Phasing. The design by committee process is moving slowly. It is not the slow part that concerns me, however.
Completing the “last” thing has many in the verification community waiting until it is done before they migrate and adopt UVM. The best thing the committee could do to encourage use is to give the users certainty that UVM will not change in the next 12 months. At the same time, the committee could commit to take input from users at the end of those 12 months as a guide to what it does next.
2. UVM needs a simple path to first use
Accellera has an approved and published standard, an open-source implementation and embedded UVM User’s Guide. This is a lot to digest. And while one may expect the User’s Guide to help, it calls the reader to supplement it with “education, experience and professional judgment.” It warns that “not all aspects of this guide may be applicable in all circumstances.”
Users should be offered an unambiguous, easy-to-use and understand means to adopt UVM without having to know everything about it before starting to use it. UVM was not made for just those who have large verification teams and central CAD groups. Those large teams are the ones who are already using UVM. The first step to UVM adoption for the rest of the world should not be too high as it currently is.
UVM needs a simple path for fast adoption.
3. UVM needs to bridge the system domain
Accellera System Initiative has come to life from the unification of Accellera and OSCI. While the vision to bring the two organizations together is without fault, the lack of a publicly visible plan to leverage each others strengths is noted by Gabe Moretti in his recent blog on DVCon when he wrote: “First we build it and then we figure out how to use it has never been a good architectural approach, especially in electronics.” His comment was in response to the questions to be asked at DVCon’s Monday lunch about what the new organization should look like. Gabe certainly thought “the creators of the organization must have some ideas of the focus, mission and goals.”
I certainly do. In the case of UVM, I think it needs a bridge between the SystemVerilog world in which it was written and the SystemC world of design and modeling. As teams move to higher levels of abstraction for system-level architectural exploration and definition, the need for efficient and reusable functional models has become an imperative.
It is no secret to the Accellera VIP-TSC that Mentor Graphics thinks this is needed. Our presentation to committee members on a UVM API to facilitate this outlines exactly what we think should be done to address reusable functional models in the system world. [Accellera requires registration to download the Mentor presentation. Accellera members can register here. Guests require VIP-TSC leadership permission and can request it here.]
UVM must grow and bridge the system world. The Accellera SystemC Verification Working Group (VWG) knows this. They have a meeting planned at the DATE conference to discuss future evolutions related to SystemC and Verification on 14 March 2012 from 1230-1340 in Conference Room 4 which I plan to attend. The VWG meeting is open to external participants, not just Accellera members.
Summary
I don’t know what your thoughts about what should happen next with UVM are. Feel free to share them here if you wish or join me at DVCon or DATE and we can discuss it with the whole community. Maybe there is hope we can make progress on these three areas in the coming year.
Tags: accellera, DATE Conference, dvcon, Standards, systemc, SystemVerilog, UVM
Language Transitions: The Dawning of Age of Aquarius
Wally Rhines DVCon 2011 Keynote Highlights Survey on Verification Languages
OK, maybe it is not the Dawning of the Age of Aquarius, but Wally Rhines’ DVCon 2011 keynote did have a slide titled “SystemVerilog in the Ascendancy.” It is not a word I see or use much. In fact, Google labs’ “Book Ngram Viewer” shows ascendancy has been in decline since around 1825.
It struck me that the title was tending towards the allegoric, if not mostly there, due to it conjuring possible metaphoric, astrological meaning as I began to wonder if planetary positioning was going to be offered on the next slide to bolster SystemVerilog’s ascendancy. I asked myself: Is SystemVerilog’s “ascendancy” a move to a new spiritual level? Has it transcended all other languages to garner greater social importance for design and verification? Is this a greater representation of another trends? Or, perhaps, I was having a flashback to the hippie era. After all, I was hearing in my mind that Hair song with the phrase
When the moon is in the second house
and Jupiter aligned with Mars…
But I was too young in the hippie era of 1967 to have a real flashback. And Wally’s keynote was not some hippie mumbo jumbo. I am also more than certain any of the engineers in the room at DVCon with some physics background could tell us Jupiter aligns with Mars several times a year and the few who might have astrological training (I’ve got to meet them!) could share with us the Moon is in the 7th House for about two hours every day.
Wally’s DVCon 2011 keynote was presented in three parts. The third and last part was on language transitions. When he got to that section he started it by presenting a slide on language transition titled “SystemVerilog in the Ascendancy.”
When Wally last keynoted DVCon in 2008, he presented information that SystemVerilog had been adopted by 24% of survey respondents in 2007. For 2010 that number is 60% and will be 74% in 2011.
When some things go up, others go down. It is no surprise that VERA, which seeded the SystemVerilog standard, has reached a low level of predicted use in 2011 of 3%. Joining this decline is the other language of that day that battled with VERA, “e.” “e” use was at 16% in 2007 and 15% in 2010, but users plan a greater than 25% reduction in use from 2010 to 2011. This is a rather dramatic drop in one year, given it has held so steady from 2007 until now.
Wally also discussed the adoption of languages by geography. SystemVerilog has a strong global presence with particular strength in Asia and India. The “e” language shows focused geographic use in Europe/Israel followed by India. VHDL’s use also has focused geographic use with Europe/Israel leading followed by North America. It is interesting to note some languages have broad global appeal while others have only regional adoption.
Wally also touched on the adoption trends in testbench base-class libraries. Accellera’s UVM shows the largest growth from 2010 use to predicted use in 2011. It should grow from 7% to 27% in the next 12 months. While many projects adopted UVM’s progenitor, OVM, there appears to be no let up in use of OVM either over the next 12 months. In fact, there is some small growth predicted from 42% to 47%. Ongoing projects are the most probable reason that the OVM transition to UVM does not appear to start in the next 12 months. One can postulate that once projects end, teams can consider a transition from OVM to UVM. What it means to Mentor, OVM support is going to be critical for customer success for some time.
What is declining? “Other methodologies,” such as in-house or homebrew drop fastest as the last holdouts adopt the Accellera industry standard. All the other methodologies show small declines in the coming year.
The survey results Wally shared confirm the world is tending towards dominant use of IEEE Std. 1800™ (SystemVerilog) and Accellera UVM™. If the world is aligning on these standards, can we predict the standards wars are over? Looks like another Hair musical flashback:
Then peace will guide the planets.
And love will steer the stars
There are more survey results in Wally’s keynote. I will offer additional commentary in subsequent posts. Maybe you see additional information and meaning in those numbers. If so, I invite you to share your views and opinions of them. And no, you don’t need to dim the lights, turn on the black lights, download and listen to Hair’s Aquarius to divine your view.
Tags: dvcon, OVM, SystemVerilog, UVM, Verification, vhdl, Wally Rhines
DVCon: The Present and the Future
Open SystemC Initiative Tackles the Future
If you have examined the DVCon program, you know that it is a week full of the Universal Verification Methodology (UVM). And I certainly encourage those with an interest in UVM to attend the Monday tutorial and the technical conference the next few days. But you may also want to bring a colleague to attend the SystemC Day activities.
For SystemC Day at DVCon, the morning session is the North American SystemC Users Group (NASCUG) meeting that features a Keynote presentation by industry luminary Jim Hogan.
Jim’s keynote will be on “Navigating the SoC Era.” NASCUG attendance is free, but you need to register to attend.
Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.
In the afternoon, a tutorial on software-driven verification titled Software-Driven Verification Using TLM-2.0 Virtual Platforms will be presented by experts from the OSCI, Accellera and the user community that are using standards-based methodologies in production today. The afternoon tutorial requires registration at the DVCon website. The tutorial is free for conference attendees. A small fee is charged for those who wish to attend this tutorial only. Is software-driven verification in your future? Chances are highly likely it is and I suggest you look at attending this event.
I’ll see you there!
Tags: dvcon, Jim Hogan, nascug, OSCI, systemc, TLM, TLM 2.0, UVM
Accellera Approves New Co-Emulation Standard
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1 Improves Verification Productivity
The Accellera Interface Technical Subcommittee (ITC) completed version 2.1 of the standard used to interface software and hardware-based verification technology. With SCE-MI, models can be developed for simulation to run in an emulation environment and visa versa.
The major addition to SCE-MI 2.1 is support for a subset of the IEEE Std 1800™ (SystemVerilog) Direct Programming Interface (DPI) that permits a streaming, variable length messaging system to be built on top of it to reduce the number of synchronizations that would otherwise be required by alternate methods.
The standard is available here free of charge from Accellera.
What does this mean to the verification professional?
Dr. van der Schoot has published four sessions on Acceleration of SystemVerilog Testbenches with Co-Emulation at the Verification Academy that give an excellent overview of the benefits of this technology. Dr. van der Schoot shows how the prevalent verification methodologies (OVM and UVM) can see dramatic improvements when this technology is applied.
| Verification Academy Session | |
| Introduction to Hardware Assisted Testbench Acceleration | |
| Testbench Acceleration Depicted | |
| Modeling for Acceleration | |
| Testbench Acceleration Flow |
How is Co-Emulation Used in Practice?
EDSFair 2011
The technology is also deployed in a working verification flow by Mentor Graphics. At EDSFair 2011 in Japan this week, users could see Co-Emulation in action.
This technology has allowed verification runs using the prevalent methodologies, OVM and UVM, to operate easily up to 400x faster when emulation technology is used to accelerate verification as previously announced.
While EDSFair is over, verification professionals will have another opportunity to see this technology in action at the DVCon 2011 exhibition. Dr. van der Schoot also has a paper at DVCon, Off To The Races With Your Accelerated SystemVerilog Testbench, that he will present to explore details on how this standards technology is being applied in real life.
Tags: accellera, dvcon, EDSFair, OVM, SCE-MI, Standards, SystemVerilog, UVM
Easier UVM Testbench Construction – UVM Sequence Layering
UVM Layering Package updated from OVM Layering Package
In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM. This package has been updated and tested to work with UVM 1.0 EA and is ready for download.
As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementations. The package also provides the DVCon paper and presentation that describes it in more detail in case you did not attend DVCon.
Users have found layered sequences can make verification life easier as sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in. The package is a companion to the UVM 2.0 Register Package that was also updated from OVM to UVM.
Tags: dvcon, OVM, register package, sequence, sequencers, testbench, UVM
New OVM Sequence Layering Package – For Easier Tests
Download Now
A new OVM Layering Package that provides a means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementation is available for download.
The DVCon 2010 paper on this topic, You Are In a Maze of Twisty Little Sequences, All Alike – or Layering Sequences for Stimulus Abstraction, is also part of the download kit. The paper demonstrates building layered stimulus using OVM sequences and sequencers. Virtual sequences and virtual sequencers are highlighted by building a small collection of examples that can be used in layered stimulus verification environments. The main contribution of this paper is a new layering component that performs the standard layering task while minimizing user programming without requiring exotic connectivity, extended components or the use of the factory.
Using layered sequences can make your verification life easier, since sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in. To learn more, download the kit. You will also find a presentation in the kit and how to use it with the OVM 2.0 Register Package mentioned in my last blog.
Tags: dvcon, layered sequences, OVM, register package
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
Latest Posts
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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