Posts Tagged ‘dac’
Live & In-Person at DAC 2012!
Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year. Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.
The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design. The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well. A whole host of educational modules and seminars can also be found there too.
If you know about the Verification Academy, you know all about the content mentioned above and that there is much more to be found there. For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum. (Flash is required to watch Harry discuss Verification Academy with Luke.)
The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends. Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations. While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations. Verification Academy “Total Access” members now have access to many of the presentations.
Thales Alenia Space
Test & Verification Solutions
Total Access members can also download all the presentations in a .zip file. Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.
Tags: ABV, ACE, ams, ARM, Assertion-Based Verification, Coverage Closure, dac, Doulos, formal, IEEE, iTBA, Low Power, OVM, SystemVerilog, Tech Design Forum, Thales, upf, UVM, UVM Express, Verification Academy, Verification Trends
Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)
For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency. Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification goals. Collecting information on how each tool adds to verification closure and sharing this information for ever larger designs among different tools has become a daunting challenge.
As a precursor to addressing this from a standardization point of view, many companies built their own way of collecting and sharing this information. Users recognized the need for a standard and market participants responded. For Mentor Graphics part, we developed and deployed the Unified Coverage Database (UCDB) technology for our verification products several years back. Via our Questa Vanguard Partnership program, many partners have integrated into the UCDB to help drive further verification efficiency and productivity for mutual customers.
Yet, users were still left with the challenge to use the emerging coverage database technologies from multiple vendors. Those users sought a solution to this dilemma from Accellera. After users completed a requirements document that outlined their needs, we at Mentor Graphics noted that our UCDB technology offered a good match. We offered to seed the standards development with our tested technology, as did other suppliers. In the end and with extensions from consultations with other suppliers, an updated UCDB Application Programming Interface (API) specification from Mentor Graphics formed the basis from which Accellera created the UCIS API standard.
In July 2008 we announced the Mentor Graphics technology donation to this Accellera standards effort. And on the day Accellera announced completion and availability of the standard at DAC 2012, Mentor Graphics was the first to announce product support.
The UCIS co-chair, Dr. Richard Ho from D.E. Shaw Research presented a comprehensive overview of UCIS at DAC. Dr. Ho along with his co-chair, Dr. Ambar Sarkar of Paradigm Works, Inc. also presented a tutorial at DVCon 2012 titled An Introduction to the Unified Coverage Interoperability Standard. The tutorial is available online. Accellera does require registration for the tutorial. The DVCon 2012 website on the UCIS tutorial goes into detail about what is covered in this 1 hour presentation.
I highly recommend you register and watch the DVCon 2012 tutorial for a good overview of UCIS. You can also download, for free and without registration, your copy of the Unified Coverage Interoperability Standard here. It makes a good companion for the tutorial.
What will you do with UCIS?
After reading the standard and watching the tutorial you should have a solid understanding of the importance it plays to reach coverage closure. You will learn how you can create applications to improve your own verification productivity and efficiency. Do you want to share the applications you write? The new UCIS forum and contribution area was created just for this purpose by Accellera. Please visit the site, register and contribute.
As more users begin to adopt UCIS, I envision this site will provide a good site for users to share applications.
Where might our paths cross?
It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC). If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.
Saturday and Sunday are busy with an Accellera Systems Initiative board meeting. Split across two days, Accellera board members will meet to conduct traditional business and do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year. Intel has graciously granted space in their San Francisco offices, so I won’t be around the Moscone Center during the pre-conference setup phase. (By the way, Thank you Intel!)
After we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception (registration required) at 6:00pm (San Francisco Marriott, Salon 7) and Gary Smith’s “Sunday Night at DAC” at 7:00pm (San Francisco Marriott, Salon 6).
During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings. And just in case you may note that most of my evenings are not scheduled, they are with customer activities.
When the show floor is open, you will find me most of the time at the Verification Academy Booth #1514. I will join Mentor’s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry’s research results, updates on important verification standards from Mentor’s perspective and more. You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth. (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)
Verification Academy DAC Schedule
|Monday, June 4th||Tuesday, June 5th||Wednesday, June 6th|
10:00 – Simulation and Formal Assertion-Based Verification
Harry Foster, Mentor Graphics
9:30 – Using the UVM Register Layer
10:00 – Bringing UVM to Life
11:00 – Bringing UVM to Life
10:00 – Generating Coverage Models and Achieving Coverage Closure
11:00 – Resistance is Futile: Learning to love UVM!
2:00 – Verification of Low Power SoCs with IEEE UPF
2:00 – Bringing UVM to Life
2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics
3:00 - Evolving Trends in Functional Verification
3:00 - Evolving Trends in Functional Verification
3:00 – UVM Express
4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
4:00 - Evolving Trends in Functional Verification
5:00 - Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
5:00 – Meet the Verification Experts Cocktail Reception
Accellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS). The lunch is free and seating is limited and registration is required.
Hosted Luncheon and Technical Presentation
Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard
Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee
Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.
This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.
SystemC User Group Meeting
North American SystemC User’s Group Meeting
Wednesday, June 6, 2:00-6:00pm
Moscone Center, Room 262
Register Now >
This event is open to all DAC attendees. Seating is limited!
The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agendafor the event has a lot offer user group attendees.
Mentor’s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog. Adam’s presentation is scheduled to start at 3:00pm.
System Standards Worlds Initiate Unification
Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization. You can read their joint press release here.
While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs. At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit? Where are they going?,” technical members of the two communities gathered to ponder answers to those questions. At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.
Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community. A lot has transpired since then. Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively. And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.
In this evolution, it became clear to me that each organization was “completing” the other. OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™). As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.
In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.
What do you think about the unification?
The standards developing organizations defining and updating front-end EDA standards will be at DAC in force. And from the looks of if, they are getting an early start to DAC with updates on IEEE, Accellera and OSCI standards at Sunday workshops. The Sunday workshops may be of particular interest to verification engineers interested in UVM and systems designers interested in SystemC AMS.
Following the workshops, there will be a half-day meeting of the North American SystemC Users Group on Monday where users will share their SystemC experiences. The following morning, Accellera will host its annual DAC breakfast where the UVM users will meet to share their experiences. A lively conversation is expected.
Sunday – June 5, 2011
Time: 10:00 AM — 1:00 PM
Location: San Diego Convention Center Room 33A
Summary: The Accellera Verification IP Technical Subcommittee (VIP-TSC), building on over two years of work by verification experts from around the world, released Universal Verification Methodology (UVM) in February 2011. This workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
GET MORE DETAILS
Registration: This is an official DAC sponsored event and DAC registration required.
Time: 10:00 AM — 6:00 PM
Location: San Diego Convention Center Room 33B
Summary: Today’s embedded systems interact more and more tightly with the analog physical environment; where digital HW/SW subsystems become functionally interwoven with analog/mixed-signal (AMS) blocks such as RF interfaces, power electronics, or sensors and actuators. Examples are software defined radios, sensor networks, automotive applications, or systems for image sensing. This requires new means to model and simulate the interaction between AMS subsystems and HW/SW subsystems at functional and architecture levels. Especially for this purpose, the SystemC language standard has been extended with powerful AMS capabilities to tackle the challenges in heterogeneous electronic system-level (ESL) design. You will get a good working knowledge of SystemC AMS by attending the workshop.
GET MORE DETAILS
Registration: This is an official DAC sponsored event and DAC registration required.
Monday – June 6, 2011
North American SystemC Users Group Meeting
Time: 8:30 AM – 12:00 PM
Location: OMNI Hotel
Room Salon AB
675 Laurel Street
San Diego, CA 92101
Summary: The North American SystemC Users Group explores the newest advancements in sustainable and flexible solutions for system-level design using SystemC.
GET MORE DETAILS
Registration: This event is free and open to all registered DAC attendees. Click here to reserve your seat
Tuesday – June 7, 2011
Time: 7:00 AM – 8:30 AM
Location: San Diego Convention Center Room 25AB
Summary: With the introduction of Accellera’s Universal Verification Methodology (UVM) user interest and adoption has been rapidly growing. You are invited to join us and share the experience with fellow users. During the breakfast, you will hear from real users who have migrated to, and/or applied, the UVM for the first time. Accellera Verification IP Technical Subcommittee (VIP-TSC) participants will provide their insights on UVM. We invite you to take part in the open discussion to foster greater adoption of this important verification standard.
GET MORE DETAILS
Registration: This event is free open to all registered DAC attendees. Click here to reserve your seat
After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup called 0-In Design Automation. I firmly believe that static verification can complement dynamic simulation. Static verification uses synthesis and formal technologies to find bugs in the design. It does not rely on simulation stimulus. You do not need to exercise the bugs, propagate the results, and check the outputs to detect them.
Static verification includes RTL lint, static checks, formal checks, automated and assertion-based formal property checking. To read more on static verification, you can take a look at my white paper: Getting Started With Static Verification. If you are interested in formal methods, you can take a look at Harry Foster’s white paper: Why Now for Formal Property Checking. Both can be found in the Knowledge Center of DAC.com.
In the future, we are going to talk about individual static verification technologies and its application in areas such as RTL verification, clock domain crossing verification, low power verification, timing constraint verification, etc. Your feedback and comments are most welcome.
Visit Booth 1350 – The hub of OVM/UVM Activity at DAC
The OVM World booth at the Design Automation Conference (#1350) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from
4:30 p.m. to 6:00 p.m.
The Open Verification Methodology (OVM) is the industry’s open and interoperable solution, guaranteed to run on multiple simulators, supporting multiple design languages, and is the basis for the Accellera UVM standard. The OVM enables scalability and reuse, fostering a vibrant verification ecosystem. OVMworld.org is the one-stop site for the OVM open-source library, documentation, and community contributions.
Featured half-hour presentations at the booth will include those listed below. In addition to the presenting company and presentation title, full presentation abstracts can be found at http://www.ovmworld.org/tradeshows.php.
Monday (June 14th)
OVM-based Verification Methodology VIP permits Silicon Interfaces to release Gigabit Ethernet MAC to industry with zero defect guarantee
VIP Technical Subcommittee Update
Simulation-Based FlexRay™ Conformance Testing – an OVM success story
OVM Support in DVT
|Mentor Graphics & Cadence
OVM and UVM Update
SuperSpeed your USB 3.0 Verification with OVM based nSys Verification IP
OVM/UVM from a single spec
Tuesday (June 15th)
OVM/UVM for FPGAs: The End of Burn and Churn?
Virtual Interface Techniques for OVM
Beyond a common base class library: reduce work by reusing OVM agents on common interfaces
The Communication and Customization Mechanisms in OVM and UVM
|Mentor Graphics & Cadence
OVM and UVM Update
|Methodology Experts Discussion|
|Cocktail Networking Event|
Wednesday (June 16th)
Denali’s PureSpec: OVM-compatible VIP for bus and I/O protocols
Successful OVM deployment
Agile methods for OVM
ESL to RTL Verification – Progressive Refinement and Reuse Paradigm.
TSMC Open Innovation Platform.
|3 p.m.||Mentor Graphics & Cadence
OVM and UVM Update
Automatic Generation of OVM Registers
At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion. While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users. UVM is at is simplest, just OVM. If you know OVM; you know UVM.
While OVM and UVM are much alike, what is uncharted territory is how users will respond to and adopt UVM. Unique to UVM is public support by the Big-3 EDA companies. Other than that, nothing is really new for an OVM user.
What will be new next year at DAC 2011? The Accellera panel abstract invites you to the breakfast to listen to a panel of expert verification engineers and methodology developers debate what they would like to see in UVM by DAC 2011. And it encourages attendees to be vocal as well to share their views about what they would like to see by DAC 2011.
Tuesday, June 15, 2010
7:30 am – 9:00 a.m.
Anaheim Convention Center Room 203B
Moderator: Gabe Moretti, Gabe on EDA
Sharon Rosenberg, Cadence
Hillel Miller, Freescale
Mohamed Elmalaki, Intel
Tom Fitzpatrick, Mentor Graphics
Janick Bergeron, Synopsys
Stacey Secatch, Xilinx
On a light note: In prior DACs, the Accellera breakfast always seemed to follow the Denali party. As you can imagine, a 7:30 a.m. start (or end to the night before) was always a challenge. While many might have looked forward to break with tradition this year, we were informed by Denali that a second party (actually the first party if taken in chronological order) was being added. For those who will register for a Denali party ticket, the Accellera breakfast will be a full breakfast to soak up any sins of the night before offered with plenty of coffee to wake you up.
I’ll see you at the Accellera breakfast and at the Denali party!
You Are Invited – Register Now!
(seating is limited)
Sunday, June 13
2:30pm – 6:00pm
Anaheim Hilton, California Ballroom A
On the Sunday before DAC, the North American SystemC User’s Group (NASCUG) will hold NASCUG XIII and they invites all DAC attendees to this special event featuring the latest advancements in sustainable and flexible solutions for ESL design.
As a global sponsor of OSCI events, Mentor encourages the SystemC community to meet at this event to learn more about SystemC advances and applications.
Technical presentations on architectural modeling, transaction-level modeling and analog/mixed-signal design using SystemC™ will be featured. You will be able to interact with colleagues and industry experts, and find out first-hand how system-level design with SystemC has become a nuts-and-bolts part of the designer’s toolbox.
|2:30pm – 3:00pm||Registration|
|3:00pm – 3:10pm||Welcome & Agenda|
|3:10pm – 3:30pm||OSCI and Technical Working Group Update
Eric Lish, OSCI Chairman
|3:30pm – 5:50pm||Technical Presentations:|
|5:50pm – 6:00pm||Meeting Close and Prize Drawing|
6:00pm – 7:30pm
Anaheim Hilton, Pacific Ballroom
The DAC Executive Committee and the EDA Consortium invite the NASCUG XIII participants to attend their annual DAC Kick-Off Reception at this year’s conference in Anaheim, California. The reception begins just as the user group meeting concludes. Both events are in the Anaheim Hilton and located close to each other. Register Now to attend the Sunday reception.
About Verification Horizons BLOG
This blog will provide an online forum to provide weekly updates on concepts, values, standards, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. We're looking forward to your comments and suggestions on the posts to make this a useful tool.
- Part 1: The 2012 Wilson Research Group Functional Verification Study
- What’s the deal with those wire’s and reg’s in Verilog
- Getting AMP’ed Up on the IEEE Low-Power Standard
- Prologue: The 2012 Wilson Research Group Functional Verification Study
- Even More UVM Debug in Questa 10.2
- IEEE Approves New Low Power Standard
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- Intelligent Testbench Automation Delivers 10X to 100X Faster Functional Verification
- Part 9: The 2010 Wilson Research Group Functional Verification Study
- Verification Horizons DAC Issue Now Available Online
- Accellera & OSCI Unite
- The IEEE’s Most Popular EDA Standards
- UVM Register Kit Available for OVM 2.1.2
- May 2011 (2)
- April 2011 (7)
- User-2-User’s Functional Verification Track
- Part 7: The 2010 Wilson Research Group Functional Verification Study
- Part 6: The 2010 Wilson Research Group Functional Verification Study
- SystemC Day 2011 Videos Available Now
- Part 5: The 2010 Wilson Research Group Functional Verification Study
- Part 4: The 2010 Wilson Research Group Functional Verification Study
- Part 3: The 2010 Wilson Research Group Functional Verification Study
- March 2011 (5)
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- The reports of OVM’s death are greatly exaggerated (with apologies to Mark Twain)
- New Verification Academy Advanced OVM (&UVM) Module
- OVM/UVM @DAC: The Dog That Didn’t Bark
- DAC: Day 1; An Ode to an Old Friend
- UVM: Joint Statement Issued by Mentor, Cadence & Synopsys
- Static Verification
- OVM/UVM at DAC 2010
- DAC Panel: Bridging Pre-Silicon Verification and Post-Silicon Validation
- Accellera’s DAC Breakfast & Panel Discussion
- May 2010 (9)
- Easier UVM Testbench Construction – UVM Sequence Layering
- North American SystemC User Group (NASCUG) Meeting at DAC
- An Extension to UVM: The UVM Container
- UVM Register Package 2.0 Available for Download
- Accellera’s OVM: Omnimodus Verification Methodology
- High-Level Design Validation and Test (HLDVT) 2010
- New OVM Sequence Layering Package – For Easier Tests
- OVM 2.0 Register Package Released
- OVM Extensions for Testbench Reuse
- April 2010 (6)
- SystemC Day Videos from DVCon Available Now
- On Committees and Motivations
- The Final Signatures (the meeting during the meeting)
- UVM Adoption: Go Native-UVM or use OVM Compatibility Kit?
- UVM-EA (Early Adopter) Starter Kit Available for Download
- Accellera Adopts OVM 2.1.1 for its Universal Verification Methodology (UVM)
- March 2010 (4)
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- December 2009 (15)
- A Cliffhanger ABV Seminar, Jan 19, Santa Clara, CA
- Truth in Labeling: VMM2.0
- IEEE Std. 1800™-2009 (SystemVerilog) Ready for Purchase & Download
- December Verification Horizons Issue Out
- Evolution is a tinkerer
- It Is Better to Give than It Is to Receive
- Zombie Alert! (Can the CEDA DTC “User Voice” Be Heard When They Won’t Let You Listen)
- DVCon is Just Around the Corner
- The “Standards Corner” Becomes a Blog
- I Am Honored to Honor
- IEEE Standards Association Awards Ceremony
- ABV and being from Missouri…
- Time hogs, blogs, and evolving underdogs…
- Full House – and this is no gamble!
- Welcome to the Verification Horizons Blog!
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