Posts Tagged ‘dac’

31 May, 2013

Hi Everyone,

Just wanted to let you know that we just posted the PDF of the latest, Texas-Sized, DAC edition of Verification Horizons on the Verification Academy. In addition to my Editor’s Note, in which I liken what we do as verification engineers to my set-building experiences in local theatre groups, and brag about my daughter, you’ll find these fine articles:

We’ll have plenty of copies available at DAC. Be sure to stop by the Mentor booth (2046) or the Verification Academy booth (1215) to pick one up, or just to say “Howdy.”

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29 May, 2013

Download the standard now – at no charge

The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard, officially called IEEE Standard for Design and Verification of Low-Power Integrated Circuits, many refer to it as IEEE 1801 or UPF for the Unified Power Format as this was the name Accellera had given it prior to transferring standardization responsibility and ongoing maintenance and enhancement to the IEEE.  Further – Courtesy of Accellera – the standard is available for download without charge directly from the IEEE.

1801-2013_Page_001The latest update to IEEE 1801 is ready for download.  It joins other EDA standards, like SystemVerilog and SystemC in the IEEE Get™ program that grants public access to view and download current individual standards at no charge as a PDF.  (If you wish to have an older, superseded and withdrawn version of the standard or if you wish to have a printed copy or have it in a CD-ROM format, you can purchase older and alternate formats from IEEE for a fee.)

The official IEEE announcement on the standard’s publication can be found here.  And the official Accellera announcement that it has partnered with the IEEE-SA to offer the standard to all at no charge can be found here.  This revision of the standard had one of the largest number of IEEE-SA entity members of any corporate standards program.  Participation from the IEEE-SA global community of entity participants ensures the needs of a broad set of companies are captured to support this worldwide standard.

Just In Time For DAC

50th DACDAC 2013 has many events that will allow you to learn more about the new standard and how to use it to your maximum benefit.  And for those who cannot attend DAC, visit the Verification Academy, you will find the Low Power sessions cover the new standard as well. [Registration required; restrictions apply.]

Sunday
Topic: DAC Workshop:  Low-Power Design with the New IEEE 1801-2013 Standard
Date: 2 June 2013
Time: 1:00 p.m. – 5:00 p.m.
Location: Convention Center: Room 18C
Registration: Official DAC Workshop registration required ($). For more information and to register, click here.


Monday
Accellera Breakfast & Town Hall Meeting
Topic: The Standard for Low Power Design and Verification is here!  What’s next?
Date: 3 June 2013
Time: 7:00 a.m. – 8:45 a.m.
Location: Convention Center: Ballroom D
Registration: This is a free Accellera event, but registration is required.  Form more information click here and to register, click here.


Monday
Verification Academy
Topic: “Low Power Monday”
Date: 3 June 2013
Time: 11:00 a.m. – 6:00 p.m.
Location: Tradeshow Floor – Booth 1215
Registration: The DAC Tradeshow floor is open to all DAC registrants. Visit www.dac.com to register.

The Verification Academy is open to all DAC registrants.  There are no restrictions and we invite everyone to visit booth 1215 for Low Power sessions that may be of interest to you on Monday.  To help judge attendance, please feel free to pre-register at here.  I look forward to see you there as you will find me here most of the time Monday-Wednesday.

Time Description Presenter
11:00 a.m. – 12:00 p.m. Low Power Verification Tim Jordon
MicroChip Technlogy
1:00 p.m. – 2:00 p.m What’s New in UPF 2.1? Erich Marschner
IEEE 1801 Vice-chair
Mentor Graphics
2:00 p.m. – 3:00 p.m. UPF-Based Verification for Cypress PSOC Ellie Burns
Mentor Graphics
4:00 p.m. – 5:00 p.m. Optimizing for Power Efficient Design Abhishek Ranjan
Calypto
5:00 p.m. – 6:00 p.m. IEEE 1801 UPF Commands and Methodology John Biggs
ARM
IEEE 1801 Chair

If you are coming to DAC and participating in the DAC Low Power Workshop on Sunday, or in other events, download your person copy of the new IEEE 1800-2013 standard today.  The PDF form allows you to take it with you and read it using your favorite e-reader or i-device.  Let’s me know what you think of the standard.  And – See you at DAC!

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20 July, 2012

Live & In-Person at DAC 2012!

DAC 2012 4Verification Academy, the brain child of Harry Foster, Chief Verification Scientist at Mentor Graphics, was live from the Design Automation Conference tradeshow floor this year.  Harry is pictured to the right giving an update on his popular verification survey from the DAC tradeshow floor.

The Verification Academy, predominantly a web-based resource is a popular site for verification information with more than 11,000 registered members for forum access on topics ranging from OVM/UVM, SystemVerilog and Analog/Mixed-Signal design.  The popular OVM/UVM Cookbook, which used to be available as a print edition, is now a live online resource there as well.  A whole host of educational modules and seminars can also be found there too.

If you know about the Verification Academy, you know all about  the content mentioned above and that there is much more to be found there.  For those who don’t know as much about it, Harry took a break from the being at the Verification Academy booth at DAC to discuss the Verification Academy with Luke Collins, Technology Journalist, Tech Design Forum.  (Flash is required to watch Harry discuss Verification Academy with Luke.)

The Verification Academy at DAC was a great venue to connect in person with other Verification Academy users to discuss standards, methodologies, flows and other industry trends.  Each hour there were short presentations by Verification Academy members that proved to be a popular way to start some interesting conversations.  While we realize not all Verification Academy members were able to attend DAC in person, we know many have expressed an interest to some of the presentations.  Verification Academy “Total Access” members now have access to many of the presentations.

 

ARM

 

Doulos

 

Thales Alenia Space

 

Test & Verification Solutions

 

Willamette HDL

 

Sunburst Design

 

Mentor Graphics

Total Access members can also download all the presentations in a .zip file.  Happy reading to all those who were unable to visit us at DAC and thank you to all who were able to stop by and visit.

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12 July, 2012

Accellera Ushers in Unified Coverage Interoperability Standard (UCIS)

For the past few months, Accellera’s Unified Coverage Interoperability Standards working group has completed and released a new standard that is destined to help boost verification productivity and efficiency.  Verification teams use a variety of verification technologies, many times from different suppliers, to achieve their verification goals.  Collecting information on how each tool adds to verification closure and sharing this information for ever larger designs among different tools has become a daunting challenge.

As a precursor to addressing this from a standardization point of view, many companies built their own way of collecting and sharing this information.  Users recognized the need for a standard and market participants responded.  For Mentor Graphics part, we developed and deployed the Unified Coverage Database (UCDB) technology for our verification products several years back.  Via our Questa Vanguard Partnership program, many partners have integrated into the UCDB to help drive further verification efficiency and productivity for mutual customers.

Yet, users were still left with the challenge to use the emerging coverage database technologies from multiple vendors.  Those users sought a solution to this dilemma from Accellera.  After users completed a requirements document that outlined their needs, we at Mentor Graphics noted that our UCDB technology offered a good match.  We offered to seed the standards development with our tested technology, as did other suppliers.  In the end and with extensions from consultations with other suppliers, an updated UCDB Application Programming Interface (API) specification from Mentor Graphics formed the basis from which Accellera created the UCIS API standard.

UCIS CoverpageIn July 2008 we announced the Mentor Graphics technology donation to this Accellera standards effort.  And on the day Accellera announced completion and availability of the standard at DAC 2012, Mentor Graphics was the first to announce product support.

To read more about support of UCIS and how it plays a critical role in verification, you may wish to read the article in the DAC issue of Verification Horizons.

The UCIS co-chair, Dr. Richard Ho from D.E. Shaw Research presented a comprehensive overview of UCIS at DAC.  Dr. Ho along with his co-chair, Dr. Ambar Sarkar of Paradigm Works, Inc. also presented a tutorial at DVCon 2012 titled An Introduction to the Unified Coverage Interoperability Standard.  The tutorial is available online.  Accellera does require registration for the tutorial.  The DVCon 2012 website on the UCIS tutorial goes into detail about what is covered in this 1 hour presentation.

I highly recommend you register and watch the DVCon 2012 tutorial for a good overview of UCIS.  You can also download, for free and without registration, your copy of the Unified Coverage Interoperability Standard here.  It makes a good companion for the tutorial.

What will you do with UCIS?

After reading the standard and watching the tutorial you should have a solid understanding of the importance it plays to reach coverage closure.  You will learn how you can create applications to improve your own verification productivity and efficiency.  Do you want to share the applications you write?  The new UCIS forum and contribution area was created just for this purpose by Accellera.  Please visit the site, register and contribute.

As more users begin to adopt UCIS, I envision this site will provide a good site for users to share applications.

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30 May, 2012

Where might our paths cross?

It is always challenge to fit all the needed visits in during the Design Automation Conference (DAC).  If you happen to like some of the same events I attend, then the chances are good our paths might cross in public.

Saturday and Sunday are busy with an Accellera Systems Initiative board meeting.  Split across two days, Accellera board members will meet to conduct traditional business and  do some strategic planning in which each board member outlines what they aspire the goals and objectives for the group should be in the coming year.  Intel has graciously granted space in their San Francisco offices, so I won’t be around the Moscone Center during the pre-conference setup phase.  (By the way, Thank you Intel!)
After we close the Accellera board meeting on Sunday, I plan to attend the pre-DAC events on Sunday that include the EDAC reception (registration required) at 6:00pm  (San Francisco Marriott, Salon 7) and Gary Smith’s “Sunday Night at DAC” at 7:00pm (San Francisco Marriott, Salon 6).

During the conference I will spend most of my time at the Mentor Graphics Verification Academy Booth  #1514 and on Wednesday split my time between there and the Accellera Systems Imitative meetings.  And just in case you may note that most of my evenings are not scheduled, they are with customer activities.

MentorGraphics-LogoWhen the show floor is open, you will find me most of the time at the Verification Academy Booth #1514.  I will join Mentor’s Harry Foster there were user and partner presentations will be done on UVM applications, updates on Harry’s research results, updates on important verification standards from Mentor’s perspective and more.  You are invited to join other verification experts for the Tuesday evening cocktail reception at the Verification Academy Booth.  (And the cocktail hour may be just the thing that tis needed before the annual DAC Birds-Of-A-Feather meetings begin to help the conversations start.)

Verification Academy DAC Schedule

Monday, June 4th Tuesday, June 5th Wednesday, June 6th
10:00 – Simulation and Formal Assertion-Based Verification
Harry Foster, Mentor Graphics
9:30 – Using the UVM Register Layer
John Aynsley, Doulos
10:00 – Bringing UVM to Life
Ellie Burns, Mentor Graphics
11:00 – Bringing UVM to Life
Ellie Burns, Mentor Graphics
10:00 – Generating Coverage Models and Achieving Coverage Closure
Mark Olen, Mentor Graphics
11:00 – Resistance is Futile: Learning to love UVM!
Mike Bartley, Test & Verification Solutions
2:00 – Verification of Low Power SoCs with IEEE UPF
Stephen Bailey, Mentor Graphics
2:00 – Bringing UVM to Life
Ellie Burns, Mentor Graphics
2:00 – Automating Assertion Based Verification with NextOp and Mentor Graphics
Yunshan Zhu, NextOp
3:00 – Evolving Trends in Functional Verification
Harry Foster, Mentor Graphics
3:00 – Evolving Trends in Functional Verification
Harry Foster, Mentor Graphics
3:00 – UVM Express
Mike Baird, Willamette HDL, Inc.
4:00 – An Introduction to AMBA 4 AXI Coherency Extensions (ACE) and Verification Challenges
Paul Martin, ARM
4:00 – Evolving Trends in Functional Verification
Harry Foster, Mentor Graphics
5:00 – Using Rules-Based Integration to Develop a SoC-Level UVM Verification Environment
David Murray, Duolog
5:00 – Meet the Verification Experts Cocktail Reception

Accellera logo_color_200x111 - CopyAccellera Systems Initiative will host a set of meetings on Wednesday starting with a luncheon to roll out the Unified Coverage Operability Standard (UCIS).  The lunch is free and seating is limited and registration is required.

Hosted Luncheon and Technical Presentation

Accellera Systems Initiative Rolls Out the Unified Coverage Interoperability Standard


Speaker: Dr. Richard Ho, Co-Chair of the UCIS Technical Subcommittee

Wednesday, June 6, 12:00-1:30pm
Moscone Center, Room 250
Register Now >
This luncheon is open to all DAC attendees. Seating is limited! You must pre-register for this event.

Coverage metrics are critical to measuring and guiding design verification. As designs have grown, increasingly advanced verification technologies, methods and additional metrics have been designed to form a fuller coverage model. There is currently no single metric that consistently and globally tells engineers the exact status of verification. But one step in the right direction is to bring all types of coverage metrics into a single database that can be accessed in an industry standard way. The UCIS facilitates the creation of a unified coverage database that allows for interoperability of coverage data across multiple tools from multiple vendors.

This presentation, intended for verification managers and tool developers alike, provides an introduction to and overview of the UCIS and how users plan to utilize it to enhance their verification flows. We provide a survey of many of the commonly-used coverage metrics and how they are modeled in the UCIS. The information that users will be able to access through the UCIS will allow them to write their own applications to analyze, grade, merge and report coverage from one or more databases from one or more tool vendors. We will also discuss the XML-based interchange format of UCIS, which provides a path to exchange coverage databases without requiring a common code library between tools and vendors.

SystemC User Group Meeting

NASCUG XVIII

North American SystemC User’s Group Meeting
Wednesday, June 6, 2:00-6:00pm
Moscone Center, Room 262
Register Now >
This event is open to all DAC attendees. Seating is limited!

The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC experiences and knowledge among industry, research and universities. The agendafor the event has a lot offer user group attendees.

Mentor’s Adam Erickson will present An Open-Source, Standards-Based Library for Achieving Interoperability Between TLM Models in SystemC and SystemVerilog.  Adam’s presentation is scheduled to start at 3:00pm.

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21 June, 2011

System Standards Worlds Initiate Unification

accellera SystemC Logo

Accellera, who brought us SystemVerilog, and the Open SystemC Imitative (OSCI), who brought us SystemC have made known their intent to unite to form a single front-end electronic design automation (EDA) standards organization.  You can read their joint press release here.

While this may come as a surprise to many, one thing has remained constant for many years: the two organizations have had a long standing policy of collaborative interactions as both have evolved their standards programs.  At a DATE 2004 panel titled “SystemC and SystemVerilog: Where do they fit?  Where are they going?,” technical members of the two communities gathered to ponder answers to those questions.  At DAC 2004, when I was chair of Accellera and Guido Arnout was chair of OSCI, we stood before a large assembly of SystemC users a few months later to point to what was not so obvious to many, SystemVerilog and SystemC complement each other.

DAC Slide 5

Guido and I dispelled any issues of a “language war” and focused on what the value each language and what it delivered to the design and verification community.  A lot has transpired since then.  Both SystemC and SystemVerilog are now IEEE standards, know as IEEE Std. 1666™ and IEEE Std. 1800™ respectively.  And both OSCI and Accellera have continued to evolve their standards work program in significant and meaningful ways.

In this evolution, it became clear to me that each organization was “completing” the other.  OSCI has developed the popular Transaction Level Modeling (TLM) standards and Accellera had adopted TLM in their Universal Verification Methodology (UVM™).  As the technical teams from each organization have leveraged each other, it began to make more sense to initiate discussions to unite the two groups to address further front-end EDA standards challenges – as one. And, indeed, the two organization recognized this and have taken the steps to determine how best to combine operations into a single organization.

In the months ahead, the unified organization will emerge, but for now, it is business as usual for the standards development teams in OSCI and Accellera.

What do you think about the unification?

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12 May, 2011

The standards developing organizations defining and updating front-end EDA standards will be at DAC in force.  And from the looks of if, they are getting an early start to DAC with updates on IEEE, Accellera and OSCI standards at Sunday workshops.  The Sunday workshops may be of particular interest to verification engineers interested in UVM and systems designers interested in SystemC AMS.

Following the workshops, there will be a half-day meeting of the North American SystemC Users Group on Monday where users will share their SystemC experiences.  The following morning, Accellera will host its annual DAC breakfast where the UVM users will meet to share their experiences.  A lively conversation is expected.

Sunday – June 5, 2011

UVM LogoDAC Workshop on Universal Verification Methodology (UVM) – Verifying Blocks to IP to SOCs and Systems

Time: 10:00 AM — 1:00 PM
Location: San Diego Convention Center Room 33A
Summary: The Accellera Verification IP Technical Subcommittee (VIP-TSC), building on over two years of work by verification experts from around the world, released Universal Verification Methodology (UVM) in February 2011. This workshop, presented by expert verification methodology architects and engineers, will provide an example-based overview of UVM to chip and SOC design and verification engineers of all skill levels on the first open-source verification methodology to be fully supported and endorsed by all major EDA vendors, and many end-user and consulting companies.
GET MORE DETAILS

Registration: This is an official DAC sponsored event and DAC registration required.


systemc_amsDAC Workshop on Using the Power of the SystemC AMS Extensions

Time: 10:00 AM — 6:00 PM
Location: San Diego Convention Center Room 33B
Summary: Today’s embedded systems interact more and more tightly with the analog physical environment; where digital HW/SW subsystems become functionally interwoven with analog/mixed-signal (AMS) blocks such as RF interfaces, power electronics, or sensors and actuators. Examples are software defined radios, sensor networks, automotive applications, or systems for image sensing. This requires new means to model and simulate the interaction between AMS subsystems and HW/SW subsystems at functional and architecture levels. Especially for this purpose, the SystemC language standard has been extended with powerful AMS capabilities to tackle the challenges in heterogeneous electronic system-level (ESL) design. You will get a good working knowledge of SystemC AMS by attending the workshop.
GET MORE DETAILS

Registration: This is an official DAC sponsored event and DAC registration required.

Monday – June 6, 2011

SystemC Logo

North American SystemC Users Group Meeting

Time: 8:30 AM – 12:00 PM
Location: OMNI Hotel
Room Salon AB
675 Laurel Street
San Diego, CA 92101
Summary: The North American SystemC Users Group  explores the newest advancements in sustainable and flexible solutions for system-level design using SystemC.
GET MORE DETAILS

Registration: This event is free and open to all registered DAC attendees. Click here to reserve your seat

Tuesday – June 7, 2011

accelleraAccellera Breakfast at DAC: UVM User Experiences

Time: 7:00 AM – 8:30 AM
Location: San Diego Convention Center Room 25AB
Summary: With the introduction of Accellera’s Universal Verification Methodology (UVM) user interest and adoption has been rapidly growing. You are invited to join us and share the experience with fellow users. During the breakfast, you will hear from real users who have migrated to, and/or applied, the UVM for the first time.  Accellera Verification IP Technical Subcommittee (VIP-TSC) participants will provide their insights on UVM. We invite you to take part in the open discussion to foster greater adoption of this important verification standard.
GET MORE DETAILS

Registration: This event is free open to all registered DAC attendees. Click here to reserve your seat

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7 June, 2010

After spending years verifying ASICs with dynamic simulation, I started working on static verification 10 years ago in a startup called 0-In Design Automation. I firmly believe that static verification can complement dynamic simulation. Static verification uses synthesis and formal technologies to find bugs in the design. It does not rely on simulation stimulus. You do not need to exercise the bugs, propagate the results, and check the outputs to detect them.

Static verification includes RTL lint, static checks, formal checks, automated and assertion-based formal property checking. To read more on static verification, you can take a look at my white paper: Getting Started With Static Verification. If you are interested in formal methods, you can take a look at Harry Foster’s white paper: Why Now for Formal Property Checking. Both can be found in the Knowledge Center of DAC.com.

In the future, we are going to talk about individual static verification technologies and its application in areas such as RTL verification, clock domain crossing verification, low power verification, timing constraint verification, etc. Your feedback and comments are most welcome.

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3 June, 2010

Visit Booth 1350 – The hub of OVM/UVM Activity at DAC

OVM_LogoThe OVM World booth at the Design Automation Conference (#1350) will feature user and partner presentations on OVM/UVM, a live discussion by prominent verification experts and a Tuesday cocktail reception from
4:30 p.m. to 6:00 p.m.

UVM_LogoThe Open Verification Methodology (OVM) is the industry’s open and  interoperable solution, guaranteed to run on multiple simulators, supporting multiple design languages, and is the basis for the Accellera UVM standard. The OVM enables scalability and reuse, fostering a vibrant verification ecosystem. OVMworld.org is the one-stop site for the OVM open-source library, documentation, and community contributions.

Featured half-hour presentations at the booth will include those listed below.  In addition to the presenting company and presentation title, full presentation abstracts can be found at http://www.ovmworld.org/tradeshows.php.

Monday (June 14th)

10 a.m.

Silicon Interfaces
OVM-based Verification Methodology VIP permits Silicon Interfaces to release Gigabit Ethernet MAC to industry with zero defect guarantee

11 a.m.

Accellera
VIP Technical Subcommittee Update

1 p.m.

Verilab
Simulation-Based FlexRay™ Conformance Testing – an OVM success story

2 p.m.

AMIQ
OVM Support in DVT

3 p.m.

Mentor Graphics & Cadence
OVM and UVM Update

4 p.m.

Nsys
SuperSpeed your USB 3.0 Verification with OVM based nSys Verification IP

5 p.m.

Duolog
OVM/UVM from a single spec

Tuesday (June 15th)

9 a.m.

Aldec
OVM/UVM for FPGAs: The End of Burn and Churn?

10 a.m.

Sunburst Design
Virtual Interface Techniques for OVM

1 p.m.

Xilinx
Beyond a common base class library: reduce work by reusing OVM agents on common interfaces

2 p.m.

Doulos
The Communication and Customization Mechanisms in OVM and UVM

3 p.m.

Mentor Graphics & Cadence
OVM and UVM Update

4 p.m.

Methodology Experts Discussion

5 p.m.

Cocktail Networking Event

Wednesday (June 16th)

9 a.m. Denali
Denali’s PureSpec: OVM-compatible VIP for bus and I/O protocols
10 a.m. Sibridge
Successful OVM deployment
11 a.m. Agnisys
Agile methods for OVM
2 p.m. TSMC
ESL to RTL Verification – Progressive Refinement and Reuse Paradigm.
TSMC Open Innovation Platform.
3 p.m. Mentor Graphics & Cadence
OVM and UVM Update
4 p.m. Agnisys
Automatic Generation of OVM Registers
5 p.m. Duolog
GNAT

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2 June, 2010

accellera UVM: Charting the New Territory

At this year’s DAC, Accellera introduces UVM (Universal Verification Methodology) to the world at its Tuesday breakfast and panel discussion.  While Accellera may call this “Charting the New Territory,” it is not terra incognita to Mentor Graphics nor to tens of thousands of OVM users.  UVM is at is simplest, just OVM.  If you know OVM; you know UVM.

While OVM and UVM are much alike, what is uncharted territory is how users will respond to and adopt UVM.  Unique to UVM is public support by the Big-3 EDA companies.  Other than that, nothing is really new for an OVM user.

What will be new next year at DAC 2011?  The Accellera panel abstract invites you to the breakfast to listen to a panel of expert verification engineers and methodology developers debate what they would like to see in UVM by DAC 2011.  And it encourages attendees to be vocal as well to share their views about what they would like to see by DAC 2011.

Breakfast Details

Tuesday, June 15, 2010
7:30 am – 9:00 a.m.
Anaheim Convention Center Room 203B

Please register for this event here

Moderator: Gabe Moretti, Gabe on EDA

Panelists:
Sharon Rosenberg, Cadence
Hillel Miller, Freescale
Mohamed Elmalaki, Intel
Tom Fitzpatrick, Mentor Graphics
Janick Bergeron, Synopsys
Stacey Secatch, Xilinx

On a light note: In prior DACs, the Accellera breakfast always seemed to follow the Denali party.  As you can imagine, a 7:30 a.m. start (or end to the night before) was always a challenge.  While many might have looked forward to break with tradition this year, we were informed by Denali that a second party (actually the first party if taken in chronological order) was being added.  For those who will register for a Denali party ticket, the Accellera breakfast will be a full breakfast to soak up any sins of the night before offered with plenty of coffee to wake you up.

I’ll see you at the Accellera breakfast and at the Denali party!

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